JP3094953B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a semiconductor device.

[0002]

2. Description of the Related Art Conventionally, flip chips have been used for connecting a chip and a package via solder bumps to reduce inductance parasitic on an electrical connection line and realize high-speed operation of a device. ing.

FIG. 6 is a plan view showing a pattern of a VCC wiring and a GND wiring on a chip used for a general flip chip. Chip 2 is connected to VCC wiring ring 15 and G
And an ND wiring ring 16. The plurality of VCC pads 11 are connected to the VCC wiring ring 15 via the VCC lead line 13. Similarly, a plurality of GND pads 12
Is the GND wiring ring 1 via the GND lead line 14.
6 is connected.

The VCC pad 11 has solder bumps 9 and is connected to the VCC plane of the package via the solder bumps 9. Similarly, the GND pad 12
Have solder bumps 10, and are connected to the GND plane of the package via the solder bumps 10. Such a method of bonding VCC or GND between a package and a chip via a solder bump has a feature that a parasitic inductance is small as compared with a bonding method using a bonding wire used in a general semiconductor device. This method is effective for suppressing conductive noise and for stably operating the device.

FIG. 7 is a sectional view taken along the line AB in FIG. The package 1 has a multilayer structure having a VCC plane 3 and a GND plane 4, and the VCC plane 3 is connected to a VCC plane.
The GND plane 4 is connected to the VCC land electrode 7 via the through-hole wiring 5, and the GND plane 4 is connected to the GND land electrode 8 via the GND through-hole wiring 6.

On the other hand, the chip 2 has V in the multilayer wiring layer 17.
It has a CC wiring ring 15 and a GND wiring ring 16. The VCC wiring ring 15 is connected to the VCC pad 11 through the VCC lead-out line 13, and the GND wiring ring 1
6 is connected to the GND pad 12 through the GND lead line 14. VCC land electrode 7 and VCC pad 1
1 is connected via a solder bump 9, and the GND land electrode 8 and the GND pad 12 are connected via a solder bump 10. The mechanism of electrically connecting the package and the pads on the chip via the solder bumps is the same for signal pads other than the VCC pads and the GND pads.

Conventionally, as shown in Japanese Patent Application Laid-Open No. Hei 5-114622, a semiconductor device of this type employs a VCC inner lead and a VSS inner lead by connecting a VCC inner lead and a VSS inner lead to a VCC pad on a chip and a VSS pad. By bonding the pads to the solder bumps, the parasitic inductance of the bonding portion is reduced as compared with the case of bonding wire bonding, and this is used for the purpose of suppressing pulsed power supply noise and stabilizing the operation.

[0008]

By using the above-described conventional semiconductor device having a flip chip structure,
By changing the bonding plane between the VCC plane of the package and the VCC pad on the chip, or between the GND plane and the GND pad, from the bonding wire bonding method to the solder bump bonding method, the parasitic inductance of the bonding part mainly concentrated on the bonding wire part Has been greatly reduced.

Referring to FIG. 7, a description will be given of a place where an inductance is generated on a VCC wiring path or a GND wiring path in the vicinity of a solder bump bonding portion by a conventional flip chip structure. In FIG. 7, the place where the parasitic inductance occurs on the electric path from the VCC plane 3 of the package to the VCC wiring ring 15 on the chip is determined by the VCC.
These are the locations of the through-hole wiring 5, the VCC land electrode 7, the solder bump 9, the VCC pad 11, and the VCC lead line 13. Among them, the VCC lead line 13 has the largest parasitic inductance.

Similarly, the GND lead 14 has the largest parasitic inductance on the wiring path from the GND plane 4 to the GND wiring ring 16. Generally, the parasitic inductance on the wiring increases in proportion to the wiring length, but is sufficiently small as compared with the parasitic inductance associated with the bonding wire, and has no effect even if ignored.

However, as the scale, speed, and power consumption of semiconductor devices have increased, it has become impossible to ignore the parasitic inductance remaining in the wiring on the chip even when the bump bonding method is employed. Was. As the power supply voltage for driving the device is reduced from 5 V to 3.3 V and 2.5 V, a slight change in the power supply voltage due to power supply noise has had a fatal effect on the stable operation of the device. In addition, power supply noise tends to be promoted due to the increase in device MHz and the accompanying increase in power consumption.
Increasingly, pulsed power supply noise due to parasitic inductance cannot be ignored.

SUMMARY OF THE INVENTION It is an object of the present invention to reduce a parasitic inductance remaining in a VCC wiring and a GND wiring in a semiconductor device in which a VCC and a GND wiring between a package and a chip are joined via solder bumps, and further suppress power supply noise. Another object of the present invention is to provide a semiconductor device in which high-speed operation is stabilized.

[0013]

In order to achieve the above object, a semiconductor device according to the present invention is a semiconductor device for connecting a VCC and a GND wiring between a package and a chip via solder bumps. In front of GND pad
On the same wiring layer as the VCC wiring and GND wiring on the chip
And put them in direct contact, and connect the VCC electrode and VCC through-hole wiring connected to the VCC wiring of the package, GND
A GND electrode and a GND through-hole wiring connected to the wiring are arranged so as to be located directly above the VCC pad and the GND pad, and the VCC pad and the GND pad of the chip are provided.
The VCC electrode and the GND electrode of the package are connected only by solder bumps.

A semiconductor device according to the present invention is a semiconductor device for connecting VCC and GND wiring between a package and a chip via solder bumps.
The ND pad is a VCC wiring and a GND wiring on the chip.
In the same wiring layer as the VCC wiring and the VCC path.
In this case, the GND wiring includes an area shared by
The GND pads may include a region shared with each other.
The VCC electrode and the GND through-hole wiring connected to the VCC wiring of the package and the GND electrode and the GND through-hole wiring connected to the GND wiring are connected to the VCC pad, G
It is arranged just above the ND pad, and the VCC pad and the GND pad of the chip, the VCC electrode of the package,
The GND electrode is connected only by solder bumps.

The VCC wiring or GND wiring is
They are arranged in a child shape .

[0016]

[0017]

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a diagram showing patterns of VCC and GND wirings in a semiconductor device according to Embodiment 1 of the present invention. In FIG. 1, the chip 2 is
It has a VCC wiring ring 15, a GND wiring ring 16, a plurality of VCC pads 11, and a plurality of GND pads 12.

A solder bump 9 is mounted on the VCC pad 11, and the package VC is connected via the solder bump 9.
Joined to C plane. Similarly, a solder bump 10 is mounted on the GND pad 12, and is connected to the GND plane via the solder bump 10. Further, the VCC pad 11 is in direct contact with the VCC wiring ring 15 without going through the VCC lead line. Similarly, the GND pad 12 directly connects to the GND without going through the GND lead line.
It is in contact with ND wiring ring 16.

As described above, the VCC pad 11 or the GND
The pad 12 is directly connected to the VCC wiring ring 15 or the GND wiring ring 16 so that solder between the VCC plane of the package and the VCC wiring ring on the chip or between the GND plane of the package and the GND wiring ring on the chip can be soldered. It becomes possible to join as close as possible via the bumps 9 and 10. The electrical path between the VCC plane and the VCC wiring ring or between the GND plane and the GND wiring ring will be described in detail with reference to FIG.

FIG. 2 is a sectional view taken along line AB of FIG. The structure shown in FIG. 2 corresponds to the VCC pad 11 or the GND pad 1
2 is arranged so as to be in direct contact with the VCC wiring ring 15 or the GND wiring ring 16 and the VCC of the package.
The present invention is characterized in that the land electrode 7 and the VCC through-hole wiring 5 or the GND land electrode 8 and the GND through-hole wiring 6 are arranged directly above the VCC pad or the GND pad.

VCC plane 3 and VCC wiring ring 15
Are only the VCC through-hole wiring 5, the VCC land electrode 7, the solder bump 9, and the VCC pad 11, and are electrically joined at a short distance. Similarly, between the GND plane 4 and the GND wiring ring 16, the GND through-hole wiring 6, the GND land electrode 8, and the solder bump 1 are formed.
0 and the GND pad 12 only, and are electrically joined at a very short distance.

Therefore, according to the first embodiment, between the conventional VCC pad on the chip and the VCC wiring ring or GN
It is possible to eliminate the parasitic inductance generated in the lead connecting the D pad and the GND wiring ring. Therefore, it is possible to suppress pulsed power supply noise generated on an electric path from the VCC plane of the package to the VCC wiring ring on the chip or from the GND plane of the package to the GND wiring ring on the chip. It is possible to operate stably at high speed.

In the first embodiment as well, from the VCC plane 3 to the VCC wiring ring or from the GND plane to G
Although a small amount of parasitic inductance exists on the electrical path to the ND wiring ring 16, it is sufficiently small as compared with the parasitic inductance generated in the conventional lead wire, and does not affect the operation of the chip.

(Embodiment 2) Next, Embodiment 2 of the present invention
Will be described with reference to the drawings.

FIG. 3 is a diagram showing patterns of VCC and GND wires in the semiconductor device according to the second embodiment of the present invention. The arrangement structure of the VCC pad or the GND pad in FIG. 3 is exactly the same as that of the first embodiment, ie, between the VCC plane and the VCC wiring ring or between the GND plane and the GND.
The effect of reducing the parasitic inductance between the wiring rings is the same.

However, in the second embodiment, the VCC wiring ring 15 or the GND wiring ring 16 is laid on the chip 2 vertically and horizontally in the form of a lattice so that the VCC pad 11
Alternatively, the second embodiment is different from the first embodiment in that the arrangement of the GND pad 12 on the chip 2 has a degree of freedom.

According to the second embodiment, the VCC pad 11
Alternatively, when arranging the GND pad 12 on the chip 2, a spatial restriction due to a layout arrangement of a semiconductor circuit unit formed on the chip or a spatial restriction upon forming a through-hole wiring of a package is required. An improvement effect equivalent to that of the first embodiment can be obtained without receiving it.

Embodiment 3 Next, Embodiment 3 of the present invention will be described with reference to the drawings.

FIG. 4 is a view showing patterns of VCC and GND wirings in the semiconductor device according to the third embodiment of the present invention. In the first embodiment, the VCC pad 11 or the GND
While the pad 12 is adjacent to the VCC wiring ring 15 or the GND wiring ring 16,
By arranging the C pad 11 or the GND pad 12 on the VCC wiring ring 15 or the GND wiring ring 16, the VCC pad 11 and the VCC wiring ring 15 or G
The ND pad 12 and the GND wiring ring 16 are shared.

That is, the chip 2 includes a VCC wiring ring 15, a GND wiring ring 16, and a plurality of VCC pads 11.
And a plurality of GND pads 12. Solder bumps 9 are mounted on the VCC pads 11, and are connected to the VCC plane 3 of the package via the solder bumps 9. Similarly, a solder bump 10 is mounted on the GND pad 12, and the GND of the package is connected via the solder bump 9.
It is joined to the D plane 4.

The VCC pad 11 is arranged directly on the VCC wiring ring 15 without going through the VCC lead line. Similarly, the GND pad 12 is directly disposed on the GND wiring ring 16 without going through the GND lead line. Such a VCC pad 11 or GND
The arrangement structure of the pad 12 is such that the solder bump 9 or the solder bump 10 is connected to the VCC wiring ring 15 or the GND wiring ring 16.
Mounted directly on top of the
Between the CC plane 3 and the VCC wiring ring 15 on the chip or between the GND plane 4 of the package and the GND on the chip
The wiring ring 16 can be bonded as close as possible via the solder bump.

The electrical path between the VCC plane and the VCC wiring ring or between the GND plane and the GND wiring ring will be described with reference to FIG.

FIG. 5 is a sectional view taken along line AB of FIG. In FIG. 5, the VCC wiring ring 15 or the GND wiring ring 1
6 differs from the other embodiments in that it is shared as a part of the VCC pad 11 or the GND pad 12.

VCC plane 3 and VCC wiring ring 15
The space between the VCC through hole wiring 5 and the VCC land electrode 7
And the solder bumps 9 alone, and are electrically joined at the shortest distance. Similarly, between the GND plane 4 and the GND wiring ring 16, only the GND through-hole wiring 6, the GND land electrode 8, the solder bump 10, and the GND pad 12 are provided, and are electrically connected at the shortest distance.

Therefore, it is possible to completely eliminate the parasitic inductance generated in the conventional lead line connecting between the VCC pad and the VCC wiring ring or between the GND pad and the GND wiring ring on the chip. for that reason,
High-speed and stable chips can be achieved by suppressing pulsed power noise generated on the electrical path from the package VCC plane to the VCC wiring ring on the chip or from the package GND plane to the GND wiring ring on the chip. It becomes possible to operate it. On the electrical path from the VCC plane 3 to the VCC wiring ring 15 or from the GND plane to the GND wiring ring 16,
Although there is still a small amount of parasitic inductance, it is sufficiently smaller than the parasitic inductance generated in the conventional lead wire, and does not affect the operation of the chip.

[0038]

As described above, according to the present invention, in a semiconductor device for connecting a VCC and a GND wiring between a package and a chip via solder bumps, the semiconductor device is left on the VCC wiring and the GND wiring on the chip. Parasitic inductance can be reduced. The reason is that VCC pad-VC
By arranging the VCC pad or the GND pad on the chip such that the length of the lead line between the C wiring ring or between the GND pad and the GND wiring ring is as short as possible,
Between the VCC plane of the package and the VCC wiring ring on the chip or between the GND plane of the package and the G on the chip
This is because the ND wiring rings are joined as close as possible via solder bumps.

Further, power supply noise of a semiconductor device having a flip-chip structure can be suppressed, and high-speed operation can be stabilized. The reason is that the parasitic inductance generated between the VCC plane of the package and the VCC wiring ring on the chip or on the electrical path between the GND plane and the GND wiring ring has been reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a sectional view taken along line AB in FIG.

FIG. 3 is a diagram showing a second embodiment of the present invention.

FIG. 4 is a diagram showing a third embodiment of the present invention.

FIG. 5 is a sectional view taken along line AB in FIG. 4;

FIG. 6 is a diagram of a VCC and GND wiring pattern on a chip used for a general flip chip.

FIG. 7 is a sectional view taken along line AB in FIG. 6;

[Explanation of symbols]

 1 Package 2 Chip 3 VCC plane 4 GND plane 5 VCC through-hole wiring 6 GND through-hole wiring 7 VCC land electrode 8 GND land electrode 9 VCC solder bump 10 GND solder bump 11 VCC pad 12 GND pad 13 VCC lead line 14 GND lead line 15 VCC wiring ring 16 GND wiring ring 17 Multi-layer wiring layer

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/60 H01L 21/60 311

Claims (3)

(57) [Claims] 1. A semiconductor device for connecting VCC and GND wiring between a package and a chip via solder bumps, wherein a VCC pad and a GND pad are connected to a VCC wiring on the chip.
Line and GND wiring on the same wiring layer and connect them directly.
Touch and connect the VCC electrode and VCC through hole wiring connected to the VCC wiring of the package, and the GND electrode and GN connected to the GND wiring.
D through-hole wiring is arranged so as to be located directly above the VCC pad and the GND pad, and the VCC pad and the GND pad of the chip are connected to the VCC electrode and the GND electrode of the package only by solder bumps. A semiconductor device, comprising: 2. A semiconductor device for joining a VCC and a GND wiring between a package and a chip via solder bumps, wherein the VCC pad and the GND pad are connected to a VC on the chip.
The same wiring layer as the C wiring and the GND wiring;
Including the area where the wiring and the VCC pad are shared with each other
Only, the GND wiring and the GND pad are shared with each other
And a GND electrode connected to the VCC wiring of the package and a GND electrode connected to the GND wiring and a GND electrode connected to the GND wiring.
The D through-hole wiring is arranged directly above the VCC pad and the GND pad, and the VCC pad and the GND pad of the chip are connected to the VCC electrode and the GND electrode of the package only by solder bumps. A semiconductor device characterized by the above-mentioned. 3. The semiconductor device according to claim 1, wherein the VCC wiring or the GND wiring is arranged in a lattice.