JPS60263450A - Integrated circuit package - Google Patents
Integrated circuit packageInfo
- Publication number
- JPS60263450A JPS60263450A JP59120165A JP12016584A JPS60263450A JP S60263450 A JPS60263450 A JP S60263450A JP 59120165 A JP59120165 A JP 59120165A JP 12016584 A JP12016584 A JP 12016584A JP S60263450 A JPS60263450 A JP S60263450A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- terminals
- insulating
- terminal
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は、集積回路を覆う絶縁性キャンプにこれを貫通
して電極部に固着する端子を設けた集積回路パンケージ
に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an integrated circuit pancage in which an insulating camp covering an integrated circuit is provided with terminals that penetrate through the insulating camp and are fixed to electrode portions.
従来、集積回路パッケージは、放熱のためにセラミック
基板の片面に放熱板を固着し、その反対面に集積回路を
搭載してその端子に基板内配線を介してセラミック基板
上の入出力端子を設けた構成である。Conventionally, integrated circuit packages have a heat dissipation plate fixed to one side of a ceramic substrate for heat dissipation, an integrated circuit mounted on the other side, and input/output terminals on the ceramic substrate connected to the terminals via wiring inside the substrate. The configuration is as follows.
しかしながら、セラミック基板上の複数の入出力端子は
、コネクター等の接続のため一定間隔を以って離間配置
される必要があるため、これにより、セラミック基板は
一定の面積以上に限定されてしまい、集積回路パッケー
ジの小型化が困難であった。However, the plurality of input/output terminals on the ceramic substrate need to be spaced apart from each other to connect connectors, etc., so the ceramic substrate is limited to a certain area or more. It has been difficult to miniaturize integrated circuit packages.
本発明は、上記問題点を解決するもので、集積回路を覆
う絶縁性キャップにこれを貫通して電極部に固着する端
子を設けることにより、絶縁基板上の端子数の誠少を図
ジ、絶縁基板の面積を小さくなし、パッケージ全体を小
型化しうる集積回路パンケージを提供することを目的と
する。The present invention solves the above-mentioned problems and reduces the number of terminals on an insulating substrate by providing terminals that penetrate through the insulating cap that covers the integrated circuit and are fixed to the electrode parts. An object of the present invention is to provide an integrated circuit package that can reduce the area of an insulating substrate and downsize the entire package.
本発明の目的を達成するための、本発明に係る集積回路
パッケージの構成は、絶縁性基板上に設けた集積回路と
、集積回路の端子に配線を介して接続する絶縁基板上の
第１の端子とを有する集積回路パッケージにおいて、集
積回路の端子に接続する電極部を絶縁性基板上に設ける
と共に、集積回路を覆う絶縁性キャップを設け、絶縁性
キャンプにこれを貫通して電極部に固着した第２の端子
を設けてなるものである。To achieve the object of the present invention, the structure of the integrated circuit package according to the present invention includes an integrated circuit provided on an insulating substrate, and a first integrated circuit provided on the insulating substrate connected to terminals of the integrated circuit via wiring. In an integrated circuit package having a terminal, an electrode part connected to the terminal of the integrated circuit is provided on an insulating substrate, an insulating cap is provided to cover the integrated circuit, and the cap is passed through the insulating camp and fixed to the electrode part. A second terminal is provided.
次に、本発明の一実施例を図面に基づいて説明する。 Next, one embodiment of the present invention will be described based on the drawings.
第１図は、本発明に係る集積回路パッケージの一実施例
を示す分解斜視図である。FIG. 1 is an exploded perspective view showing an embodiment of an integrated circuit package according to the present invention.
第２図は、同実施例の断面図である。FIG. 2 is a sectional view of the same embodiment.
図中、１０は絶縁性基板としてのセラミック基板で、そ
の片面上中央には集積回路２０が搭載されている。１１
はセラミック基板ｌＯの周縁部に一定間隔ごとに植設さ
れた第１の端子としての入力出端子であり、これらは集
積回路加の所定の端子とボンディングワイヤ２１、ポン
ディングパッド２２、基板内配線（図示せず）を介して
接続されている。In the figure, 10 is a ceramic substrate serving as an insulating substrate, and an integrated circuit 20 is mounted on the center of one side of the ceramic substrate. 11
are input/output terminals as first terminals implanted at regular intervals on the periphery of the ceramic substrate IO, and these are connected to predetermined terminals of the integrated circuit, bonding wires 21, bonding pads 22, and wiring within the substrate. (not shown).
１２は集積回路加の周囲に設けられた電極部で、集積回
路２００所定端子とボンディングワイヤ１３、ポンディ
ングパッド１４を介して接続されている。Reference numeral 12 denotes an electrode portion provided around the integrated circuit, and is connected to a predetermined terminal of the integrated circuit 200 via a bonding wire 13 and a bonding pad 14.
４０は集積回路２０を覆いこれを保護する絶縁性キャッ
プである。４１線、この絶縁性キャップにこれを貫通し
て植設された第２の端子としての絶縁性キャップの端子
で、フランジ状の下部４１ａを有する。各々の端子４１
は、絶縁性キャンプ４０を絶縁性基板１０に接着固定し
た際、下部４１＆が夫々電極部【２に衝合するよう配設
されており、下部４１ａと電極部１２の固着は、絶縁性
キャップ４０を絶縁性基板■０に接着するとき同時に加
熱半田付けにより行なわれる。40 is an insulating cap that covers and protects the integrated circuit 20. 41 wire, which is a terminal of the insulating cap as a second terminal implanted through the insulating cap, and has a flange-shaped lower part 41a. Each terminal 41
When the insulating camp 40 is adhesively fixed to the insulating substrate 10, the lower part 41& is arranged so as to abut against the electrode part [2], and the fixing of the lower part 41a and the electrode part 12 is done by the insulating cap 40. At the same time as bonding the insulating substrate (1) to the insulating substrate (2), heat soldering is performed.
なお、３０はセラミック基板１０の裏面に固着された放
熱板である。Note that 30 is a heat sink fixed to the back surface of the ceramic substrate 10.
このように、集積回路２０を覆う絶縁性キャップ４０を
設け、集積回路加の端子に接続する電極部１２に対し固
着される端子４１を絶縁性キャンプ４０にこれを貫通さ
せて設けた構造であるから、端子４１の数の分だけセラ
ミック基板ＩＯ上に直接植設する端子１１の数を減らす
ことができる。これによシセラミック基板１０の面積を
減らすことができ、パンケージを小型化しうる。またセ
ラミック基板ＩＯの周縁部までの基板内配線が減少する
から、この分、セラミック基板の面積を減らすことがで
き、更に一層パンケージの小型化を図りうる。In this way, the insulating cap 40 covering the integrated circuit 20 is provided, and the terminal 41, which is fixed to the electrode part 12 connected to the terminal of the integrated circuit, is provided by penetrating the insulating cap 40. Therefore, the number of terminals 11 directly implanted on the ceramic substrate IO can be reduced by the number of terminals 41. As a result, the area of the ceramic substrate 10 can be reduced, and the pan cage can be made smaller. Furthermore, since the wiring within the substrate up to the periphery of the ceramic substrate IO is reduced, the area of the ceramic substrate can be reduced accordingly, and the size of the pancage can be further reduced.
以上説明したように本発明に係る集積回路パッケージに
よれば、集積回路の端子に接続する電極部を絶縁性基板
上に設けると共に、集積回路を覆う絶縁性キャップを設
け、絶縁性キャンプにこれを貫通して電極部に固着した
第２の端子を設けた点に特徴を有するため、集積回路の
上部スペースを有効利用しておシ、絶縁性基板の端子の
数を減らすことができ、この分、絶縁性基板の面積を小
さくできるから、集積回路パッケージを小型化、高密度
化しうるという効果を奏する。As explained above, according to the integrated circuit package according to the present invention, the electrode portion connected to the terminal of the integrated circuit is provided on the insulating substrate, an insulating cap is provided to cover the integrated circuit, and this is placed in the insulating camp. The feature is that a second terminal is provided that penetrates and is fixed to the electrode part, so the upper space of the integrated circuit can be used effectively, and the number of terminals on the insulating substrate can be reduced. Since the area of the insulating substrate can be reduced, the integrated circuit package can be made smaller and more dense.
第１図は、本発明に係る集積回路パッケージの一実施例
を示す分解斜視図である。
第２図線、同実施例の断面図である。
１０・・・セラミック基板
１１・・・第１の端子としての入力出端子■２・・・電
極部
１３ 、２１・・・ボンディングワイヤ１４ 、２２・
・・ポンディングパッド２０・・・集積回路 ３０・・
・放熱板４０・・・絶縁性キャップ
４１・・・第２の端子としての絶縁性キャップの端子
４１ａ・・・フランジ状下部
出願人 日本電気株式会社
２１７−FIG. 1 is an exploded perspective view showing an embodiment of an integrated circuit package according to the present invention. FIG. 2 is a sectional view of the same embodiment. DESCRIPTION OF SYMBOLS 10... Ceramic substrate 11... Input/output terminal as a first terminal ■2... Electrode portion 13, 21... Bonding wire 14, 22...
...Ponding pad 20...Integrated circuit 30...
- Heat sink 40...Insulating cap 41...Terminal 41a of the insulating cap as a second terminal...Flanged bottom Applicant NEC Corporation 217-
Claims (1)
に配線を介して接続する前記絶縁基板上の第１の端子と
を有する集積回路パッケージにおいて、前記集積回路の
端子に接続する電極部を前記絶縁性基板上に設けると共
に、前記集積回路を覆う絶縁性キャップを設け、前記絶
縁性キャンプにこれを貫通して前記電極部に固着した第
２の端子を設けてなることを特徴とする集積回路パッケ
ージ。An integrated circuit package having an integrated circuit provided on an insulating substrate and a first terminal on the insulating substrate connected to the terminal of the integrated circuit via wiring, an electrode portion connected to the terminal of the integrated circuit. is provided on the insulating substrate, an insulating cap is provided to cover the integrated circuit, and a second terminal is provided in the insulating camp through the cap and fixed to the electrode section. integrated circuit package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59120165A JPS60263450A (en) | 1984-06-12 | 1984-06-12 | Integrated circuit package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59120165A JPS60263450A (en) | 1984-06-12 | 1984-06-12 | Integrated circuit package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60263450A true JPS60263450A (en) | 1985-12-26 |
Family
ID=14779552
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59120165A Pending JPS60263450A (en) | 1984-06-12 | 1984-06-12 | Integrated circuit package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60263450A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5097318A (en) * | 1988-04-04 | 1992-03-17 | Hitachi, Ltd. | Semiconductor package and computer using it |
| US8629566B2 (en) * | 2000-03-17 | 2014-01-14 | International Rectifier Corporation | Semiconductor multichip module package with improved thermal performance; reduced size and improved moisture resistance |
-
1984
- 1984-06-12 JP JP59120165A patent/JPS60263450A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5097318A (en) * | 1988-04-04 | 1992-03-17 | Hitachi, Ltd. | Semiconductor package and computer using it |
| US8629566B2 (en) * | 2000-03-17 | 2014-01-14 | International Rectifier Corporation | Semiconductor multichip module package with improved thermal performance; reduced size and improved moisture resistance |
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