JPH01278031A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01278031A JPH01278031A JP63108110A JP10811088A JPH01278031A JP H01278031 A JPH01278031 A JP H01278031A JP 63108110 A JP63108110 A JP 63108110A JP 10811088 A JP10811088 A JP 10811088A JP H01278031 A JPH01278031 A JP H01278031A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- die pad
- die
- wire bonding
- pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 238000000034 method Methods 0.000 abstract 2
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、電極機能を有するダイパッドと、前記ダイ
パッド上に絶縁して固定された半導体チップを有する樹
脂封止型半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a resin-sealed semiconductor device having a die pad having an electrode function and a semiconductor chip insulated and fixed onto the die pad.
第４図は従来の電極機能を有するダイパッドと、前記ダ
イパッド上に絶縁して固定された半導体チップを有する
樹脂封止型半導体装置を示す上面図、第５図は第４図の
Ｉ−Ｉ断面図である。これらの図に示すように、電極機
能を有するダイパッド１の所定領域上に半導体チップ２
が絶縁ダイボンド３により固定されている。半導体チッ
プ２上には信号線（電源線、接地線を含む）５が設けら
れている。また、４は半導体チップ２の周囲に樹脂封止
で固定されているリードフレームであり、これらのリー
ドフレーム４及びダイパッド１は、各々の１箇所のワイ
ヤボンディング領域４ａ、１ａ、から１本のワイヤ６に
より半導体チップ２上のポンディングパッド７を介し電
気的に接続される。FIG. 4 is a top view showing a conventional resin-sealed semiconductor device having a die pad having an electrode function and a semiconductor chip insulated and fixed on the die pad, and FIG. 5 is a cross section taken along the line II in FIG. It is a diagram. As shown in these figures, a semiconductor chip 2 is placed on a predetermined area of a die pad 1 having an electrode function.
is fixed by an insulating die bond 3. Signal lines (including a power line and a ground line) 5 are provided on the semiconductor chip 2 . Further, 4 is a lead frame fixed around the semiconductor chip 2 by resin sealing, and these lead frames 4 and the die pad 1 each have one wire from one wire bonding area 4a, 1a. 6 is electrically connected via a bonding pad 7 on the semiconductor chip 2.
従来の電極機能を有するダイパッドを備えた樹脂封止型
の半導体装置は以上のように構成されており、リードフ
レーム４及びダイパッド１には各々ワイヤボンディング
領域４ａ、ｌａが１箇所しか設けられていない。このた
め、ワイヤボンディング領［４ａ、１ａから比較的遠い
半導体チップ −２の領域からリードフレーム４ある
いはダイパッド１との電気的接続を行う必要がある場合
、半導体チップ２内に信号配線を施しリードフレーム４
あるいはダイパッド１に近いポンディングパッド７に接
続し、このポンディングパッド７を介してワイヤボンデ
ィングを行なうことで補う必要があった。その結果、半
導体チップ２内に必要以上に長い信号線を配線すること
になり、半導体チップ２面積の増大等の集積度の低下、
信号配線間のノイズの増大を招くという問題点があった
。A conventional resin-sealed semiconductor device equipped with a die pad having an electrode function is configured as described above, and the lead frame 4 and the die pad 1 are each provided with only one wire bonding area 4a, la. . Therefore, if it is necessary to make an electrical connection to the lead frame 4 or the die pad 1 from the area of the semiconductor chip 2 which is relatively far from the wire bonding area 4a, 1a, signal wiring is provided within the semiconductor chip 2 and the lead frame 4
Alternatively, it was necessary to compensate by connecting to a bonding pad 7 near the die pad 1 and performing wire bonding via this bonding pad 7. As a result, unnecessarily long signal lines are wired inside the semiconductor chip 2, resulting in a decrease in the degree of integration such as an increase in the area of the semiconductor chip 2, etc.
There is a problem in that noise between signal lines increases.
この発明は上記のような問題点を解決するためになされ
たもので、半導体チップ内の信号線の配線量を低減化で
きる半導体装置を得ることを目的とする。The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor device that can reduce the amount of signal lines in a semiconductor chip.
この発明にかかる半導体装置は、電極機能を有するダイ
パッドと、前記ダイパッド上に絶縁して固定された半導
体チップを有し、前記ダイパッド上における前記半導体
チップとのワイヤボンディング領域を複数個設けている
。A semiconductor device according to the present invention includes a die pad having an electrode function, a semiconductor chip insulated and fixed on the die pad, and a plurality of wire bonding regions with the semiconductor chip on the die pad.
この発明における電極機能を有するダイパッドは、半導
体チップとのワイヤボンディング領域を複数個設けたた
め、ダイパッドと接続する必要がある半導体チップ上の
領域との接続をいずれのワイヤボンディング領域で行う
かを選択できる。The die pad having an electrode function in this invention has a plurality of wire bonding areas with the semiconductor chip, so that it is possible to select which wire bonding area should be used to connect the die pad to the area on the semiconductor chip that needs to be connected. .
第１図はこの発明の一実施例である半導体装置を示す上
面図、第２図はその■−■断面図である。FIG. 1 is a top view showing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line 1--2.
従来と異なり、互いに絶縁された２つのダイパッド１０
．１１各々の所定領域上に半導体チップ２が絶縁ダイボ
ンド３により固定されている。これらのダイパッド１０
．１１は各々ワイヤボンディング領域を（１０ａ、１０
ｂ）、（１１ａ、１１ｂ）と２箇所ずつ有している。Unlike conventional methods, two die pads 10 are insulated from each other.
．． A semiconductor chip 2 is fixed onto a predetermined area of each of the semiconductor chips 11 by an insulating die bond 3. These die pads 10
．． 11 designates wire bonding areas (10a, 10
b) and (11a, 11b).
また、信号線１２ａをポンディングパッド７ａを介して
ダイパッド１０のワイヤボンディング領域１０ａとワイ
ヤ６で接続し、信号線１２ｂをポンディングパッド７ｂ
を介してダイパッド１０のワイヤボンディング領域１０
ｂとワイヤ６で接続している。このため、信号線１２ａ
、１２ｂの電気的接続をダイパッド１０により行うこと
ができ、半導体チップ２内の内部配線により信号線１２
ａ。Further, the signal line 12a is connected to the wire bonding area 10a of the die pad 10 via the bonding pad 7a with the wire 6, and the signal line 12b is connected to the bonding area 10a of the die pad 10 via the bonding pad 7b.
Wire bonding area 10 of die pad 10 via
b with wire 6. Therefore, the signal line 12a
, 12b can be electrically connected by the die pad 10, and the signal lines 12 can be electrically connected by internal wiring within the semiconductor chip 2.
a.
１２ｂを接続する必要がなくなる。その結果、半導体チ
ップ２内に形成すべき信号線１２（１２ａ。There is no need to connect 12b. As a result, the signal lines 12 (12a) to be formed within the semiconductor chip 2.
１２ｂ）の信号配線量の低減化が図れ、半導体チップ２
の面積の増大等による集積度の低下、信号配線間のノイ
ズの増大を回避できる。12b), the amount of signal wiring can be reduced, and the semiconductor chip 2
It is possible to avoid a decrease in the degree of integration due to an increase in area, etc., and an increase in noise between signal wirings.
信号線１３ （１３ａ、１３ｂ）も同様に（８号［１１
３ａとダイパッド１１のワイヤボンディング領１ｉ１！
１１ａをポンディングパッド７ｃを介してワイヤ６で接
続し１．信号線１３ｂとダイパッド１１のワイヤボンデ
ィング領域１１ｂをポンディングパッド７ｄを介してワ
イヤ６で接続することで、半導体チップ２内の信号線１
３の信号配Ｉｌ開が低減化できる。Similarly, the signal lines 13 (13a, 13b) (No. 8 [11
Wire bonding area 1i1 between 3a and die pad 11!
11a by the wire 6 via the bonding pad 7c.1. By connecting the signal line 13b and the wire bonding region 11b of the die pad 11 with the wire 6 via the bonding pad 7d, the signal line 1 in the semiconductor chip 2
The signal distribution Il opening of No. 3 can be reduced.
なお、この実施例では、２つのダイパッド上に各々２つ
のワイヤボンディング領域を設けた例を示したが、１つ
のダイパッド上に複数のワイヤボンディング領域を有し
ておれば、ダイパッドの数は従来同様１つでも、第３図
に示すように４つでもよく、限定されない。なお、第３
図において、２０〜２３はダイパッド、２０ａ〜２３ａ
、２０ｂ〜２３ｂはワイヤボンディング領域である。ま
た、リードフレーム、ダイパッドの形状も実施例に限定
されるものではない。Although this embodiment shows an example in which two wire bonding areas are provided on each of two die pads, if a plurality of wire bonding areas are provided on one die pad, the number of die pads can be the same as before. There may be one, or there may be four as shown in FIG. 3, and the number is not limited. In addition, the third
In the figure, 20 to 23 are die pads, 20a to 23a
, 20b to 23b are wire bonding regions. Furthermore, the shapes of the lead frame and die pad are not limited to the embodiments.
以上説明したように、この発明によれば、電極機能を有
するダイパッドが半導体チップとのワイヤボンディング
領域を複数個有しているため、半導体チップ内の信号線
の配線量を低減化できる効果がある。As explained above, according to the present invention, since the die pad having an electrode function has a plurality of wire bonding regions with the semiconductor chip, it is possible to reduce the amount of wiring of signal lines in the semiconductor chip. .
【図面の簡単な説明】
第１図はこの発明の一実施例である樹脂封止型半導体装
置を示す上面図、第２図は第１図の半導体装置の■−■
断面図、第３図はこの発明の他の実施例である樹脂封止
型半導体装置を示す上面図、第４図は従来の樹脂封止型
半導体装置を示す上面図、第５図は第４図で示した半導
体装置のＩ−Ｉ断面図である。
図において、２は半導体チップ、１０．１１はダイパッ
ド、１０ａ、１０ｂ、１１ａ、１１ｂはワイヤボンディ
ング領域、１２（１２ａ、１２ｂ）、１３ （１３ａ、
１３ｂ）Ｇ、を信号線である。
なお、各図中同一符号は同一または相当部分を示す。
代理人 大 岩 増 雄
第１図
第２図
第３ＷＡ
第４図
第５ＷＪBRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a top view showing a resin-sealed semiconductor device according to an embodiment of the present invention, and FIG. 2 is a top view of the semiconductor device shown in FIG. 1.
3 is a top view showing a resin-sealed semiconductor device according to another embodiment of the present invention, FIG. 4 is a top view showing a conventional resin-sealed semiconductor device, and FIG. 5 is a top view showing a conventional resin-sealed semiconductor device. FIG. 2 is a sectional view taken along line II of the semiconductor device shown in the figure. In the figure, 2 is a semiconductor chip, 10.11 is a die pad, 10a, 10b, 11a, 11b are wire bonding regions, 12 (12a, 12b), 13 (13a,
13b) G is a signal line. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa Figure 1 Figure 2 Figure 3 WA Figure 4 Figure 5 WJ
Claims (1)
有する半導体装置において、 前記ダイパッド上における前記半導体チップとのワイヤ
ボンディング領域を複数個設けたことを特徴とする半導
体装置。(1) A semiconductor device having a die pad having an electrode function and a semiconductor chip insulated and fixed on the die pad, characterized in that a plurality of wire bonding areas with the semiconductor chip are provided on the die pad. Semiconductor equipment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63108110A JPH01278031A (en) | 1988-04-28 | 1988-04-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63108110A JPH01278031A (en) | 1988-04-28 | 1988-04-28 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01278031A true JPH01278031A (en) | 1989-11-08 |
Family
ID=14476148
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63108110A Pending JPH01278031A (en) | 1988-04-28 | 1988-04-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01278031A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6538306B1 (en) * | 1999-07-02 | 2003-03-25 | Rohm Co., Ltd. | Electronic part |
-
1988
- 1988-04-28 JP JP63108110A patent/JPH01278031A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6538306B1 (en) * | 1999-07-02 | 2003-03-25 | Rohm Co., Ltd. | Electronic part |
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