JPH04151842A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH04151842A
JPH04151842A JP2277490A JP27749090A JPH04151842A JP H04151842 A JPH04151842 A JP H04151842A JP 2277490 A JP2277490 A JP 2277490A JP 27749090 A JP27749090 A JP 27749090A JP H04151842 A JPH04151842 A JP H04151842A
Authority
JP
Japan
Prior art keywords
bonding
semiconductor chip
wire
wires
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2277490A
Other languages
Japanese (ja)
Inventor
Hiroyuki Fukuda
浩之 福田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2277490A priority Critical patent/JPH04151842A/en
Publication of JPH04151842A publication Critical patent/JPH04151842A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/4556—Disposition, e.g. coating on a part of the core
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45565—Single coating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To miniaturize a semiconductor chip by performing wire bonding by using insulatively coated bonding wires. CONSTITUTION:After a semiconductor chip 4 is die-bonded to a package, an inner lead 1 of the package and a bonding pad 3 formed on a semiconductor chip 4 are connected by using an insulatively coated bonding wire 5. As a result, when the bonding wires intersect with each other, short circuitting is not generated, because the wires are covered with insulative coating 6. Thereby the position of the bonding pad 3 can be comparatively arbitrarily selected, so that the area of a semiconductor chip can be reduced.

Description

【発明の詳細な説明】 ［産業上の利用分野］ この発明は、半導体装置の内部のワイヤボンディングに
関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to wire bonding inside a semiconductor device.

［従来の技術］ 第３図はＺＩＰ（Ｚｉｇ−Ｚａｇ　Ｉｎ１ｉｎｅ　Ｐａ
ｃｋ　ａｇｅ）にワイヤボンディングされた従来の半導
体装置内部の平面図、第４図は第３図に示すＡ−Ａにお
ける拡大断面図である。[Prior art] FIG. 3 shows a ZIP (Zig-Zag Inline Pa
FIG. 4 is an enlarged cross-sectional view taken along line A-A shown in FIG. 3.

図において、（１）はインナーリード、（２）はホンデ
ィングワイヤ、（３）はボンディングパット、（４）は
半導体チップである。In the figure, (1) is an inner lead, (2) is a bonding wire, (3) is a bonding pad, and (4) is a semiconductor chip.

次に動作について説明する。Next, the operation will be explained.

半導体チップ（４）はパッケージにダイボンディングさ
れた後、パッケージのインナーリート（１）と、半導体
チップ（４）上に形成されたポンディングパッド（３）
との間を、金線超音波併用熱圧着ポールボンディング方
式、アルミ線超音波ウェッジボンディング方式又は銅線
超音波併用熱圧着ポールボンディング方式などにより、
金属性のポールボンディングワイヤ（２）を用いて結線
される。After the semiconductor chip (4) is die-bonded to the package, the inner reel (1) of the package and the bonding pad (3) formed on the semiconductor chip (4) are bonded.
The connection between the
The wires are connected using a metal pole bonding wire (2).

［発明が解決しようとする課題］ 従来の半導体装置は以上のように構成されているので、
ボンディングワイヤか封止樹脂の応力などによって流れ
てショートしたり、ボンデングワイヤが交差しないよう
に結線しなければならす、ピン数の多いＺＩＰなとは、
ボンデングパッドの方向性が決められ、半導体チップの
面積がさらに大きくなるなどの問題点があった。[Problem to be solved by the invention] Since the conventional semiconductor device is configured as described above,
ZIPs with a large number of pins must be connected so that the bonding wires do not flow due to the stress of the bonding wire or the sealing resin, resulting in a short circuit, or that the bonding wires do not cross.
There were problems such as the directionality of the bonding pads being determined and the area of the semiconductor chip becoming larger.

この発明は上記のような問題点を解決するためになされ
たもので、ボンデングワイヤが交差してもショートの原
因とならす、又、半導体チップの小型化が可能である半
導体装置を得ることを目的とする。This invention was made in order to solve the above-mentioned problems, and aims to provide a semiconductor device in which even if the bonding wires cross, it causes a short circuit, and in which the size of the semiconductor chip can be reduced. purpose.

［課題を解決するための手段］ この発明に係る半導体装置は、絶縁被覆されたボンデン
グワイヤで結線したものである。[Means for Solving the Problems] A semiconductor device according to the present invention is connected by bonding wires coated with insulation.

［作　用］ この発明における半導体装置は、絶縁被覆されたボンデ
ングワイヤで交差するようにワイヤホンデングしても、
電気的にショートの原因とならない。[Function] Even if the semiconductor device of the present invention is bonded with insulation-covered bonding wires so as to cross each other,
Does not cause electrical shorts.

［実施例］ 以下、この発明の一実施例を図について説明する。第１
図はＺＩＰにワイヤホンデングされた半導体装置の内部
の平面図、第２図は第１図に示すＢ・Ｂにおける拡大断
面図である。図において（１）、（３）、（４）は第３
図の従来例に示したものと同等でおるので説明を省略す
る。（５）は絶縁被覆されたボンデングワイヤ（６）は
ボンデングワイヤ（５）の絶縁被覆である。[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
The figure is a plan view of the inside of a semiconductor device wire-bonded to a ZIP, and FIG. 2 is an enlarged sectional view taken along line B-B shown in FIG. In the figure, (1), (3), and (4) are the third
Since it is the same as that shown in the conventional example in the figure, the explanation will be omitted. The bonding wire (6) coated with insulation (5) is the insulation coating of the bonding wire (5).

に動作について説明する。半導体チップ（４）は、パッ
ケージにグイホンティングされた後、パッテ−ジのイン
ナーリート（１）と、半導体チップ（４）上に形成され
たホンデングバット（３）との間を、金線超音波併用熱
圧着ホールホンディング方式、アルミ線超音波ウェッジ
ホンディング方式又は、銅線超音波併用熱圧着ホールホ
ンディング方式なとにより、ホンディングワイヤ（５）
を用いて結線される。第１図に示すようにホンディング
ワイヤ（５）か交差しても、絶縁被覆（６）で覆われて
いるので、電気的にショートにはならない。The operation will be explained below. After the semiconductor chip (4) is glued into a package, a gold wire is connected between the inner reel (1) of the package and the real butt (3) formed on the semiconductor chip (4). Honing wire (5) by using the ultrasonic thermocompression hole honding method, the aluminum wire ultrasonic wedge bonding method, or the copper wire ultrasonic thermocompression hole honding method.
The wires are connected using As shown in FIG. 1, even if the wires (5) cross each other, they are covered with an insulating coating (6) so that no electrical short circuit occurs.

なお、上記実施例ではＺＴＰの場合について説明したが
、どのような形状のパッケージであってもよく、上記実
施例と同様の効果を奏する。In the above embodiment, a ZTP case has been described, but any shape of the package may be used and the same effects as in the above embodiment can be obtained.

［発明の効果］ 以上のように、この発明によれば、絶縁被覆されたボン
ディングワイヤでワイヤボンディングしたので、ボンデ
ィングワイヤか樹脂の応力により流れてショーＩ・する
を防くことかてき、ボンディングワイヤを交差させて使
用できるので、例えばＺＴＰなとの様に、従来半導体チ
ップの片側にホンディングパットか集中するのに対し、
比較的任意にホンディングパットの位置を選択すること
かてきるのて、信頼性のみならす、半導体チ・ノブ面積
の縮小化がおこなえる効果がある。[Effects of the Invention] As described above, according to the present invention, since wire bonding is performed using an insulated bonding wire, it is possible to prevent the bonding wire from flowing and showing due to the stress of the resin. Because it can be used in a crossed manner, for example in ZTP, unlike conventionally, the honking pads are concentrated on one side of the semiconductor chip,
By selecting the position of the padding relatively arbitrarily, it is possible to not only improve reliability but also to reduce the area of the semiconductor chip/knob.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの発明の一実施例によるＺＩＰにワイヤボン
ディングされた半導体装置の内部の平面図第２図は第１
図に示すＢ−Ｂにおける拡大断面図、第３図はＺＩＰに
ワイヤボンディングされた従来の半導体装置の内部の平
面図、第４図は第３図に示すＡ−Ａにおける拡大断面図
である。 図において、（１）はインナーリート、（３）はボンデ
ィングバット、（４）は半導体チップ、（５）はボンテ
ィングワイヤ、（６）は絶縁被覆である。 なお、図中、同一符号は同一、又は相当部分を示す。FIG. 1 is a plan view of the inside of a semiconductor device wire-bonded to a ZIP according to an embodiment of the present invention.
3 is a plan view of the interior of a conventional semiconductor device wire-bonded to a ZIP, and FIG. 4 is an enlarged sectional view taken along line AA shown in FIG. 3. In the figure, (1) is an inner lead, (3) is a bonding butt, (4) is a semiconductor chip, (5) is a bonding wire, and (6) is an insulating coating. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] 半導体装置をアセンブリするに際して、絶縁被覆された
ボンディングワイヤでワイヤボンディングしたことを特
徴とする半導体装置。A semiconductor device characterized in that wire bonding is performed using an insulated bonding wire when assembling the semiconductor device.
JP2277490A 1990-10-15 1990-10-15 Semiconductor device Pending JPH04151842A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2277490A JPH04151842A (en) 1990-10-15 1990-10-15 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2277490A JPH04151842A (en) 1990-10-15 1990-10-15 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH04151842A true JPH04151842A (en) 1992-05-25

Family

ID=17584326

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2277490A Pending JPH04151842A (en) 1990-10-15 1990-10-15 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH04151842A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10129006A1 (en) * 2001-06-15 2003-01-02 Conti Temic Microelectronic Electronic module e.g. for motor vehicle controls, has part of bonding links formed by bonding wire provided with insulating layer
JP2007088453A (en) * 2005-09-23 2007-04-05 Freescale Semiconductor Inc Method of manufacturing stack die package

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10129006A1 (en) * 2001-06-15 2003-01-02 Conti Temic Microelectronic Electronic module e.g. for motor vehicle controls, has part of bonding links formed by bonding wire provided with insulating layer
DE10129006B4 (en) * 2001-06-15 2009-07-30 Conti Temic Microelectronic Gmbh Electronic module
JP2007088453A (en) * 2005-09-23 2007-04-05 Freescale Semiconductor Inc Method of manufacturing stack die package

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