JPH04151842A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04151842A JPH04151842A JP2277490A JP27749090A JPH04151842A JP H04151842 A JPH04151842 A JP H04151842A JP 2277490 A JP2277490 A JP 2277490A JP 27749090 A JP27749090 A JP 27749090A JP H04151842 A JPH04151842 A JP H04151842A
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- semiconductor chip
- wire
- wires
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 239000011248 coating agent Substances 0.000 abstract description 4
- 238000000576 coating method Methods 0.000 abstract description 4
- 238000009413 insulation Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/4554—Coating
- H01L2224/4556—Disposition, e.g. coating on a part of the core
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/4554—Coating
- H01L2224/45565—Single coating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/4554—Coating
- H01L2224/45599—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
この発明は、半導体装置の内部のワイヤボンディングに
関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to wire bonding inside a semiconductor device.
[従来の技術]
第3図はZIP(Zig−Zag In1ine Pa
ck age)にワイヤボンディングされた従来の半導
体装置内部の平面図、第4図は第3図に示すA−Aにお
ける拡大断面図である。[Prior art] FIG. 3 shows a ZIP (Zig-Zag Inline Pa
FIG. 4 is an enlarged cross-sectional view taken along line A-A shown in FIG. 3.
図において、(1)はインナーリード、(2)はホンデ
ィングワイヤ、(3)はボンディングパット、(4)は
半導体チップである。In the figure, (1) is an inner lead, (2) is a bonding wire, (3) is a bonding pad, and (4) is a semiconductor chip.
次に動作について説明する。Next, the operation will be explained.
半導体チップ(4)はパッケージにダイボンディングさ
れた後、パッケージのインナーリート(1)と、半導体
チップ(4)上に形成されたポンディングパッド(3)
との間を、金線超音波併用熱圧着ポールボンディング方
式、アルミ線超音波ウェッジボンディング方式又は銅線
超音波併用熱圧着ポールボンディング方式などにより、
金属性のポールボンディングワイヤ(2)を用いて結線
される。After the semiconductor chip (4) is die-bonded to the package, the inner reel (1) of the package and the bonding pad (3) formed on the semiconductor chip (4) are bonded.
The connection between the
The wires are connected using a metal pole bonding wire (2).
[発明が解決しようとする課題]
従来の半導体装置は以上のように構成されているので、
ボンディングワイヤか封止樹脂の応力などによって流れ
てショートしたり、ボンデングワイヤが交差しないよう
に結線しなければならす、ピン数の多いZIPなとは、
ボンデングパッドの方向性が決められ、半導体チップの
面積がさらに大きくなるなどの問題点があった。[Problem to be solved by the invention] Since the conventional semiconductor device is configured as described above,
ZIPs with a large number of pins must be connected so that the bonding wires do not flow due to the stress of the bonding wire or the sealing resin, resulting in a short circuit, or that the bonding wires do not cross.
There were problems such as the directionality of the bonding pads being determined and the area of the semiconductor chip becoming larger.
この発明は上記のような問題点を解決するためになされ
たもので、ボンデングワイヤが交差してもショートの原
因とならす、又、半導体チップの小型化が可能である半
導体装置を得ることを目的とする。This invention was made in order to solve the above-mentioned problems, and aims to provide a semiconductor device in which even if the bonding wires cross, it causes a short circuit, and in which the size of the semiconductor chip can be reduced. purpose.
[課題を解決するための手段]
この発明に係る半導体装置は、絶縁被覆されたボンデン
グワイヤで結線したものである。[Means for Solving the Problems] A semiconductor device according to the present invention is connected by bonding wires coated with insulation.
[作 用]
この発明における半導体装置は、絶縁被覆されたボンデ
ングワイヤで交差するようにワイヤホンデングしても、
電気的にショートの原因とならない。[Function] Even if the semiconductor device of the present invention is bonded with insulation-covered bonding wires so as to cross each other,
Does not cause electrical shorts.
[実施例]
以下、この発明の一実施例を図について説明する。第1
図はZIPにワイヤホンデングされた半導体装置の内部
の平面図、第2図は第1図に示すB・Bにおける拡大断
面図である。図において(1)、(3)、(4)は第3
図の従来例に示したものと同等でおるので説明を省略す
る。(5)は絶縁被覆されたボンデングワイヤ(6)は
ボンデングワイヤ(5)の絶縁被覆である。[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
The figure is a plan view of the inside of a semiconductor device wire-bonded to a ZIP, and FIG. 2 is an enlarged sectional view taken along line B-B shown in FIG. In the figure, (1), (3), and (4) are the third
Since it is the same as that shown in the conventional example in the figure, the explanation will be omitted. The bonding wire (6) coated with insulation (5) is the insulation coating of the bonding wire (5).
に動作について説明する。半導体チップ(4)は、パッ
ケージにグイホンティングされた後、パッテ−ジのイン
ナーリート(1)と、半導体チップ(4)上に形成され
たホンデングバット(3)との間を、金線超音波併用熱
圧着ホールホンディング方式、アルミ線超音波ウェッジ
ホンディング方式又は、銅線超音波併用熱圧着ホールホ
ンディング方式なとにより、ホンディングワイヤ(5)
を用いて結線される。第1図に示すようにホンディング
ワイヤ(5)か交差しても、絶縁被覆(6)で覆われて
いるので、電気的にショートにはならない。The operation will be explained below. After the semiconductor chip (4) is glued into a package, a gold wire is connected between the inner reel (1) of the package and the real butt (3) formed on the semiconductor chip (4). Honing wire (5) by using the ultrasonic thermocompression hole honding method, the aluminum wire ultrasonic wedge bonding method, or the copper wire ultrasonic thermocompression hole honding method.
The wires are connected using As shown in FIG. 1, even if the wires (5) cross each other, they are covered with an insulating coating (6) so that no electrical short circuit occurs.
なお、上記実施例ではZTPの場合について説明したが
、どのような形状のパッケージであってもよく、上記実
施例と同様の効果を奏する。In the above embodiment, a ZTP case has been described, but any shape of the package may be used and the same effects as in the above embodiment can be obtained.
[発明の効果]
以上のように、この発明によれば、絶縁被覆されたボン
ディングワイヤでワイヤボンディングしたので、ボンデ
ィングワイヤか樹脂の応力により流れてショーI・する
を防くことかてき、ボンディングワイヤを交差させて使
用できるので、例えばZTPなとの様に、従来半導体チ
ップの片側にホンディングパットか集中するのに対し、
比較的任意にホンディングパットの位置を選択すること
かてきるのて、信頼性のみならす、半導体チ・ノブ面積
の縮小化がおこなえる効果がある。[Effects of the Invention] As described above, according to the present invention, since wire bonding is performed using an insulated bonding wire, it is possible to prevent the bonding wire from flowing and showing due to the stress of the resin. Because it can be used in a crossed manner, for example in ZTP, unlike conventionally, the honking pads are concentrated on one side of the semiconductor chip,
By selecting the position of the padding relatively arbitrarily, it is possible to not only improve reliability but also to reduce the area of the semiconductor chip/knob.
第1図はこの発明の一実施例によるZIPにワイヤボン
ディングされた半導体装置の内部の平面図第2図は第1
図に示すB−Bにおける拡大断面図、第3図はZIPに
ワイヤボンディングされた従来の半導体装置の内部の平
面図、第4図は第3図に示すA−Aにおける拡大断面図
である。
図において、(1)はインナーリート、(3)はボンデ
ィングバット、(4)は半導体チップ、(5)はボンテ
ィングワイヤ、(6)は絶縁被覆である。
なお、図中、同一符号は同一、又は相当部分を示す。FIG. 1 is a plan view of the inside of a semiconductor device wire-bonded to a ZIP according to an embodiment of the present invention.
3 is a plan view of the interior of a conventional semiconductor device wire-bonded to a ZIP, and FIG. 4 is an enlarged sectional view taken along line AA shown in FIG. 3. In the figure, (1) is an inner lead, (3) is a bonding butt, (4) is a semiconductor chip, (5) is a bonding wire, and (6) is an insulating coating. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
ボンディングワイヤでワイヤボンディングしたことを特
徴とする半導体装置。A semiconductor device characterized in that wire bonding is performed using an insulated bonding wire when assembling the semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2277490A JPH04151842A (en) | 1990-10-15 | 1990-10-15 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2277490A JPH04151842A (en) | 1990-10-15 | 1990-10-15 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04151842A true JPH04151842A (en) | 1992-05-25 |
Family
ID=17584326
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2277490A Pending JPH04151842A (en) | 1990-10-15 | 1990-10-15 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04151842A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10129006A1 (en) * | 2001-06-15 | 2003-01-02 | Conti Temic Microelectronic | Electronic module e.g. for motor vehicle controls, has part of bonding links formed by bonding wire provided with insulating layer |
JP2007088453A (en) * | 2005-09-23 | 2007-04-05 | Freescale Semiconductor Inc | Method of manufacturing stack die package |
-
1990
- 1990-10-15 JP JP2277490A patent/JPH04151842A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10129006A1 (en) * | 2001-06-15 | 2003-01-02 | Conti Temic Microelectronic | Electronic module e.g. for motor vehicle controls, has part of bonding links formed by bonding wire provided with insulating layer |
DE10129006B4 (en) * | 2001-06-15 | 2009-07-30 | Conti Temic Microelectronic Gmbh | Electronic module |
JP2007088453A (en) * | 2005-09-23 | 2007-04-05 | Freescale Semiconductor Inc | Method of manufacturing stack die package |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2819285B2 (en) | Stacked bottom lead semiconductor package | |
US6762079B2 (en) | Methods for fabricating dual loc semiconductor die assembly employing floating lead finger structure | |
US8637975B1 (en) | Semiconductor device having lead wires connecting bonding pads formed on opposite sides of a core region forming a shield area | |
US6982220B1 (en) | Semiconductor device power distribution system and method | |
JP2954110B2 (en) | CSP type semiconductor device and manufacturing method thereof | |
JPS622628A (en) | Semiconductor device | |
JPH04151842A (en) | Semiconductor device | |
JPH0582720A (en) | Resin sealed type semiconductor device | |
JPH08250620A (en) | Semiconductor device | |
JPH03165549A (en) | Semiconductor integrated circuit device | |
JPH0666351B2 (en) | Semiconductor integrated circuit | |
JPS59198744A (en) | Resin sealed type semiconductor device | |
JPH02164057A (en) | Pin grid array semiconductor package | |
JPS63160262A (en) | Lead frame and semiconductor device using the same | |
JPH0936295A (en) | Lead frame, manufacture thereof, resin-sealed semiconductor device and manufacture thereof | |
JPH0637234A (en) | Semiconductor device | |
JPH05291476A (en) | Semiconductor device | |
JPH0669411A (en) | Semiconductor device | |
JPH02198163A (en) | Semiconductor device and manufacture thereof | |
JPH04365340A (en) | Composite circuit type semiconductor device | |
JPH04368140A (en) | Semiconductor device | |
JPH01278031A (en) | Semiconductor device | |
JPH05243309A (en) | Wire bonding method and semiconductor device using it | |
JPH0645503A (en) | Lead frame for resin seal type semiconductor device | |
JPH02134836A (en) | Resin-sealed semiconductor device |