JPH03165549A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH03165549A JPH03165549A JP30521989A JP30521989A JPH03165549A JP H03165549 A JPH03165549 A JP H03165549A JP 30521989 A JP30521989 A JP 30521989A JP 30521989 A JP30521989 A JP 30521989A JP H03165549 A JPH03165549 A JP H03165549A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor integrated
- circuit device
- power supply
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 76
- 239000003990 capacitor Substances 0.000 claims abstract description 24
- 239000011347 resin Substances 0.000 claims abstract description 8
- 229920005989 resin Polymers 0.000 claims abstract description 8
- 230000007257 malfunction Effects 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 4
- 239000000853 adhesive Substances 0.000 abstract description 2
- 239000002184 metal Substances 0.000 abstract description 2
- 229910052751 metal Inorganic materials 0.000 abstract description 2
- 239000010931 gold Substances 0.000 abstract 1
- 229910052737 gold Inorganic materials 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 3
- 230000009977 dual effect Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Abstract
Description
【発明の詳細な説明】 【産業上の利用分野］ 本発明は、半導体集積回路装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor integrated circuit device.
［従来の技術］
一つの基板に複数の半導体集積回路装置を実装して、そ
れらに電源を供給した場合は、電源ラインが共通となる
ため、他の半導体集積回路装置からの不要信号が電源ラ
インから混入して、誤動作の原因となる０周波数の高い
信号の混入はど誤動作となる場合が多いので、一般にコ
ンデンサを使って不要信号をグランドへ逃がしてやるこ
とがおこなわれる。このような目的のために各半導体集
積回路装置の電源ラインとグランドの間に挿入されてい
るコンデンサを、電源バイパスコンデンサと呼ぶ。[Prior Art] When multiple semiconductor integrated circuit devices are mounted on one board and power is supplied to them, the power line is shared, so unnecessary signals from other semiconductor integrated circuit devices are transmitted to the power line. Mixing of signals with a high zero frequency that causes malfunctions often results in malfunctions, so generally a capacitor is used to release unnecessary signals to the ground. A capacitor inserted between the power line and ground of each semiconductor integrated circuit device for this purpose is called a power supply bypass capacitor.
従来の技術では、半導体集積回路装置と電源バイパスコ
ンデンサは第２図のように基板に実装されていた。即ち
、第２図において、１１は半導体集積回路装置、１２は
１ｔｆｉバイパスコンデンサ、１３は基板である。また
、１１の従来例の半導体集積回路装置のパッケージ構造
の断面図は第３図のようになっていた。即ち、第１３図
において、２１はリードフレーム、２２は半導体集積回
路チップ、 ２３はリード、２４はボンディングワイヤ
、２５は樹脂モールドである。In the conventional technology, a semiconductor integrated circuit device and a power supply bypass capacitor are mounted on a board as shown in FIG. That is, in FIG. 2, 11 is a semiconductor integrated circuit device, 12 is a 1TFI bypass capacitor, and 13 is a substrate. Further, a cross-sectional view of the package structure of the semiconductor integrated circuit device of 11 conventional examples is as shown in FIG. That is, in FIG. 13, 21 is a lead frame, 22 is a semiconductor integrated circuit chip, 23 is a lead, 24 is a bonding wire, and 25 is a resin mold.
［発明が解決しようとする課題］
しかし前述の従来技術では、電源バイパスコンデンサは
半導体集積回路チップの電源端子となるべく短い配線で
接続されることが望ましいにもかかわらず、ポンディン
グワイヤとリードの長さの合計より短く接続できないと
いう問題を有していた。さらに電源バイパスコンデンサ
を実装するための基板の面積と配線を要するという問題
点を有する。[Problems to be Solved by the Invention] However, in the prior art described above, although it is desirable that the power supply bypass capacitor be connected to the power supply terminal of the semiconductor integrated circuit chip with as short a wiring as possible, the length of the bonding wire and the lead is too long. There was a problem that the connection could not be made if the length was shorter than the sum of the lengths. Furthermore, there is a problem in that a board area and wiring are required for mounting the power supply bypass capacitor.
そこで本発明はこのような問題点を解決するもので、そ
の目的は、電源ラインからの不要信号で誤動作を起こし
にくく、かつ実装面積が少なくて涜む半導体集積回路装
置を提供するものである。SUMMARY OF THE INVENTION The present invention is intended to solve these problems, and its purpose is to provide a semiconductor integrated circuit device that is less likely to malfunction due to unnecessary signals from a power supply line, and that requires less space for mounting.
［課題を解決するための手段〕
本発明の半導体集積回路装置は、半導体集積回路チップ
を樹脂封止した半導体集積回路装置において、樹脂封止
された該半導体集積回路内に該半導体集積回路チップと
電気的に接続された電源バイパスコンデンサとを少なく
とも１個以上内蔵していることを特徴とする。[Means for Solving the Problems] A semiconductor integrated circuit device of the present invention is a semiconductor integrated circuit device in which a semiconductor integrated circuit chip is sealed with a resin, in which the semiconductor integrated circuit chip and the semiconductor integrated circuit are sealed in the resin-sealed semiconductor integrated circuit. It is characterized by incorporating at least one electrically connected power supply bypass capacitor.
また、樹脂封止された該半導体集積回路装置は、ＤＩＰ
（Ｄｕａｌ Ｉｎ１ｉｎｅ Ｐａｃｋａｇｅ ）
形状、 ＳＩＰ（Ｓｉｎｇｌｅ ＩｎｌｉｎｅＰａ
ｃｋａｇｅ） 形状、 ＺＩＰ （ＺｉｇｚａｇＩ
ｎｌｉｎｅ Ｐａｃｋａｇｅ） 形状、 ＱＦＰ
（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ）
形状、ＳＯＰ（Ｓｍａｌｌ ０ｕｔｌｉｎｅ
Ｐａｃｋａｇｅ） 形状、 ＳＯＪ（Ｓｍａｌｌ
０ｕｔｌｉｎｅ Ｊ−ｂｅｎｄ ｐａｃｋａ
ｇｅ） 形状、 ＰＧＡ（Ｐｉｎ Ｇｒｉｄ
Ａｒｒａｙ） 形状、 Ｃ０Ｂ（Ｃｈｉｐ
Ｏｎ Ｂｏａｒｄ） 形状、 ＴＡＢ（Ｔａ
ｐｅ Ａｕｔｏｍａｔｅｄ Ｂｏｎｄｉｎｇ）
形状であることを特徴とする。Further, the resin-sealed semiconductor integrated circuit device is
(Dual In1ine Package)
Shape, SIP (Single InlinePa)
ckage) shape, ZIP (ZigzagI
nline Package) Shape, QFP
(Quad Flat Package)
Shape, SOP (Small 0utline
Package) Shape, SOJ (Small)
0utline J-bend packa
ge) Shape, PGA (Pin Grid
Array) shape, C0B (Chip
On Board) shape, TAB (Ta
pe Automated Bonding)
It is characterized by its shape.
［作用］
本発明の上記の構成によれば、半導体集積回路装置にお
いて電源バイパスコンデンサを半導体集積回路チップと
ともにパッケージに封止したことにより、電源バイパス
コンデンサを半導体集積回路チップの電源端子に最短で
配線できるため、配線によるインピーダンスが従来技術
より軽減され、電源バイパスコンデンサが効果的に働く
ことによって、電源ラインからの不要信号に強い半導体
集積回路装置が得られる。さらに外部に電源バイパスコ
ンデンサを接続する必要がなくなるため、実装面積が少
なくて済む半導体集積回路装置が得られる。[Function] According to the above configuration of the present invention, in the semiconductor integrated circuit device, the power supply bypass capacitor is sealed in the package together with the semiconductor integrated circuit chip, so that the power supply bypass capacitor can be wired to the power supply terminal of the semiconductor integrated circuit chip in the shortest possible time. As a result, the impedance due to wiring is reduced compared to the conventional technology, and the power supply bypass capacitor works effectively, resulting in a semiconductor integrated circuit device that is resistant to unnecessary signals from the power supply line. Furthermore, since there is no need to connect an external power supply bypass capacitor, a semiconductor integrated circuit device that requires less mounting area can be obtained.
［実施例］
第１図は、本発明の実施例を示す要部の断面図であって
、 １はリードフレーム、２は誘電体、３は電極、４は
絶縁層、５は半導体集積回路チップ、６はリード、７は
ａＳバイパスコンデンサ接続用ボンディングワイヤ、８
はボンディングワイヤ、９は樹脂モールドである。[Example] Fig. 1 is a sectional view of main parts showing an example of the present invention, in which 1 is a lead frame, 2 is a dielectric, 3 is an electrode, 4 is an insulating layer, and 5 is a semiconductor integrated circuit chip. , 6 is a lead, 7 is a bonding wire for connecting the aS bypass capacitor, 8
9 is a bonding wire, and 9 is a resin mold.
以下、工程を追いながら、詳細を説明する。The details will be explained below while following the process.
まず、金属製のリードフレーム１に接着剤を付け、誘電
体２を接着する。さらにこの上に電極３を接着する。こ
のリードフレーム１．誘電体２、及び電極３によって、
コンデンサが形成される。First, an adhesive is applied to a metal lead frame 1, and a dielectric material 2 is adhered thereto. Furthermore, the electrode 3 is bonded on top of this. This lead frame 1. By the dielectric 2 and the electrode 3,
A capacitor is formed.
なお、リードフレーム１は、誘電体２、電極３、絶縁！
！４及び半導体集積回路チップ５の厚みの分だけ中央部
をへこませておくことによって、半導体集積回路チップ
５とリード６の段差を小さくし、後のワイヤボンディン
グの工程を容易に行なうことができる。Note that the lead frame 1 includes a dielectric 2, an electrode 3, and insulation!
! 4 and the thickness of the semiconductor integrated circuit chip 5, the height difference between the semiconductor integrated circuit chip 5 and the leads 6 can be reduced, and the subsequent wire bonding process can be easily performed. .
次に絶縁Ｉ！４を電極３の上に接着する。この時絶縁膜
４は後述のワイヤボンディングのために、穴をあけてお
くか、電極３より面積の狭いものを用いる。そしてこの
上に、半導体集積回路チップ５を接着し、この電源端子
と電極３及びリードフレーム１を金線のボンディングワ
イヤ６で接続する。これで電源バイパスコンデンサが、
半導体集積回路チップ５の電源端子に接続される。同様
に、半導体集積回路チップ５の端子とり−ド７をボンデ
ィングワイヤ８で接続する。Next is insulation I! 4 is glued onto the electrode 3. At this time, the insulating film 4 may have a hole or a film having a smaller area than the electrode 3 may be used for wire bonding, which will be described later. Then, a semiconductor integrated circuit chip 5 is bonded thereon, and the power supply terminal, electrode 3, and lead frame 1 are connected with gold wire bonding wires 6. Now the power supply bypass capacitor is
It is connected to the power supply terminal of the semiconductor integrated circuit chip 5. Similarly, the terminal leads 7 of the semiconductor integrated circuit chip 5 are connected with bonding wires 8.
最後に樹脂モールド９で封止を行なった債に、リードフ
レームの不要な部分の切断を行ない、リード７を曲げて
完成となる。Finally, unnecessary portions of the lead frame of the bond sealed with the resin mold 9 are cut, and the leads 7 are bent to complete the bond.
なお、本実施例ではＤＩＰ （Ｄｕａｌ Ｉｎ１ｉｎ
ｅ Ｐａｃｋａｇｅ）形状のパッケージについて示し
たが、これはＳＩＰ （Ｓｉｎｇｌｅ Ｉｎ１ｉｎｅ
Ｐａｃｋａｇｅ） 形状、 ＺＩＰ（Ｚｉｇｚ
ａｇ Ｉｎ１ｉｎｅ Ｐａｃｋａｇｅ）形状、ＱＦ
Ｐ（Ｑｕａａｄ Ｆｌａｔ Ｐａｃｋａｇｅ）
形状、 ＳＯＰ（Ｓｍａｌｌ ０ｕｔｌｉｎｅ
Ｐａｃｋａｇｅ） 形状、 ＳＯＪ （Ｓｍａｌ
ｌＯｕｔｌｉｎｅ Ｊ−ｂｅｎｄ ｐａｃｋａｇｅ
）形状、ＰＧＡ（Ｐｉｎ Ｇｒｉｄ Ａｒｒａｙ）
形状、 ＣＯＢ （Ｃｈｉｐ Ｏｎ Ｂｏａ
ｒｄ）形状、 ＴＡＢ（Ｔａｐｅ Ａｕｔｏｍａｔ
ｅｄＢｏｎｄｉｎｇ）形状のものにおいても、同様な効
果が期待できる。Note that in this embodiment, DIP (Dual In1 In
This is a SIP (Single Inline) package.
Package) shape, ZIP (Zigz
ag In1ine Package) Shape, QF
P (Quaad Flat Package)
Shape, SOP (Small 0utline)
Package) Shape, SOJ (Small
lOutline J-bend package
) shape, PGA (Pin Grid Array)
Shape, COB (Chip On Boa)
rd) shape, TAB (Tape Auto
edBonding) shape can also be expected to have similar effects.
［発明の効果］
以上述べたように本発明によれば、電源バイパスコンデ
ンサを半導体集積回路チップとともにパッケージに封止
するという構造により、電源ラインからの不要信号に対
し誤動作を起こしにくい半導体集積回路装置が得られる
。さらに外部に電源バイパスコンデンサを接続する必要
がなくなるため、実装面積が少なくて済む半導体集積回
路装置が得られる。このように本発明の実用的効果はき
わめて大きい。[Effects of the Invention] As described above, according to the present invention, a semiconductor integrated circuit device that is less likely to malfunction due to unnecessary signals from a power supply line is achieved due to the structure in which a power supply bypass capacitor is sealed in a package together with a semiconductor integrated circuit chip. is obtained. Furthermore, since there is no need to connect an external power supply bypass capacitor, a semiconductor integrated circuit device that requires less mounting area can be obtained. As described above, the practical effects of the present invention are extremely large.
第１図は、本発明の半導体集積回路装置のパッケージ構
造の実施例を示す要部の断面図。
第２図は、従来例の半導体集積装置と電源バイパスコン
デンサの実装例を示す図。
第３図は、従来例の半導体集積回路装置のパッケージ構
造を示す要部の断面図。
１・・・リードフレーム
２・・・誘電体
３・・・電極
４・・・絶縁層
５・・・半導体集積回路チップ
６・・・リード
７・・・１ｉｔｆｉバイパスコンデンサ接続用ポンデイ
ングワイヤ
８・・・ボンディングワイヤ
９・・・樹脂モールド
１１・・・半導体集積回路装置
１２・・・電源バイパスコンデンサ
１３・・・基板
２１・・・リードフレーム
２２・・・半導体集積回路チップ
２３・・・リード
２４・・・ボンディングワイヤ
２
５・・・樹脂モールド
以
上FIG. 1 is a sectional view of essential parts showing an embodiment of the package structure of a semiconductor integrated circuit device according to the present invention. FIG. 2 is a diagram showing an example of mounting a conventional semiconductor integrated device and a power supply bypass capacitor. FIG. 3 is a sectional view of main parts showing the package structure of a conventional semiconductor integrated circuit device. 1... Lead frame 2... Dielectric 3... Electrode 4... Insulating layer 5... Semiconductor integrated circuit chip 6... Lead 7... 1itfi bypass capacitor connection bonding wire 8. ... Bonding wire 9 ... Resin mold 11 ... Semiconductor integrated circuit device 12 ... Power supply bypass capacitor 13 ... Substrate 21 ... Lead frame 22 ... Semiconductor integrated circuit chip 23 ... Lead 24 ... Bonding wire 2 5 ... Resin mold or more
Claims (1)
路装置において、樹脂封止された該半導体集積回路装置
内に該半導体集積回路チップと電気的に接続された電源
バイパスコンデンサとを少なくとも１個以上内蔵してい
ることを特徴とする半導体集積回路装置。 ２）樹脂封止された該半導体集積回路装置は、ＤＩＰ（
ＤｕａｌＩｎｌｉｎｅＰａｃｋａｇｅ）形状である事を
特徴とする請求項１記載の半導体集積回路装置。 ３）樹脂封止された該半導体集積回路装置は、ＳＩＰ（
ＳｉｎｇｌｅＩｎｌｉｎｅＰａｃｋａｇｅ）形状である
事を特徴とする請求項１記載の半導体集積回路装置。 ４）樹脂封止された該半導体集積回路装置は、ＺＩＰ（
ＺｉｇｚａｇＩｎｌｉｎｅＰａｃｋａｇｅ）形状である
事を特徴とする請求項１記載の半導体集積回路装置。 ５）樹脂封止された、該半導体集積回路装置は、ＱＦＰ
（ＱｕａｄＦｌａｔＰａｃｋａｇｅ）形状である事を特
徴とする請求項１記載の半導体集積回路装置。 ６）樹脂封止された該半導体集積回路装置は、ＳＯＰ（
ＳｍａｌｌＯｕｔｌｉｎｅＰａｃｋａｇｅ）形状である
事を特徴とする請求項１記載の半導体集積回路装置。 ７）樹脂封止された該半導体集積回路装置は、ＳＯＪ（
ＳｍａｌｌＯｕｔｌｉｎｅＪ−ｂｅｎｄｐａｃｋａｇｅ
）形状である事を特徴とする請求項１記載の半導体集積
回路装置。 ８）樹脂封止された該半導体集積回路装置は、ＰＧＡ（
ＰｉｎＧｒｉｄＡｒｒａｙ）形状である事を特徴とする
請求項１記載の半導体集積回路装置。 ９）樹脂封止された該半導体集積回路装置は、ＣＯＢ（
ＣｈｉｐＯｎＢｏａｒｄ）形状である事を特徴とする請
求項１記載の半導体集積回路装置。 １０）樹脂封止された該半導体集積回路装置は、ＴＡＢ
（ＴａｐｅＡｕｔｏｍａｔｅｄＢｏｎｄｉｎｇ）形状で
ある事を特徴とする請求項１記載の半導体集積回路装置
。[Claims] 1) In a semiconductor integrated circuit device in which a semiconductor integrated circuit chip is sealed with resin, a power supply bypass capacitor electrically connected to the semiconductor integrated circuit chip within the resin-sealed semiconductor integrated circuit device. What is claimed is: 1. A semiconductor integrated circuit device comprising at least one built-in device. 2) The resin-sealed semiconductor integrated circuit device is DIP (
2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device has a DualInlinePackage shape. 3) The resin-sealed semiconductor integrated circuit device is SIP (
2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device has a SingleInlinePackage shape. 4) The resin-sealed semiconductor integrated circuit device is ZIP (
2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device has a ZigzagInlinePackage) shape. 5) The resin-sealed semiconductor integrated circuit device is a QFP.
2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device has a (QuadFlatPackage) shape. 6) The resin-sealed semiconductor integrated circuit device has SOP (
2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device has a shape of a SmallOutlinePackage. 7) The resin-sealed semiconductor integrated circuit device is SOJ (
SmallOutlineJ-bendpackage
2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device has a shape of: ). 8) The resin-sealed semiconductor integrated circuit device is a PGA (
2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device has a PinGridArray) shape. 9) The resin-sealed semiconductor integrated circuit device is COB (
2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device has a ChipOnBoard shape. 10) The resin-sealed semiconductor integrated circuit device is TAB
2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device has a (Tape Automated Bonding) shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30521989A JPH03165549A (en) | 1989-11-25 | 1989-11-25 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30521989A JPH03165549A (en) | 1989-11-25 | 1989-11-25 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03165549A true JPH03165549A (en) | 1991-07-17 |
Family
ID=17942477
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30521989A Pending JPH03165549A (en) | 1989-11-25 | 1989-11-25 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03165549A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5734198A (en) * | 1994-11-10 | 1998-03-31 | Micron Technology, Inc. | Multi-layer lead frame for a semiconductor device |
| US5965936A (en) * | 1997-12-31 | 1999-10-12 | Micron Technology, Inc. | Multi-layer lead frame for a semiconductor device |
| US6054754A (en) * | 1997-06-06 | 2000-04-25 | Micron Technology, Inc. | Multi-capacitance lead frame decoupling device |
| US6114756A (en) * | 1998-04-01 | 2000-09-05 | Micron Technology, Inc. | Interdigitated capacitor design for integrated circuit leadframes |
| US6472737B1 (en) | 1998-01-20 | 2002-10-29 | Micron Technology, Inc. | Lead frame decoupling capacitor, semiconductor device packages including the same and methods |
-
1989
- 1989-11-25 JP JP30521989A patent/JPH03165549A/en active Pending
Cited By (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5734198A (en) * | 1994-11-10 | 1998-03-31 | Micron Technology, Inc. | Multi-layer lead frame for a semiconductor device |
| US6307255B1 (en) | 1994-11-10 | 2001-10-23 | Micron Technology, Inc. | Multi-layer lead frame for a semiconductor device |
| US6124630A (en) * | 1994-11-10 | 2000-09-26 | Micron Technology, Inc. | Multi-layer lead frame for a semiconductor device |
| US6707136B2 (en) | 1996-09-04 | 2004-03-16 | Micron Technology, Inc. | Multi-layer lead frame for a semiconductor device |
| US6515353B2 (en) | 1996-09-04 | 2003-02-04 | Micron Technology, Inc. | Multi-layer lead frame for a semiconductor device |
| US6184574B1 (en) | 1997-06-06 | 2001-02-06 | Micron Technology, Inc. | Multi-capacitance lead frame decoupling device |
| US6504236B2 (en) | 1997-06-06 | 2003-01-07 | Micron Technology, Inc. | Semiconductor die assembly having leadframe decoupling characters and method |
| US6781219B2 (en) | 1997-06-06 | 2004-08-24 | Micron Technology, Inc. | Semiconductor die assembly having leadframe decoupling characters |
| US6310388B1 (en) | 1997-06-06 | 2001-10-30 | Micron Technology, Inc. | Semiconductor die assembly having leadframe decoupling characters |
| US6054754A (en) * | 1997-06-06 | 2000-04-25 | Micron Technology, Inc. | Multi-capacitance lead frame decoupling device |
| US5965936A (en) * | 1997-12-31 | 1999-10-12 | Micron Technology, Inc. | Multi-layer lead frame for a semiconductor device |
| US6472737B1 (en) | 1998-01-20 | 2002-10-29 | Micron Technology, Inc. | Lead frame decoupling capacitor, semiconductor device packages including the same and methods |
| US6515359B1 (en) | 1998-01-20 | 2003-02-04 | Micron Technology, Inc. | Lead frame decoupling capacitor semiconductor device packages including the same and methods |
| US6717257B2 (en) | 1998-01-20 | 2004-04-06 | Micron Technology, Inc. | Lead frame decoupling capacitor, semiconductor device packages including the same and methods |
| US7071542B2 (en) | 1998-01-20 | 2006-07-04 | Micron Technology, Inc. | Lead frame decoupling capacitor, semiconductor device packages including the same and methods |
| US6396134B2 (en) | 1998-04-01 | 2002-05-28 | Micron Technology, Inc. | Interdigitated capacitor design for integrated circuit lead frames |
| US6531765B2 (en) | 1998-04-01 | 2003-03-11 | Micron Technology, Inc. | Interdigitated capacitor design for integrated circuit lead frames and method |
| US6265764B1 (en) | 1998-04-01 | 2001-07-24 | Micron Technology, Inc. | Interdigitated capacitor design for integrated circuit lead frames |
| US6730994B2 (en) | 1998-04-01 | 2004-05-04 | Micron Technology, Inc. | Interdigitated capacitor design for integrated circuit lead frames and methods |
| US6114756A (en) * | 1998-04-01 | 2000-09-05 | Micron Technology, Inc. | Interdigitated capacitor design for integrated circuit leadframes |
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