JPH05243309A - Wire bonding method and semiconductor device using it - Google Patents

Abstract

PURPOSE:To accommodate to the miniaturaization and high integration of a semiconductor device by providing a wire bonding method which is suitable for the reduced pad pitch on a chip. CONSTITUTION:A wire bonding method is provided for a semiconductor device formed by wire bonding a plurality of electrode pads 11a arranged in the vicinity of the top plane periphery on a semiconductor chip 11 with inner leads 12d arranged at positions that correspond with the electrode pads 11a on the external side in the vicinity of the semiconductor chip periphery. After bonding the corresponding electrode pad 11a with the inner lead 12d alternately using coated bonding wire 13' which is coated with an insulating layer, the remaining corresponding electrode pads 11a and the inner leads 12d are bonded by bonding wire 13 whose core line is exposed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wire bonding method in a semiconductor device manufacturing process and a structure of a semiconductor device using the same, and is particularly suitable for reducing a pad pitch on a semiconductor chip (hereinafter simply referred to as a chip). The present invention relates to a wire bonding method that realizes downsizing as a semiconductor device and higher integration by realizing the wire bonding method, and a semiconductor device using the same.

In the manufacturing process of a semiconductor device, for example, gold (Au), aluminum (Al), having a thickness of about 30 μm, is provided between an electrode pad on a chip and an inner lead portion such as a package substrate.
There is a process of connecting with a bonding wire (hereinafter simply referred to as a wire) consisting of thin wires such as copper (Cu) and silver (Ag), but as the demand for miniaturization and high integration of semiconductor devices progresses, The pad pitch on the chip tends to become narrower.

In this case, an electrical short circuit is apt to occur due to contact between adjacent wires, and its solution is strongly desired.

[0004]

2. Description of the Related Art FIGS. 3A and 3B are conceptual views for explaining a configuration example of a conventional semiconductor device, in which (3-1) is a side sectional view and (3-2) is a plan view.

FIG. 4 is a diagram for explaining a conventional wire bonding method. In the figure, a semiconductor device in which the chip is mounted on the package substrate will be described as an example.

In FIG. 3, a semiconductor device 1 has a rectangular shape in plan view with a chip 11, a stage 12a is formed in the center thereof with a concave step surface, and a peripheral wall 12b is formed so as to project around the surface. A package substrate 12 made of ceramic or resin mold and a lid plate 14 attached to the upper surface of the peripheral wall of the package substrate 12 are main components.

Among them, the chip 11 has a plurality of electrode pads 11a (11a _-1 , 11a _-2 , ...) At predetermined positions along the periphery of its upper surface.
…) Are aligned. In addition, the package substrate 12 has the chip 11 on the upper surface around the stage 12a.
External connection terminal 12c at the position corresponding to each electrode pad 11a
(12c _-1 ,, 11c _-2 , ...) Conductor pattern 12d (12
d _-1 , 12d _-2 , ...) are formed.

Therefore, each electrode pad 11 of the chip 11 is
The diameter between a _-1 , 11a _-2 , ... and the conductor pattern 12d _-1 , 12d _-2 , ... corresponding to each electrode of the package substrate 12 is 30.
The chip 11 is connected by bonding with a wire 13 of about μm.
After mounting on the package substrate 12, the chip 11 is
And the conductor pattern 12d are sealed together, the required semiconductor device 1 can be obtained.

In this case, the bonding technique for bonding the wire 13 to the electrode pad 11a and the conductor pattern 12d is carried out by a thermocompression bonding method, an ultrasonic bonding method, or a combination of both methods. A case using the crimping technique will be described.

In FIG. 4, (4-1) is a view for explaining the state during bonding, and (4-2) is a plan view showing the state after bonding. Note that, in the drawing, the case where the semiconductor device 1 of FIG. 3 is configured is taken as an example, and therefore, the same target members as those in FIG. 3 are denoted by the same symbols.

The electrode pad 11 on the chip 11 is shown in FIG.
In order to perform bonding connection between a and a corresponding conductor pattern 12d on the package substrate 12 with a wire 13, the wire 13 wound around a reel (not shown) is attached to a horn (not shown) of an ultrasonic device by a capillary 15 Through hole 15
After passing through a, the end portion 13a of the wire 13 protruding from the tip portion 15b of the capillary 15 is attached to the tip portion 15 of the capillary 15.
While pressing the electrode pad 11a with b, ultrasonic energy is applied to connect the wire 13 to the electrode pad 11a, and the capillary 15 is connected to the conductor pattern 12 as shown by an arrow a shown by a broken line.
After moving to d, ultrasonic energy is added in the same pressed state to connect with the conductor pattern 12d.

In this case, the electrode pad 11a on the chip 11 is usually smaller than the conductor pattern 12d on the package substrate 12. Therefore, when the wire 13 is connected to the electrode pad 11a on the chip 11, the end of the wire 13 is brought close to an electrode plate (not shown) to cause an electrical spark between the wire 13 and the tip of the wire 13. After forming a minute spherical pressure-bonded ball in the portion 13a, ultrasonic energy is applied to the electrode pad 11a while pressing the electrode pad 11a, so that they are pressure-bonded to each other.

A conductor pattern on the package substrate 12
Since it is easy to secure a sufficient connection area when connecting to 12d, it is possible to easily connect by increasing the pressing force on the conductor pattern 12d and adding large ultrasonic energy.

Therefore, as shown in (4-2), the electrode pad 11a on the chip 11 and the conductor pattern 12d on the package substrate 12 are formed.
It is possible to easily configure the semiconductor device 1 of FIG.

[0015]

On the other hand, with the recent demand for miniaturization and high integration of semiconductor devices, it is inevitable that the electrode pads formed on the chip are miniaturized and the pitch between adjacent electrodes is narrowed. However, this means that the space between adjacent wires becomes narrower, and an electrical short circuit due to contact or the like is likely to occur.

Therefore, a technique for suppressing an electrical short circuit due to contact between adjacent wires by replacing the conventional wire with a covered wire covered with an insulating layer has been put into practical use.

However, in this case, since the covered wire which is still covered with the insulating layer is connected to the electrode pad or the conductor pattern, the electrode pad surface is pressed with a larger pressing force than in the case of the conventional wire. It is necessary to apply ultrasonic energy while pressing the conductor pattern surface to perform bonding connection, and a large capillary having a wider tip region than the conventional one must be used.

This means that there are restrictions on the narrowing of the pitch between the adjacent electrode pads on the chip, and as a result, there is a growing demand for miniaturization of the electrode pads and a demand for the narrowing of the adjacent pitch. There was a problem that we could not respond.

[0019]

SUMMARY OF THE INVENTION The above-mentioned problems are solved by arranging a plurality of electrode pads arranged in the vicinity of the periphery of the upper surface of the semiconductor chip in alignment with the respective electrode pads on the outside of the periphery of the semiconductor chip. A wire bonding method for a semiconductor device, wherein a bonding wire is used to bond between an inner lead that is provided and a corresponding electrode pad and an inner lead that are covered by an insulating layer. This is solved by a wire bonding method in which the remaining corresponding electrode pads and the inner leads are bonded and connected by the bonding wires with exposed core wires after the bonding and connection with the covered bonding wires.

In addition, a plurality of electrode pads arranged in alignment near the periphery of the upper surface of the semiconductor chip and inner leads arranged at positions corresponding to the respective electrode pads outside the periphery of the semiconductor chip are arranged. A semiconductor device in which bonding gaps are connected by bonding wires, and a covered bonding wire covered with an insulating layer and a bonding wire with an exposed core wire are alternately bonded and connected. Will be resolved.

[0021]

When the conventional wire having the exposed core wire and the covered wire are alternately wired so as to be adjacent to each other, it is possible to halve the use of a capillary having a large tip area and to adjoin even if the pitch between adjacent electrode pads is small. An electrical short circuit due to contact between the wires can be suppressed.

Therefore, in the present invention, after performing the bonding work with the covered wire on every other electrode pad, the bonding work with the conventional wire having the core wire exposed on each of the remaining electrode pads is carried out to form the required semiconductor device. I am trying to do it.

In this case, since a large capillary having a wide tip region is used, the electrode pads on both sides of the capillary are not connected, so that a reliable bonding connection can be performed with a margin.

Further, since the conventional small capillaries can be used for bonding and connecting the conventional wires with the core wires exposed to the remaining electrode pads, there is no restriction of the covered wires connected to both sides.

Therefore, it is possible to easily realize a semiconductor device that meets the demands for advancing miniaturization of electrode pads and narrowing of the pitch between adjacent electrodes.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram for explaining an example of a wire bonding method according to the present invention, where (1-1) is a bonding wire bonding method and (1-2) is a wire bonding method. is there.

FIG. 2 is a plan view showing a state after bonding. In each of the drawings, the case where the semiconductor device 1 of FIG. 3 is configured is taken as an example, and thus the same target members as those of FIG. 3 are represented by the same symbols.

The electrode pad 11 on the chip 11 is shown at (1-1) in FIG.
Between the a and the corresponding conductor pattern 12d on the package substrate 12, for example, the electrode pad 11a- ₁ and the conductor pattern 12d are provided.
Every other connection is made like d _-1 , electrode pad 11a _-3 and conductor pattern 12d _-3 , ....

That is, the coated wire 13 'wound around a reel (not shown) is passed through the through hole 15a' of the capillary 15 'mounted on the horn of the ultrasonic device (not shown), and then the tip of the capillary 15' is inserted. The tip portion of the capillary 15 'is formed by forming a minute spherical pressure-bonded ball on the end portion 13a' of the wire 13 'protruding from the portion 15b' by the method described above.
The wire 13 'is connected to the electrode pad 11a- ₁ by applying ultrasonic energy while pressing it on the electrode pad 11a- ₁ with 15b'.

In this case, since the insulating layer of the covered wire 13 'can be eliminated when the pressure-bonded ball is formed, a reliable connection can be secured. Then, the capillary 1
5'is moved onto the conductor pattern 12d- ₁ as indicated by an arrow a ', and then ultrasonic energy is applied in the same pressed state to connect with the conductor pattern 12d- ₁ .

In this case, the insulating layer of the covered wire 13 'can secure a reliable connection by increasing the pressing force by the capillary 15' and increasing the ultrasonic energy.

Thereafter, the electrode pads 11a- ₃ and the conductor patterns 12d- ₃ are connected in the same manner, and thereafter, every other electrode pad and the conductor pattern are connected. Although the above-mentioned capillary 15 'used in this case is larger than the capillary 15 described in FIG. 4 as described above, when connecting by the capillary 15', electrode pads located on both sides thereof, for example, 11a _-2,1 .
Since the wires are not yet connected to 1a _-4 , ..., they can be connected securely with a sufficient margin.

Then, as shown in (1-2), it is wound on a reel or the like.
The method described in FIG. 4 for the wire 13 described in FIG.
With electrode pad 11a_-2And conductor pattern 12d_-2,Electrode pad
 11a _-FourAnd conductor pattern 12d_-Four,Connect every other like
To do.

The capillary 15 in this case may be a normal one smaller than the above-mentioned capillary 15 'since the connecting wire 13 does not have a covering layer, and is therefore restricted by the covering wire on the adjacent electrode pad. It is possible to connect without fail.

FIG. 2 is a plan view showing a state in which the chip 11 is mounted on the package substrate 12 by the wire bonding method, and between the electrode pad 11a on the chip 11 and the conductor pattern 12d on the package substrate 12. Shows a state in which the wiring material is an alternating wiring of the covered wire 13 ′ and the normal wire 13.

In the semiconductor device constructed by such a bonding method, electrical shorts due to contact between adjacent wires are suppressed, so that the pitch between adjacent electrode pads can be made small, and the fineness of the advancing electrode pads can be reduced. It is possible to meet the demand for narrowing the pitch between adjacent devices.

[0037]

As described above, according to the present invention, the wire bonding method suitable for reducing the pad pitch on the semiconductor chip is realized, and the wire which is downsized as a semiconductor device and adapted to the high integration is realized. A bonding method and a semiconductor device using the same can be provided.

In the description of the present invention, the case of a semiconductor device in which a semiconductor chip is mounted on a package substrate is taken as an example. However, even in the case of a semiconductor device in which the semiconductor chip is mounted on a lead frame, the above wire bonding method is used. The same effect can be obtained by applying.

[Brief description of drawings]

FIG. 1 is a diagram illustrating an example of a wire bonding method according to the present invention.

FIG. 2 is a plan view showing a state after bonding.

FIG. 3 is a conceptual diagram illustrating a configuration example of a conventional semiconductor device.

FIG. 4 is a diagram illustrating a conventional wire bonding method.

[Explanation of symbols]

11 semiconductor chip 11a, 11a _-1 ,, 11a _-2 , 11a _-3 , 11a _-4 ... electrode pad 12 package substrate 12d, 12d _-1 ,, 12d _-2 , 12d _-3 , 12d _-4 ... conductor pattern 13, 13 ' Bonding wire 13a 'End 15, 15' Capillary 15a 'Through hole 15b' Tip

Claims (2)

[Claims] 1. A plurality of electrode pads (11a) arranged in the vicinity of the periphery of the upper surface of the semiconductor chip (11) and positions corresponding to the respective electrode pads (11a) outside the periphery of the semiconductor chip. A wire bonding method for a semiconductor device, wherein a bonding wire is used to bond between the disposed inner lead (12d) and a corresponding electrode pad (11a) and the inner lead (12d). After every one of them is bonded and connected with a covered bonding wire (13 ') covered with an insulating layer, the remaining corresponding electrode pads (11a) and inner leads (12d)
A wire bonding method, characterized in that a bonding wire (13) having an exposed core wire is used for bonding connection between and. 2. A plurality of electrode pads (11a) arranged in the vicinity of the periphery of the upper surface of the semiconductor chip (11) and at positions corresponding to the respective electrode pads (11a) outside the periphery of the semiconductor chip. A semiconductor device in which a bonding wire is connected between the inner lead (12d) provided and a covered bonding wire (13 ') covered with an insulating layer.
A semiconductor device comprising a core and an exposed bonding wire (13) which are alternately connected by bonding.