JP2755032B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2755032B2 JP2755032B2 JP4095795A JP9579592A JP2755032B2 JP 2755032 B2 JP2755032 B2 JP 2755032B2 JP 4095795 A JP4095795 A JP 4095795A JP 9579592 A JP9579592 A JP 9579592A JP 2755032 B2 JP2755032 B2 JP 2755032B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode pattern
- semiconductor chip
- bonding
- resin tape
- external lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/1016—Shape being a cuboid
- H01L2924/10161—Shape being a cuboid with a rectangular active surface
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体チップと外部リ
ードとを導電体にて電気的に接続する半導体装置に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device for electrically connecting a semiconductor chip and external leads with a conductor.
【０００２】[0002]
【従来の技術】従来、樹脂封止型半導体装置は図５に示
すように、半導体チップ５０６上の電極取出口としての
ボンディングパッド５０４と外部リード５０１とがＡｕ
細線のボンディングワイヤー５０３を介して電気的に接
続されていた。2. Description of the Related Art Conventionally, as shown in FIG. 5, a bonding pad 504 as an electrode outlet on a semiconductor chip 506 and an external lead 501 are made of Au as shown in FIG.
They were electrically connected via thin wire bonding wires 503.
【０００３】ボンディングワイヤー５０３と、Ａｕまた
はＡｌで形成されたボンディングパッド５０４とは、熱
及び超音波で圧着し電気的に接続しており、また同様
に、外部リード５０１とボンディングワイヤー５０３も
熱及び超音波にて圧着し電気的に接続した後、ボンディ
ングワイヤー５０３の残りの不要部を切断し、さらに別
の部位のボンディングパッド５０４と外部リード５０１
とをボンディングワイヤー５０３で電気的に接続し、こ
れを繰り返していた。The bonding wire 503 and the bonding pad 504 made of Au or Al are electrically connected by pressure bonding with heat and ultrasonic waves. Similarly, the external lead 501 and the bonding wire 503 are also connected with heat and heat. After being press-bonded by ultrasonic waves and electrically connected, the remaining unnecessary portion of the bonding wire 503 is cut off, and the bonding pad 504 and another external lead 501 in another portion are further cut.
Are electrically connected by a bonding wire 503, and this is repeated.
【０００４】必要とするすべてのボンディングパッド５
０４と外部リード５０１とをボンディングワイヤー５０
３で電気的に接続後、エポキシ等の樹脂で半導体チップ
５０６及びボンディングワイヤー５０４を覆い保護して
いた。[0004] All necessary bonding pads 5
04 and the external lead 501 to the bonding wire 50
After electrical connection at step 3, the semiconductor chip 506 and the bonding wires 504 were covered and protected with a resin such as epoxy.
【０００５】[0005]
【発明が解決しようとする課題】この従来の半導体装置
において、外部リードは、外部リードとなる金属の不要
部をエッチング除去して作るため、外部リードのピッチ
を狭くできない。In this conventional semiconductor device, the pitch of the external leads cannot be narrowed because the external leads are formed by etching away unnecessary portions of the metal that will become the external leads.
【０００６】ボンディングパッド数の増加、またはボン
ディングパッドの大きさが小さくなる場合に、ボンディ
ングパッドと外部リードとの間隔を最小にするように外
部リードをレイアウトすることが不可能となっている。
そのためにボンディングパッドと外部リードとの間隔が
広くなり、ボンディングワイヤーも長くする必要があ
り、例えば、２ｍｍ以上の長さのボンディングワイヤー
も使われている。When the number of bonding pads is increased or the size of the bonding pads is reduced, it is impossible to lay out the external leads so as to minimize the distance between the bonding pads and the external leads.
Therefore, the distance between the bonding pad and the external lead is widened, and the bonding wire needs to be long. For example, a bonding wire having a length of 2 mm or more is used.
【０００７】また、半導体チップ上のボンディングパッ
ド数の増加に伴ない、ボンディングパッドのピッチを狭
くする必要がでてきているが、ボンディングワイヤー同
士のピッチも狭くなり、樹脂封止時にはボンディングワ
イヤーに隣接するボンディングワイヤー方向に応力が働
くため、長いボンディングワイヤーの従来の半導体装置
では隣接するボンディングワイヤー同士が接触するとい
う問題点があった。Further, as the number of bonding pads on the semiconductor chip increases, it is necessary to reduce the pitch of the bonding pads. However, the pitch between the bonding wires also becomes narrower, and the pitch between the bonding wires becomes shorter when the resin is sealed. Therefore, in the conventional semiconductor device having a long bonding wire, there is a problem that adjacent bonding wires come into contact with each other.
【０００８】本発明の目的は、樹脂封止時に働く応力に
よりボンディングワイヤー同士が接触することを防止し
た半導体装置を提供することにある。An object of the present invention is to provide a semiconductor device in which bonding wires are prevented from coming into contact with each other due to a stress applied during resin sealing.
【０００９】[0009]
【課題を解決するための手段】前記目的を達成するた
め、本発明に係る半導体装置は、半導体チップと外部リ
ードを導電体にて電気的に接続し、前記半導体チップと
外部リードを覆うように樹脂封止する半導体装置であっ
て、樹脂テープは、半導体チップの周囲を取り囲み、か
つ半導体チップのボンディングパッドの近傍まで配設さ
れ、電極パターンを有し、 前記電極パターンは、前記樹
脂テープ上に形成され、かつ半導体チップのボンディン
グパッドの近傍まで配設されたものであり、樹脂テープ
上に形成した電極パターンを用い、該電極パターンの一
端を外部リードに電気的に圧着し、かつ該電極パターン
の他端と半導体チップの所定の領域とを導電性のボンデ
ィングワイヤーにて電気的に接続したものである。In order to achieve the above object, a semiconductor device according to the present invention comprises a semiconductor chip and external leads electrically connected by a conductor so as to cover the semiconductor chip and the external leads. A semiconductor device to be resin-encapsulated , wherein a resin tape surrounds the periphery of the semiconductor chip.
To the vicinity of the semiconductor chip bonding pad.
And an electrode pattern, wherein the electrode pattern is
Bonding of semiconductor chip formed on grease tape
The electrode pattern is formed on a resin tape, one end of the electrode pattern is electrically pressed to an external lead, and the other end of the electrode pattern and a predetermined portion of the semiconductor chip are provided. it is obtained by electrically connecting the region of a conductive bonding wires.
【００１０】[0010]
【作用】半導体チップの電極取出口としてのボンディン
グパッドと外部リードとの間に電気的に配線するボンデ
ィングワイヤーを電極パターンとして樹脂テープ上に形
成することにより、隣接するボンディングワイヤー同士
の接触を阻止する。According to the present invention, a bonding wire for electrically wiring between a bonding pad as an electrode outlet of a semiconductor chip and an external lead is formed on a resin tape as an electrode pattern, thereby preventing contact between adjacent bonding wires. .
【００１１】[0011]
【実施例】次に、本発明を図面を参照して説明する。Next, the present invention will be described with reference to the drawings.
【００１２】（実施例１）図１は、本発明の実施例１を
示す平面図である。図２は、本発明の実施例１を示す断
面図である。(Embodiment 1) FIG. 1 is a plan view showing Embodiment 1 of the present invention. FIG. 2 is a sectional view showing Embodiment 1 of the present invention.
【００１３】図において、外部リード１０１上に半導体
チップ１０６をＡｕ・ＳｉまたはＡｇペースト材を使用
してマウントする工程までは従来と同一である。In the figure, the steps up to the step of mounting the semiconductor chip 106 on the external leads 101 using Au.Si or Ag paste material are the same as those in the prior art.
【００１４】本発明では、電極パターン１０２を形成し
てある樹脂テープ１０５を半導体チップ１０６と外部リ
ード１０１とを覆うように形成する。In the present invention, the resin tape 105 on which the electrode pattern 102 is formed is formed so as to cover the semiconductor chip 106 and the external leads 101.
【００１５】樹脂テープの平面図を図３、断面図を図４
に示す。樹脂テープ１０５は厚さ１０μｍで形成されて
おり、樹脂テープ１０５上に電極パターン１０２が厚さ
１．０μｍで形成されている。FIG. 3 is a plan view of the resin tape, and FIG.
Shown in The resin tape 105 is formed with a thickness of 10 μm, and the electrode pattern 102 is formed on the resin tape 105 with a thickness of 1.0 μm.
【００１６】電極パターン１０２は樹脂テープ１０５の
スルーホール１０８を介して樹脂テープ１０５の裏面ま
で延長されている。また、電極パターン１０２のレイア
ウトは、外部リード１０１とボンディングパッド１０４
のレイアウトに適合するように配置されている。The electrode pattern 102 extends to the back surface of the resin tape 105 through the through hole 108 of the resin tape 105. The layout of the electrode pattern 102 is such that the external leads 101 and the bonding pads 104
It is arranged so as to conform to the layout.
【００１７】外部リード１０１と電極パターン１０２と
は、電気スパークによる溶着または半田等で電気的に接
着される。The external lead 101 and the electrode pattern 102 are electrically bonded by welding using an electric spark or soldering.
【００１８】また、電極パターン１０２とボンディング
パッド１０４とは、ボンディング技術による熱圧着また
は超音波で電気的に接続される。The electrode pattern 102 and the bonding pad 104 are electrically connected by thermocompression bonding using bonding technology or ultrasonic waves.
【００１９】この場合、樹脂テープ１０５と半導体チッ
プ１０６とは、特に接着する必要は無い。In this case, the resin tape 105 and the semiconductor chip 106 do not need to be particularly bonded.
【００２０】次に樹脂封止を行ない、外部リードについ
ては切断及び曲げを行なう。Next, resin sealing is performed, and external leads are cut and bent.
【００２１】（実施例２）図６は、本発明の実施例２を
示す断面図である。(Embodiment 2) FIG. 6 is a sectional view showing Embodiment 2 of the present invention.
【００２２】本実施例は、緩衝用ボール１０７を用いる
点で実施例１と異なる。すなわち、樹脂テープ１０５上
の電極パターン１０２にボンディングワイヤー１０３を
ボンディングする際に、電極パターン１０２及び樹脂テ
ープ１０５を介して半導体チップ１０６へ働く応力を緩
衝用ボール１０７により緩和させ、これにより、半導体
チップ１０６のクラックを防止できるという利点があ
る。This embodiment differs from the first embodiment in that a buffer ball 107 is used. That is, when the bonding wire 103 is bonded to the electrode pattern 102 on the resin tape 105, the stress acting on the semiconductor chip 106 via the electrode pattern 102 and the resin tape 105 is relieved by the buffer ball 107, whereby the semiconductor chip There is an advantage that the crack 106 can be prevented.
【００２３】[0023]
【発明の効果】以上説明したように本発明は、樹脂テー
プ上に形成した電極パターンと外部リードとを電気的に
圧着し、かつ前記電極パターンと半導体チップの所定領
域とを導電性のボンディングワイヤーにて電気的に接続
する構造としたことにより、ボンディングワイヤーの長
さを短くすることが可能となり、ボンディングワイヤー
同士のピッチを狭くしても樹脂封止時に働く隣接ボンデ
ィングワイヤー方向への応力によるボンディングワイヤ
ー同士の接触を防止することができる。As described above, according to the present invention, an electrode pattern formed on a resin tape and an external lead are electrically pressed, and a conductive bonding wire is formed between the electrode pattern and a predetermined region of a semiconductor chip. The structure enables electrical connection by means of a bonding wire, which makes it possible to shorten the length of bonding wires. The contact between the wires can be prevented.
【００２４】また、樹脂テープ上の電極パターンは、厚
さ１．０μｍのＡｕ箔またはＣｕ箔をエッチング除去し
てつくるため、電極パターンのピッチは３．０μｍまで
狭くすることが可能であり、半導体装置の半導体チップ
以外の平面的な面積を小さくすることができる。Since the electrode pattern on the resin tape is formed by etching and removing a 1.0 μm thick Au foil or Cu foil, the pitch of the electrode pattern can be reduced to 3.0 μm. The planar area of the device other than the semiconductor chip can be reduced.
【図１】本発明の実施例１を示す平面図である。FIG. 1 is a plan view showing a first embodiment of the present invention.
【図２】図１のＩＩ−ＩＩ線断面図である。FIG. 2 is a sectional view taken along line II-II of FIG.
【図３】図１の樹脂テープを示す詳細図である。FIG. 3 is a detailed view showing the resin tape of FIG. 1;
【図４】図３のＩＶ−ＩＶ線断面図である。FIG. 4 is a sectional view taken along line IV-IV of FIG. 3;
【図５】従来例を示す平面図である。FIG. 5 is a plan view showing a conventional example.
【図６】本発明の実施例２を示す断面図である。FIG. 6 is a sectional view showing a second embodiment of the present invention.
１０１ 外部リード １０２ 電極パターン １０３ ボンディングワイヤー １０４ ボンディングパッド １０５ 樹脂テープ １０６ 半導体チップ １０７ 緩衝用ボール １０８ スルーホール DESCRIPTION OF SYMBOLS 101 External lead 102 Electrode pattern 103 Bonding wire 104 Bonding pad 105 Resin tape 106 Semiconductor chip 107 Buffer ball 108 Through hole
Claims (1)
電気的に接続し、前記半導体チップと外部リードを覆う
ように樹脂封止する半導体装置であって、樹脂テープは、半導体チップの周囲を取り囲み、かつ半
導体チップのボンディングパッドの近傍まで配設され、
電極パターンを有し、 前記電極パターンは、前記樹脂テープ上に形成され、か
つ半導体チップのボンディングパッドの近傍まで配設さ
れたものであり、 樹脂テープ上に形成した電極パターンを用い、該電極パ
ターンの一端を外部リードに電気的に圧着し、かつ該電
極パターンの他端と半導体チップの所定の領域とを導電
性のボンディングワイヤーにて電気的に接続したもので
あることを特徴とする半導体装置。1. A semiconductor device in which a semiconductor chip and an external lead are electrically connected by a conductor and resin-encapsulated so as to cover the semiconductor chip and the external lead, wherein a resin tape surrounds the semiconductor chip. Surround and half
It is arranged to the vicinity of the bonding pad of the conductor chip,
An electrode pattern, wherein the electrode pattern is formed on the resin tape;
To the vicinity of the semiconductor chip bonding pad.
Using an electrode pattern formed on a resin tape, one end of the electrode pattern is electrically pressed to an external lead, and the other end of the electrode pattern and a predetermined region of the semiconductor chip are electrically conductive. which was electrically connected by bonding wires
Wherein a in.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4095795A JP2755032B2 (en) | 1992-03-23 | 1992-03-23 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4095795A JP2755032B2 (en) | 1992-03-23 | 1992-03-23 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05267404A JPH05267404A (en) | 1993-10-15 |
| JP2755032B2 true JP2755032B2 (en) | 1998-05-20 |
Family
ID=14147383
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4095795A Expired - Fee Related JP2755032B2 (en) | 1992-03-23 | 1992-03-23 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2755032B2 (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03169032A (en) * | 1989-11-28 | 1991-07-22 | Nec Kyushu Ltd | Semiconductor device |
| JPH0828456B2 (en) * | 1990-06-11 | 1996-03-21 | 日立電線株式会社 | Multilayer leadframe |
-
1992
- 1992-03-23 JP JP4095795A patent/JP2755032B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05267404A (en) | 1993-10-15 |
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