JPH10284678A - Semiconductor device and manufacture therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate the standardization of in the number of outer leads, the improvement of the performance and the standardization of an input/output terminal arrangement in an area-array-type surface-mounting semiconductor device, wherein a TCP(tape-carrier package) tape is applied. SOLUTION: A tape substrate 2, wherein copper or copper alloy is a main conductor layer and a gold-plated wiring 5 is provided on the surface, and a semiconductor chip 1 are bonded by a bonding layer 8 composed of an elastic body. Connection is performed to the wiring connecting part on the semiconductor chip 1 by an inner lead part 5b of the wiring 5. In this semiconductor device, a common wiring part 5c, which is grounded or held at a power supply potential, is provided in the wiring 5. A lead wiring part 5d, which is connected directly to the inner lead 5b from the common wiring part 5c, without going through a land part 5a for an external electrode, is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a technology effective when applied to an area array type surface mount type semiconductor device to which a TCP (Tape Carrier Package) is applied.

[0002]

2. Description of the Related Art In recent years, there has been a strong demand for a miniaturized package of a semiconductor device for use in applications where the area occupied by a mounting substrate is extremely limited, such as a portable information terminal or a mobile communication device. In addition, there is a strong demand for a technology that responds to the increase in the number of pins of a highly functional semiconductor device and that simultaneously reduces the area occupied by the mounting substrate.

[0003] As one of techniques for satisfying such demands, for example, "LSI Handbook", published November 30, 1984 by Ohm Co., Ltd., p.
1 is known. Further, as a technology that is likely to satisfy the demand for even more strict miniaturization or multi-pin, for example,
Published by the Press Journal on April 20, 2008, "Monthly Semicon
ductor World ”, May 1995, p104-p131
CSP (Chip Size Package) as described in
The technology is known.

[0004] In particular, a proposal by Tessera Corporation of the United States described in the same document, p112 to p113, or published in Nikkei BP, May 1, 1994, "Nikkei Microdevice" May 1994, p98 to p102. ΜBGA technology is superior to bare chip mounting or flip chip mounting in terms of ease of standardization of connection pitch, good absorption of difference in thermal expansion coefficient, ease of test such as burn-in, etc.
It is superior to TCP in terms of ease of handling during mounting and the like, and is considered to be a technology that is generally superior to other mounting technologies.

[0005] The technology of μBGA is disclosed in Japanese Patent Laid-Open Publication No. Hei 6-50440.
Japanese Patent Publication No. 8 is described in detail, and its outline is as follows.

That is, for example, wiring and bumps as outer leads are formed on a flexible tape of polyimide or the like to form a tape substrate having substantially the same area as the semiconductor substrate, and the tape substrate is formed by an adhesive layer made of an elastic material. A gull wing-shaped inner lead formed by adhering to the surface and extending from the end surface of the tape substrate or a through hole opened in the tape substrate is connected to the element electrode on the main surface of the semiconductor device by heat or ultrasonic pressure bonding. is there. The inner lead is formed as a part of the wiring formed on the tape substrate.

As described above, in the μBGA technology, the outer leads are formed on the surface corresponding to the entire surface of the semiconductor substrate, so that miniaturization is easy and handling is easy as described above. In addition, since the semiconductor substrate and the tape substrate are bonded with an elastic body, relative displacement between the two substrates is possible, and thermal stress due to a difference in thermal expansion coefficient between the members is reduced. Is possible.

[0008]

However, the above-mentioned μBGA technology has been developed with an emphasis on miniaturization and ease of handling of semiconductor devices, and has been developed in consideration of standardization of semiconductor devices. It was not something. Therefore, there is a problem that the position of the outer lead on the tape substrate is restricted by the arrangement of the device electrodes on the semiconductor substrate.

In other words, in the μBGA technology, wiring is formed two-dimensionally on a tape substrate, as in other TCP technologies. If only one of the tape substrates is used,
It is not permissible for wires to cross each other. Therefore, as described above, the relationship between the positions of the outer leads and the arrangement of the element electrodes is restricted, and the outer leads are assigned in the order of the arrangement of the element electrodes.

Although such a restriction does not cause much problem when the application of the semiconductor device is a custom IC or the like, it causes a serious problem when the application of the semiconductor device is a general-purpose product such as a DRAM. That is, in the case of general-purpose products, there is a strong demand for standardizing the arrangement of the outer leads, and it is often presupposed that the arrangement of the power supply terminal or the ground terminal is determined in advance. In such a case, it is necessary to design the layout of the device electrodes on the semiconductor substrate so as to conform to the predetermined arrangement of the outer leads. Therefore, there is a problem that the degree of freedom in design is reduced.

In order to improve the electrical characteristics of the semiconductor device, it is preferable to provide as many ground electrodes and power supply electrodes as possible. However, in the current μBGA technology in which the outer leads correspond one-to-one to the element electrodes, if a large number of grounding or power terminals are provided in order to improve the electrical characteristics of the semiconductor device, the number of the outer leads is increased. On the other hand, if the number of outer leads is limited by giving priority to the miniaturization of the semiconductor device, it becomes impossible to optimize the grounding or the power supply terminal, and the performance of the semiconductor device will be reduced. There was a situation where improvement could not be achieved sufficiently.

An object of the present invention is to provide a technique capable of providing a power terminal and a ground terminal on a semiconductor substrate without being restricted by the arrangement of outer leads.

Another object of the present invention is to provide a technique capable of standardizing the outer lead arrangement of a semiconductor device without limiting the degree of freedom in designing the arrangement of element electrodes on a semiconductor substrate.

It is still another object of the present invention to provide a technique capable of reducing the number of outer leads.

It is still another object of the present invention to provide a technique capable of improving the electrical characteristics of a semiconductor device without increasing the number of outer leads.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0017]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) In the semiconductor device of the present invention, a semiconductor chip having a semiconductor circuit element formed on a main surface thereof and having a plurality of wiring connection portions on a surface thereof, a tape substrate made of an organic material, and a tape substrate are provided. A semiconductor device comprising: a plurality of external electrode lands formed to be connected to outer leads; and a wiring including a plurality of inner leads connected to a wiring connection, wherein the wiring has at least one as a part thereof. It includes a common wiring portion connected to two external electrode lands, and has one or more paths for directly connecting the common wiring portion and the inner lead portion without passing through the external electrode lands.

According to such a semiconductor device, the wiring is
A part thereof includes a common wiring portion connected to at least one external electrode land portion, and has at least one path for directly connecting the common wiring portion and the inner lead portion without passing through the external electrode land portion. Therefore, the device electrodes of the power supply and the ground potential can be arranged on the surface of the semiconductor substrate without being limited by the arrangement of the outer leads.

That is, since the external electrode land is connected to the common wiring portion, the outer lead connected to the external electrode land can be used as a power supply terminal or a ground terminal. The common wiring portion can be held at the power supply potential or the ground potential. Further, by having a path directly connecting the common wiring portion and the inner lead portion without passing through the external electrode land portion, the device electrode on the semiconductor substrate connected to this inner lead portion is the same as the common wiring portion. It can be at a potential, namely ground or power supply potential. Since this route can be installed without passing through the external electrode land portion, that is, by sewing between the external electrode land portions, the position of the element electrode in contact with the inner lead portion directly connected to the common wiring portion is provided. Can be arbitrarily arranged without being affected by the arrangement of the external electrode lands. That is, the layout of the device electrodes can be arbitrarily designed without being limited by the layout of the external electrode lands.

As a result, it is easy to standardize the outer lead terminals required when the semiconductor device is used as a general-purpose product such as a DRAM, and to facilitate the layout design of the device electrodes. Further, since the number of power supply and ground electrodes on the semiconductor substrate can be arbitrarily increased, the electrical characteristics of the semiconductor device can be improved. Further, since it is not necessary to provide a large number of outer leads, the number thereof can be reduced. Can be reduced to the minimum required.

The arrangement of the openings in which the inner lead portions are arranged, the common wiring portion, and the external electrode lands may be as follows.

That is, (a) an opening in which the inner leads are arranged is formed at the center of the tape substrate, a common wiring portion is formed along the edge of the tape substrate, and the common wiring portion is formed between the opening and the common wiring portion. When an external electrode land portion is formed between them, (b) inner lead portions are arranged along the edge of the tape substrate, a common wiring portion is formed in the center portion of the tape substrate, and the edge and the common wiring are formed. (C) the tape substrate is divided into the first and second tape substrates at the center of the semiconductor chip, and the first and second tape substrates are separated from each other. A common wiring portion is formed along an edge on the central portion side of each semiconductor chip.
In the case where an external electrode land portion is formed on the end side of each semiconductor chip of the tape substrate, and an opening where an inner lead portion is arranged is formed between the common wiring portion and the external electrode land portion. is there.

Further, in the case (c), the area of the first and second tape substrates where the common wiring portion is formed is
They can be formed to overlap with each other. In such a case, the area occupied by the first and second tape substrates is reduced by the overlapping area, and the semiconductor device can be downsized.

Further, the wiring of the semiconductor device of the present invention may be one in which copper or a copper alloy is used as a main conductive layer and gold-plated. In such a case, copper or a copper alloy is used as the main conductive layer as compared with the case where all of the wiring is manufactured from gold, so that the cost of the wiring material can be reduced and the manufacturing cost of the semiconductor device can be reduced. it can.

(2) The method of manufacturing a semiconductor device according to the present invention
The method for manufacturing a semiconductor device according to the above (1),
(A) a step of forming a conductive thin film made of copper or a copper alloy on a tape substrate; (b) a step of forming a first resist in a region corresponding to the wiring and the wiring for electrolytic plating on the conductive thin film; c) a step of etching the conductive thin film using the first resist as a mask to form a conductive pattern in which all regions are electrically connected; and (d) forming a second resist on the electroplating wiring of the conductive pattern. (E)
Immersing the tape substrate in an electrolytic solution, energizing the conductor pattern, and plating the surface of the conductor pattern except for the area covered with the second resist with gold; (f) removing the second resist and removing copper Alternatively, the method includes a step of immersing the tape substrate in an etching solution having a selectivity between the copper alloy and the gold to remove the wiring for electrolytic plating.

According to such a method of manufacturing a semiconductor device, the conductive thin film is etched using the first resist formed in the region corresponding to the wiring and the wiring for electrolytic plating as a mask. The pattern is electrically connected in all regions, and has the effect of making it easier to perform electrolytic plating in the subsequent steps.

Further, since the electroplating is performed after forming the second resist on the electroplating wiring, gold plating is not formed on the electroplating wiring by using the second resist as a mask. By performing the etching process, that is, the etching process by immersing in an etchant having a selectivity between copper or a copper alloy and gold, the wiring for electrolytic plating can be easily removed.

As described above, according to the present manufacturing method, it is possible to easily manufacture the semiconductor device described in (1) above without largely changing the conventional plating process.

The conductor pattern may be formed in the shape of the wiring from the beginning, and the conductor pattern may be subjected to electroless plating to form gold plating on the surface.

Although the first resist and the second resist can be formed by a photolithography technique using a photoresist, a screen printing technique or the like that can be formed more easily and at a lower cost can be used. May be used.

[0032]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals, and a repeated description thereof will be omitted.

(Embodiment 1) FIG. 1 is a perspective view showing an example of an appearance of a semiconductor device according to an embodiment of the present invention. In FIG. 1, some members are shown by cut portions and broken lines to make the drawing easier to see. FIG. 2 is a top view showing a wiring portion of the semiconductor device shown in FIG.
FIG. 3 is a sectional view taken along line III-III in FIGS. 1 and 2.

The semiconductor device according to the first embodiment has a semiconductor chip 1 and a tape substrate 2 made of an organic material, and a semiconductor circuit element is formed on the main surface side of the semiconductor chip 1. A wiring connection portion 3 is formed as an input / output terminal of the semiconductor circuit element. The wiring connection part 3 is arranged in the center of the semiconductor chip 1 and has an aluminum pad as a part of a wiring layer which is a circuit wiring of a semiconductor circuit element;
Alternatively, it can be a bump made of gold or the like formed on the pad.

The tape substrate 2 can be made of, for example, polyimide (Upilex) and has a thickness of 50 μm.
m. In this regard, in the normal TCP, 75
This is different from using a tape having a thickness of μm or 125 μm. Further, a tape opening 4 is formed at the center of the tape substrate 2 so as to correspond to the arrangement of the wiring connection portions 3.

On one surface of the tape substrate 2, a patterned wiring 5 is provided, and on the other surface, a bump 6 functioning as an outer lead is formed.

The wiring 5 includes an external electrode land 5a, an inner lead 5b, a common wiring 5c, and a lead wiring 5d. Twenty-eight external electrode lands 5a are provided corresponding to the 28 outer leads, and 32 inner lead portions 5b are provided corresponding to the 32 wiring connection portions. Two shared wiring portions 5c are provided, one of which is held at the ground potential and the other is held at the power supply potential. The lead wiring part 5d electrically connects the external electrode land part 5a, the inner lead part 5b, and the common wiring part 5c to each other.

The external electrode land portion 5a is a land for easily connecting the wiring 5 to the bump 6 through a connection hole 7 opened in the tape substrate 2, and has a thickness of, for example, 18
μm. The external electrode land 5
The shape of a is generally circular as shown, but may be rectangular. Further, the diameter is preferably smaller than the diameter of the bump 6 described later and larger than the diameter of the connection hole 7, and may be, for example, 500 μm.

The inner lead portions 5 b are for connecting the wiring 5 to the wiring connecting portion 3, and are arranged along the tape opening 4. That is, the tape opening 4 is provided so as to expose the 32 wiring connection portions 3 arranged at the center of the semiconductor chip 1, and the inner lead portions 5b arranged on both sides of the opening are extended from the edge of the opening. It is formed by bending at an appropriate angle to make one-to-one contact with the wiring connection part 3. This contact can be made by heat or ultrasonic bonding. Note that the thickness of the inner lead portion 5b can be, for example, 18 μm, and the width can be, for example, 50 μm. The interval between the inner lead portions 5b can be, for example, 50 μm. However, the width and the interval are each 25 μm.
It is possible to reduce to.

The common wiring portion 5c is provided near both ends of the tape substrate 2 and has a rectangular shape. The length of the long side is slightly longer than the length of the long side of the tape opening 4. Accordingly, it is possible to form a lead wiring directly extending to the inner lead part 5b at an arbitrary position in the long side direction of the common wiring part 5c. The length of the common wiring portion 5c in the short side direction, that is, the width of the common wiring portion 5c can be any length, but can be, for example, 50 μm, which is equivalent to the width of the lead wiring portion 5d. However, the common wiring section 5
Since c is used as a power supply or ground wiring as described later, it is preferable that the width is as wide as possible for improving the electrical characteristics of the semiconductor device such as noise resistance. Also,
The thickness of the common wiring portion 5c can be set to, for example, 18 μm as in the other regions of the wiring 5. In the first embodiment, the shared wiring portion 5c has a rectangular shape. However, the shared wiring portion 5c may have any shape as long as it is slightly longer than the length of the long side of the tape opening 4; It may be.

The common wiring section 5c is a part of the wiring 5 which is held at the ground potential or the power supply potential and is shared as the ground or power supply wiring. Therefore, the common wiring portion 5c needs to be connected to at least one of the external electrode land portions 5a corresponding to the ground or the power supply terminal. In the case of the first embodiment, two shared wiring portions 5c are provided, and the ground shared wiring 5c-
1 and a power supply common line 5c-2 held at the power supply potential. The ground common wiring 5c-1 is connected to the ground lead wiring 5d-
1 is connected to a ground external electrode land 5a-1 connected to the grounded bump 6, and in FIG. 2, four ground external electrode lands 5a-1 are provided. The power supply common wiring 5c-2 is connected to the power supply external electrode land 5a-2 connected to the power supply bump 6 held at a voltage via the power supply lead wiring 5d-2. Are provided.

Further, the common wiring portion 5c can be directly connected to the inner lead portion 5b, that is, the wiring connection portion 3 without going through the external electrode land portion 5a. That is, the semiconductor chip 1 is connected to the wiring connection portion 3 serving as a ground or power terminal
Are arranged at arbitrary positions by an arbitrary number, and the common wiring portion 5 is provided in such a wiring connection portion 3 by lead wiring not passing through the inner lead portion 5b and the land portion 5a for external electrode.
c. In the case of the first embodiment, the wiring connection portion 3 to be held at the ground potential is connected to the common ground wiring 5c-1 by the ground lead wire 5d-3 that does not pass through the inner lead portion 5b and the external electrode land portion 5a. In addition, the wiring connection portion 3 to be held at the power supply potential is connected to the power supply common wiring 5c- by the power supply lead wiring 5d-4 that does not pass through the inner lead portion 5b and the external electrode land portion 5a.
2 are connected. Such ground lead wiring 5d-
3 and two power supply lead wires 5d-4 are provided.

The lead wiring portion 5d connects the external electrode land portion 5a, the inner lead portion 5b, and the common wiring portion 5c to each other, and includes ground lead wires 5d-1, 3 and power supply lead wires 5d-2, 4. Is also included. The thickness of the lead wiring portion 5d can be, for example, 18 μm,
Its width can be 50 μm. Further, the interval can be set to 50 μm at the closest part. However, the width and the interval at the nearest part are each 25 μm.
It is possible to reduce to.

The wiring 5, that is, the external electrode land 5a,
The inner lead portion 5b, the common wiring portion 5c, and the lead wiring portion 5d have a main conductive layer 5e and a plating layer 5f. Main conductive layer 5e can be, for example, copper or a copper alloy, and plating layer 5f can be, for example, gold plating. By using copper or a copper alloy for the main conductive layer 5e in this manner, sufficient conductivity and current capacity can be ensured, and costs can be reduced as compared with the case where gold is used as the main conductive layer. Further, by forming the plating layer 5f with gold plating, gold plating can be used as a mask in order to remove copper or a copper alloy portion for electrolytic plating in a manufacturing process of a semiconductor device described later.

The bumps 6 can be, for example, solder bumps.
It can be 00 μm and 500 μm. However, the diameter and height are 300 μm and 200 μm, respectively.
It is possible to reduce to μm.

The wiring 5 and the bump 6 are connected via a connection hole 7 opened in the tape substrate 2. The opening diameter of the connection hole 7 can be, for example, 450 μm.
μm.

The semiconductor chip 1 and the tape substrate 2 are adhered by an adhesive layer 8. As a material of the adhesive layer 8, silicone rubber can be exemplified. The adhesive layer 8 functions as an adhesive between the semiconductor chip 1 and the tape substrate 2 and also functions as an elastic body, and its elastic modulus can be set to 0.1 to 50 MPa. When the adhesive layer 8 is made of an elastic material, thermal stress due to a difference in thermal expansion coefficient can be absorbed, and the reliability of mounting the semiconductor device can be improved.

The tape opening 4 is sealed with a resin 9. By embedding the resin 9, the inner lead portion 5b and the semiconductor chip 1 can be protected.

According to the semiconductor device of the first embodiment, in order to provide the common wiring portion 5c, it is possible to provide an arbitrary number and arrangement of the wiring connection portions 3 held on the ground and the power supply voltage on the semiconductor chip 1. it can. That is, the arbitrarily arranged ground voltage wiring connection part 3 is connected to the ground lead wiring 5d-
3, it is possible to connect to the common ground wiring 5c-1 without going through the external electrode land 5a. In such a case, the arbitrarily arranged ground voltage wiring connection part 3 is arranged by the outer lead. It does not affect the arrangement of a certain bump 6. In addition, the arbitrarily arranged power supply voltage wiring connection section 3 can be connected to the power supply common wiring 5c-2 via the power supply lead wiring 5d-4 without passing through the external electrode land 5a. In such a case, the arrangement of the arbitrarily arranged power supply voltage wiring connection portions 3 does not affect the arrangement of the bumps 6 as outer leads. As a result, the layout design of the wiring connection portion 3 can be designed irrespective of the layout of the outer leads, so that the degree of design freedom can be increased and the standardization of the semiconductor device can be supported. Further, since any number of power supply and ground terminals can be provided in the wiring connection portion 3, the number of outer leads can be reduced, and the electrical characteristics of the semiconductor device such as noise characteristics can be improved.

Next, a method of manufacturing the semiconductor device according to the first embodiment will be described with reference to FIGS. 4 to 9
FIGS. 4A to 4C show an example of a method of manufacturing the semiconductor device according to the first embodiment in the order of steps, and FIG.
(B) is a sectional view taken along line bb in (a). Also,
10 and 11 are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device of the first embodiment in the order of steps.

First, a copper or copper alloy thin film 11 having a thickness of about 18 μm is formed on one surface of a polyimide tape 10 having a thickness of 50 μm (FIG. 4).

Next, a resist is formed on both surfaces of the copper or copper alloy thin film 11, and the copper or copper alloy thin film 11 is etched using the resist as a mask. This resist is used for the wiring 5 and the gold plating wiring 1 to be formed later.
The main conductive layer 5e of the wiring 5 and the wiring 12 for gold plating are formed as a result of the patterning (FIG. 5). In FIG. 5, the main conductive layer 5e of the wiring 5 is shown by a solid line, and the gold plating wiring 12 is shown by a broken line, in order to make the drawing easy to see. The resist can be formed by a known screen printing method or a photolithography technique, and the etching can be performed by a known wet etching method or a dry etching method.

Next, a resist 13 is formed so as to cover the gold plating wiring 12 (FIG. 6). For forming the resist, a known screen printing method, a photolithography technique, or the like can be used. Then, polyimide tape 10
Is immersed in an electrolytic solution, and a current is applied to the wiring 12 for gold plating and the main conductive layer 5e so that the plating layer 5 made of gold plating is applied to a region where the resist 13 is not coated, that is, the surface of the main conductive layer 5e.
f is formed (FIG. 6C).

Next, the resist 13 is removed (FIG. 7). Then, the gold plating wiring 1 where no gold plating is formed
The portion 2 is exposed in a state where the copper or copper alloy remains.

The polyimide tape 10 in which such copper or copper alloy is exposed is immersed in an etching solution, and the wiring 12 for gold plating is removed to form the wiring 5 (FIG. 8). As the etchant, a solution that etches copper or a copper alloy and does not etch gold, for example, a mixed acid solution such as nitric acid or acetic acid can be used.

Next, connection holes 7 and tape openings 4 are formed in the polyimide tape 10 (FIG. 9). At this time, the inner lead portion 5b is formed. For removing the polyimide tape 10, for example, a laser ablation method can be used.

Next, bumps 6 made of solder are formed at the connection holes 7 (FIG. 9C). The bump 6 can be formed by, for example, electrolytic plating. The tape substrate 2 can be formed as described above.

Next, the tape substrate 2 is bonded to the semiconductor chip 1 via the bonding layer 8 (FIG. 10). As described above, a silicone resin is suitable for the adhesive layer 8, and has an effect of improving the connection reliability of the outer leads. The adhesive layer 8
May have a thickness of 150 μm.

Next, the tool 14 is acted on the lead end of the inner lead portion 5b, and the inner lead portion 5b is pressed to the wiring connection portion 3 while bending the inner lead portion 5b. In addition, tool 1
Ultrasonic energy is applied to 4 to connect the end of the inner lead portion 5b to the wiring connection portion 3 (FIG. 11). As a connection method, a known gang bonding (batch method) or a single point bonding as a TCP bonding method can be used. Note that bonding by heating may be used in addition to the ultrasonic energy.

Finally, the resin 9 is filled in the tape opening 4 to complete the semiconductor device shown in FIGS.

According to the method of manufacturing a semiconductor device of the present embodiment, the main conductive layer 5 e of the wiring 5 is formed by the gold plating wiring 12.
Are connected to form a single pattern, it is easy to apply a current for electrolytic plating, and the gold plating wiring 12 is covered with a resist 13 to perform electrolytic plating.
Gold plating can be performed only on the surface of the main conductive layer 5e. As a result, the plating layer 5f can be used as a mask in the etching step when the wiring 12 is formed by etching the wiring 12 for gold plating, and the formation step of the wiring 5 can be easily performed.

In the above-described manufacturing method, a pattern of the main conductive layer 5e corresponding to the pattern of the wiring 5 is formed at a time without forming the wiring 12 for gold plating.
The wiring 5 may be formed by forming a plating layer 5f made of gold plating by electroless plating.

(Embodiment 2) FIG. 12 is a top view showing a wiring portion of a semiconductor device according to another embodiment of the present invention, and FIG. 13 is a sectional view taken along line XIII-XIII in FIG. .

In the semiconductor device according to the second embodiment, the wiring connection portion 3 formed on the semiconductor chip 1 is arranged in the end region of the semiconductor chip 1, and thus the inner lead portion 5 b connected to the wiring connection portion 3 Are arranged on the edge of the tape substrate 2 correspondingly. In such a case, the common wiring portion 5c can be arranged at the center of the tape substrate 2, and the external electrode land portion 5a is connected to the wiring connecting portion 3 to be held at the ground potential or the power supply potential from the common wiring portion 5c. Inner lead part 5b that directly corresponds without going through
Can be connected to Therefore, the same effect as in the first embodiment can be obtained. The common wiring section 5c is not limited to a rectangular shape, but may be a rectangular shape, a waveform, a sawtooth shape, or a curved shape.

The external electrode land 5a, the lead wiring 5d, the bump 6, the connection hole 7, the adhesive layer 8, the resin 9 and the like are the same as those in the first embodiment, so that the description is omitted.
The manufacturing method can be the same as in the first embodiment. In the case of the second embodiment, no tape opening is provided.

(Embodiment 3) FIG. 14 is a top view showing a wiring portion of a semiconductor device according to still another embodiment of the present invention, and FIG. 15 is a sectional view taken along line XV-XV in FIG. is there.

In the semiconductor device of the third embodiment, the tape substrate 2 is cut at the center of the semiconductor chip 1 and has two tape substrates 2. Each of the tape substrates 2 is located near the center of the semiconductor chip 1. The tape opening 4 is provided. The common wiring portion 5c is installed along the edge of the center of the semiconductor chip 1 of each tape substrate 2 and the land portion 5a for external electrodes is arranged outside the semiconductor chip 1 of each tape substrate 2.

In such a case as well, the common wiring portion 5c is connected directly to the corresponding inner lead portion 5b without passing through the external electrode land portion 5a to the wiring connection portion 3 to be held at the ground potential or the power supply potential. Therefore, the same effect as in the first embodiment can be obtained. Common wiring section 5
The shape of c may be rectangular, wavy, saw-toothed or curved as described in the first and second embodiments.

The lead wiring portion 5d, the bump 6, the connection hole 7, the adhesive layer 8, the resin 9, and the like are the same as those in the first embodiment, and the description is omitted. The manufacturing method can be the same as in the first embodiment.

In the case where the tape substrate 2 is divided into two as in the third embodiment, FIGS.
As shown in (5), the area of the common wiring portion 5c of the tape substrate 2 can be formed to overlap. FIG. 16 is a top view showing a wiring portion of another example of the semiconductor device according to still another embodiment of the present invention, and FIG.
FIG. 7 is a sectional view taken along line II-XVII. In such a case, since the common wiring portion 5c of the tape substrate 2 is formed in an overlapping manner,
The area occupied by the whole can be reduced, and the size of the semiconductor device can be reduced.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in this embodiment, the tape substrate 2
Although the case of polyimide was exemplified, other organic materials may be used, and the material of the bump 6 was solder.
It goes without saying that gold bumps may be used.

[0073]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) A power supply terminal and a ground terminal can be provided on a semiconductor substrate without being restricted by the arrangement of the outer leads.

(2) The outer lead arrangement of the semiconductor device can be standardized without limiting the degree of freedom in designing the arrangement of the element electrodes on the semiconductor substrate.

(3) The number of outer leads can be reduced.

(4) The electrical characteristics of the semiconductor device can be improved without increasing the number of outer leads.

[Brief description of the drawings]

FIG. 1 is a perspective view showing an example of an appearance of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a top view showing a wiring portion of the semiconductor device shown in FIG. 1;

FIG. 3 is a sectional view taken along line III-III in FIGS. 1 and 2;

4A and 4B show an example of a method of manufacturing the semiconductor device according to the first embodiment in the order of steps, where FIG. 4A is a bottom view and FIG. 4B is a cross-sectional view taken along line bb in FIG. is there.

FIGS. 5A and 5B show an example of a method of manufacturing the semiconductor device according to the first embodiment in the order of steps, in which FIG. 5A is a bottom view and FIG. 5B is a sectional view taken along line bb in FIG. is there.

FIGS. 6A and 6B show an example of a method of manufacturing the semiconductor device according to the first embodiment in the order of steps, in which FIG. 6A is a bottom view, FIG. 6B is a sectional view taken along line bb in FIG. (C)
3A to 3C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device in the order of steps.

FIGS. 7A and 7B show an example of a method of manufacturing the semiconductor device according to the first embodiment in the order of steps, in which FIG. 7A is a bottom view and FIG. 7B is a sectional view taken along line bb in FIG. is there.

FIGS. 8A and 8B show an example of a method of manufacturing the semiconductor device according to the first embodiment in the order of steps, in which FIG. 8A is a bottom view and FIG. 8B is a sectional view taken along line bb in FIG. is there.

9A and 9B show an example of a method of manufacturing the semiconductor device according to the first embodiment in the order of the steps, wherein FIG. 9A is a bottom view, FIG. 9B is a sectional view taken along line bb in FIG. (C)
3A to 3C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device in the order of steps.

FIG. 10 is a cross-sectional view showing one example of the method for manufacturing the semiconductor device of the first embodiment in the order of steps;

FIG. 11 is a cross-sectional view showing an example of the method for manufacturing the semiconductor device of the first embodiment in the order of steps;

FIG. 12 is a top view showing a wiring portion of a semiconductor device according to another embodiment of the present invention.

13 is a sectional view taken along line XIII-XIII in FIG.

FIG. 14 is a top view showing a wiring portion of a semiconductor device according to still another embodiment of the present invention.

15 is a sectional view taken along line XV-XV in FIG.

FIG. 16 is a top view showing a wiring portion of another example of a semiconductor device according to still another embodiment of the present invention.

17 is a sectional view taken along line XVII-XVII in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Tape board 3 Wiring connection part 4 Tape opening 5 Wiring 5a Land part for external electrodes 5a-1 Grounding external electrode land 5a-2 Power supply external electrode land 5b Inner lead part 5c Shared wiring part 5c-1 Grounding common wiring 5c -2 Power supply common wiring 5d Lead wiring part 5d-1 Ground lead wiring 5d-2 Power supply lead wiring 5d-3 Ground lead wiring 5d-4 Power supply lead wiring 5e Main conductive layer 5f Plating layer 6 Bump 7 Connection hole 8 Adhesive layer 9 Resin DESCRIPTION OF SYMBOLS 10 Polyimide tape 11 Thin film 12 Gold plating wiring 13 Resist 14 Tool

Claims (8)

[Claims] 1. A semiconductor circuit element is formed on a main surface thereof,
A semiconductor chip having a plurality of wiring connection portions on its surface,
A tape substrate made of an organic material; and a wiring formed on the tape substrate and including a plurality of external electrode lands connected to outer leads and a plurality of inner leads connected to the wiring connection. In the semiconductor device, the wiring includes a common wiring portion connected to at least one external electrode land portion, and the common wiring portion and the inner lead portion do not pass through the external electrode land portion. Wherein the semiconductor device has one or more paths directly connected to each other. 2. The semiconductor device according to claim 1, wherein an opening for arranging the inner lead portion is formed in a center portion of the tape substrate, and the common wiring portion is formed along an edge of the tape substrate. Wherein the external electrode land portion is formed between the opening and the common wiring portion. 3. The semiconductor device according to claim 1, wherein the inner lead portions are arranged along an edge of the tape substrate, and the common wiring portion is formed at a center of the tape substrate. The semiconductor device, wherein the external electrode land portion is formed between a side and the common wiring portion. 4. The semiconductor device according to claim 1, wherein said tape substrate is divided into a first and a second tape substrate at a central portion of said semiconductor chip, and each of said first and second tape substrates is divided. The common wiring portion is formed along a central side edge of the semiconductor chip, and the first and second wiring portions are formed.
The external electrode land portion is formed on the end side of each of the semiconductor chips of the tape substrate, and an opening in which the inner lead portion is arranged between the shared wiring portion and the external electrode land portion is provided. A semiconductor device characterized by being formed. 5. The semiconductor device according to claim 4, wherein the regions of the first and second tape substrates where the common wiring portion is formed are formed so as to overlap with each other. Semiconductor device. 6. The semiconductor device according to claim 1, wherein the wiring is made of copper or a copper alloy as a main conductive layer. 7. The method of manufacturing a semiconductor device according to claim 1, wherein (a) forming a conductive thin film made of copper or a copper alloy on the tape substrate. (B) forming a first resist in a region corresponding to the wiring and the wiring for electrolytic plating on the conductive thin film, and (c) etching the conductive thin film using the first resist as a mask. Forming a conductive pattern in which the regions are electrically connected; (d) forming a second resist on the electrolytic plating wiring of the conductive pattern; and (e) immersing the tape substrate in an electrolytic solution. Dipping and energizing the conductor pattern to apply gold plating to the surface of the conductor pattern except for the region covered with the second resist; (f) removing the second resist and forming a copper or copper alloy Choose between gold And dipping the tape substrate in an etchant having a specific ratio to remove the wiring for electrolytic plating. 8. The method for manufacturing a semiconductor device according to claim 1, wherein (a) forming a conductive thin film made of copper or a copper alloy on the tape substrate. (B) patterning the conductive thin film to form a conductive pattern corresponding to the wiring; and (c) performing electroless plating on the conductive pattern and forming gold plating on the surface thereof. A method for manufacturing a semiconductor device, comprising: