JP2919648B2 - Hybrid integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit device on which elements requiring aging processing are mounted.

[0002]

2. Description of the Related Art A hybrid integrated circuit device for a vehicle is required to have extremely high environmental resistance and reliability. In particular, a hybrid integrated circuit device mounted in an engine room or a hybrid integrated circuit device related to braking is required to reliably operate under vibration, high temperature, and surge.

FIG. 3 illustrates a hybrid integrated circuit device for braking.
Such a hybrid integrated circuit device will be described with reference to FIG. FIG. 3 is a block diagram of the hybrid integrated circuit device. The hybrid integrated circuit device has an input interface (4) for converting the rotation speed signals of four wheels into signals suitable for computer processing.
0), first and second microcomputers (42) and (46) for calculating the skid state of the four wheels based on a predetermined program and determining the braking amount, and the first and second microcomputers (42) (48), a gate array (50) for comparing and judging the operation results of the first and second microcomputers (42), (48), and an output interface (52).

This hybrid integrated circuit device comprises first and second
Only when the data of the skid state and the braking amount of a specific wheel determined by the microcomputers (42) and (46) are equal to each other, a control operation of releasing the braking of the wheel according to the data is performed. As a result, dangerous malfunctions such as releasing the braking of the wheels that should not be released are prevented.

FIG. 4 shows a substrate structure of the hybrid integrated circuit device described above. An aluminum substrate (60) having an anodized surface is used for the substrate of the hybrid integrated circuit device, and a copper foil is adhered to one main surface of the aluminum substrate (60) with an adhesive insulating resin. Etching and connecting terminal (62), conductive path
(63), die bond pads (64) and other pads are formed.

The first and second microcomputers (4
2) (46), the gate array (50), the input interface (40) or the other semiconductor elements (54) constituting the output interface (52) are die-bonded with Ag paste or the like.
4), the chip resistor (56), a chip capacitor (not shown), and the like are fixed to predetermined pads by soldering.

[0007] Because of noise shielding and a large-scale circuit, a hybrid integrated circuit device for braking is usually formed by dividing into two substrates of the same size and arranging the two substrates to face each other. Is done. Then, in order to eliminate the initial failure, the first and second microcomputers (42) (46),
One substrate on which the gate array (50) is mounted is about 100 ° C.
The aging process is performed for several hours, and the functional test is performed at a voltage of 140% of the rated voltage.

[0008]

A hybrid integrated circuit device using a microcomputer and a chip immediately after completion of a wafer process as a gate array requires a smaller amount of time for the aging process than a circuit device using individual components which have been separately aged. It is inevitable that the number of initial failures will increase. Therefore, there is a possibility that, due to a failure of any one of the chips, all of the boards on which it is mounted will be defective in the final step.

In addition, in the function test of a hybrid integrated circuit device having a fail-safe structure, a test terminal is required around each element, so that there is a problem that the degree of integration is reduced. Further, a hybrid integrated circuit device having a built-in local regulator and overvoltage protection circuit has a problem that an overvoltage test cannot be performed.

[0010]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and a circuit constituted by elements requiring aging processing and a circuit constituted by elements not requiring aging processing are separately provided. The main feature is that they are mounted as a hybrid integrated circuit on an insulated metal substrate and interconnected after aging and functional testing.

[0011]

A circuit composed of elements requiring aging processing and a circuit composed of elements not requiring aging processing are realized as hybrid integrated circuits on separate substrates, so that troubleshooting of each hybrid integrated circuit is easy. And the number of circuits discarded when a failure occurs can be minimized.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. FIG. 2 is a sectional view taken along line AA of FIG. The circuit configuration of the embodiment is the same as that of FIG.
Referring to FIGS. 1 and 2, the hybrid integrated circuit device of the present invention includes a first insulated metal substrate (14) on which the input interface (40) shown in FIG. 3 is mounted, a first and a second microcomputer (42). ) (48), gate array (50), ROM (44) (4
8), a third insulating metal substrate (16) mounting an output interface (52), first and second insulating metal substrates (14) (15) and a second 3. Insulated metal substrate
(16) and a resin connection case (17) forming a sealed space between these insulating metal substrates, and a circuit connection between the second and third insulating metal substrates (15) and (16). Lid to cover the part
It consists of (18). In order to improve the degree of integration, in actual equipment, the first and second microcomputers (42)
A microcomputer with a built-in ROM is used as (48) and the ROMs (44) and (48).

First to third insulating metal substrates (14) (15) (16)
Anodizing the surface, an aluminum substrate (10) having a thickness of 0.5 mm to 2.0 mm on which an insulating layer (11) is formed is used, and an adhesive insulating resin (12) is used on one main surface thereof. Etching the adhered copper foil, internal connection terminal (20), external connection terminal (22), conductive path (24) of several tens of μm width, die bond pad
(26) and the like are formed in a predetermined pattern. First and second microcomputers (42) (48), gate array (50), R
The OM (44) (48) and other semiconductor elements (54) are fixed on the die bond pad (26) using an Ag paste or the like, and a deformed part such as a chip resistor (56) or a chip capacitor is fixed to a predetermined pad. Solder is fixed.

A plurality of internal connection terminals (20) are formed at one peripheral end of the first and third insulating metal substrates (14) and (15), and external connection terminals (22) are perpendicular to the arrangement direction. It is formed.
Further, internal connection terminals (20) are formed at two peripheral edges of the second insulated metal substrate (15). First to third
The insulated metal substrates (14) (15) (16) are their internal connection terminals (20)
Are interconnected by a flexible cable (32) interconnecting the two.

The case (17) is substantially frame-shaped as shown in FIG. 1, and includes a first insulating metal substrate (14) and a second insulating metal substrate.
A groove (34) for accommodating a connection portion with (15), a second insulating metal substrate
A groove for accommodating a connection portion between (15) and the third insulating metal substrate (16).
(36) and a groove (38). The above-mentioned external connection terminal (22)
Are first and third exposed to the outside in this groove (38).
Formed on the insulating metal substrate (14) (15) (16) of this groove (38)
And the first to third insulating metal substrates (14), (15) and (16) form a connector housing. In the embodiment, a male connector is inserted into this connector housing to connect to an external circuit. It is also possible to adopt a structure in which the lead is directly fixed to the external connection terminal (22) by soldering, and a structure in which another connector that can be connected to the female connector connected to the external circuit can be adopted. is there.

The first and second microcomputers (4
2) (48), the gate array (50), the second insulating metal substrate (12) on which the ROMs (44) and (48) are mounted are subjected to an aging treatment at about 100 ° C. for several hours, and then the internal connection terminals A function test and an overvoltage test are performed using (20) as a test terminal.

According to the present invention, since the internal connection terminal is used as a test terminal, not only the problem of occupying the mounting area of the internal connection terminal due to the division of the board does not occur, but also the function test and the overvoltage test can be easily performed. . Further, the number of circuits discarded when a failure occurs can be minimized.

The first to third insulated metal substrates (14), (15), and (16), for which the functional test has been completed, are sequentially interconnected using a flexible cable (32), and the case is covered with a thermosetting resin impregnated sheet. Glued to (17).

Referring to FIG. 2, a flexible cable
The interconnection between the first and second insulated metal substrates (14) and (15) according to (32) is disposed in the groove (34) of the case (17) and is filled with a thermosetting resin and sealed. In addition, the interconnection between the second and third insulating metal substrates (14) and (15) by the flexible cable (32) is shielded and protected by the lid (18).

As described above, the first and second insulating metal substrates (14)
Although the embodiment in which the sum of the substrate areas of (15) is equal to the substrate area of the third insulating metal substrate (15) has been described, the present invention mounts an element requiring aging on the third insulating metal substrate (15). Such changes are possible. Further, the present invention can be applied to a hybrid integrated circuit device using other elements requiring aging other than the microcomputer.

[0021]

As described above, according to the present invention, a circuit constituted by elements requiring aging processing and a circuit constituted by elements not requiring aging processing are realized as hybrid integrated circuits on separate substrates. Therefore, it is easy to troubleshoot each hybrid integrated circuit, and it is possible to minimize the number of circuits discarded when a failure occurs. Further, since a bridge is formed in the case and the divided substrates are connected to each other at the bridge, not only the problem of sealing due to the division of the substrate can be easily solved but also the strength of the case is improved. In addition, since the test terminals are shared for the internal connection of the divided substrates, there is no reduction in the degree of integration.

[Brief description of the drawings]

FIG. 1 is an exploded perspective view of an embodiment of the present invention.

FIG. 2 is a sectional view taken along line AA of FIG.

FIG. 3 is a block diagram of a hybrid integrated circuit device for braking.

FIG. 4 is a perspective view of a main part of a conventional example.

[Explanation of symbols]

 14 First hybrid integrated circuit board 15 Second hybrid integrated circuit board 16 Third hybrid integrated circuit board 17 Case 18 Lid 20 Internal connection terminal 22 External connection terminal 24 Conductive path 26 Die bond pad

Claims (4)

(57) [Claims] 1. A first hybrid integrated circuit board mounted with a main circuit composed of elements requiring aging processing, and a second hybrid integrated circuit board composed of elements not requiring aging processing and mounted with an input interface of the main circuit. A third integrated circuit board comprising a hybrid integrated circuit board, an element that does not require aging processing, and an output interface of the main circuit mounted thereon, and the hybrid integrated circuit board arranged at a predetermined interval; A hybrid integrated circuit device comprising a substantially frame-shaped case to be sealed, wherein the first hybrid integrated circuit board and the second or third hybrid integrated circuit board are arranged on the same plane. Hybrid integrated circuit device. 2. A bridge having a groove is formed in the case, and a connecting portion between the first or third hybrid integrated circuit board and the second hybrid integrated circuit board is arranged in the groove. 2. The hybrid integrated circuit device according to claim 1, wherein a sealing resin is filled, and the connection portion is resin-sealed. 3. The hybrid integrated circuit device according to claim 1, wherein at least a microcomputer is mounted in a chip shape on said first hybrid integrated circuit board. 4. The hybrid integrated circuit device according to claim 1, wherein a pad for interconnecting the hybrid integrated circuit board and a test pad are shared.