JPS5832442A - Hybrid integrated circuit device - Google Patents

Hybrid integrated circuit device

Info

Publication number
JPS5832442A
JPS5832442A JP56130552A JP13055281A JPS5832442A JP S5832442 A JPS5832442 A JP S5832442A JP 56130552 A JP56130552 A JP 56130552A JP 13055281 A JP13055281 A JP 13055281A JP S5832442 A JPS5832442 A JP S5832442A
Authority
JP
Japan
Prior art keywords
conductor
conductors
wiring
element mounting
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56130552A
Other languages
Japanese (ja)
Inventor
Shigemi Nakamura
中村　茂美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56130552A priority Critical patent/JPS5832442A/en
Publication of JPS5832442A publication Critical patent/JPS5832442A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5381—Crossover interconnections, e.g. bridge stepovers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4685—Manufacturing of cross-over conductors

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To reduce the size of an insulative substrate through the improvement of packaging density in the radial formation of a multiple of wiring conductors surrounding a semiconductor element mounting part on the center of the substrate by providing the conductors with an orthogonal conductor to which a conductor extended from one of the conductors is connected, thereby permitting the wiring conductor existence on the element mounting part. CONSTITUTION:A multiple of wiring conductors 2 are formed surrounding a semiconductor element mounting region 13 on an insulative substrate 1, these conductors being conductor 2 and the elements are connected with bonding wires, the following method is employed: a selected conductor 2 from the conductors 2 is provided with a wiring conductor 7 extending to the element mounting region, the extreme ends of which being branched out into both directions to bridge between other conductors 2. The intersecting point of the branched- out conductor and an orthogonal conductor 8 is surrounded with a protective glass film 9. Then, the elements are connected with the conductors 7,8 and the mounting region 13 is covered with a protective glass film 10.

Description

【発明の詳細な説明】 本発明は、導体が印刷された絶縁基板と、該絶縁基板に
搭載され、金属細線でワイヤポンディフグされた半導体
素子とによ）構成された混成集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a hybrid integrated circuit device configured by an insulating substrate on which a conductor is printed, and a semiconductor element mounted on the insulating substrate and wire-bonded with thin metal wires. .

従来、半導体素子を絶縁基板に搭載する場合、金合金片
、中国、あるいは導電悸樹脂により搭載固着されていた
。このとき、′半導体素子を搭載する位置には、導体に
より半導体素子搭載領域（以下マウントランドという）
が形成されて−た。Conventionally, when semiconductor elements are mounted on an insulating substrate, they are mounted and fixed using gold alloy pieces, china, or conductive resin. At this time, a semiconductor element mounting area (hereinafter referred to as mount land) is formed by a conductor at the position where the semiconductor element is mounted.
was formed.

すなわち、＠１図図体は従来の混成集積回路の平面図、
同図（ｂ）は図体）のＡ−Ａ断面図である。これらの図
において、絶縁基板ｌの上に導体印刷により形成された
マウントランド３を放射状に＠囲んで多数の配線導体２
が形成され、マウントランド３の上に導電性マウント材
４′ｆｔ用いて半導体素子５が搭載固着され、半導体素
子のボ／ディ／グ電極と配線導体２との間はボンデ（／
クワイヤ６により接続されている。In other words, the @1 figure is a plan view of a conventional hybrid integrated circuit,
Figure (b) is a sectional view taken along line A-A of the figure. In these figures, a large number of wiring conductors 2 radially surround a mounting land 3 formed by conductor printing on an insulating substrate l.
is formed, the semiconductor element 5 is mounted and fixed on the mount land 3 using 4'ft of conductive mounting material, and a bonder (/
They are connected by a choir 6.

このような従来の混成集積回路装置では、絶縁基板ｌ゛
の上の配線導体は、マウントランド３の外部に限定され
ざるを得ない、したがって、配線導体とマウントランド
それぞれ別個に絶縁基板面が占有されて実値密度に限界
があうた。In such a conventional hybrid integrated circuit device, the wiring conductors on the insulating substrate l' must be limited to the outside of the mount land 3. Therefore, the wiring conductors and the mount land each occupy separate insulating substrate surfaces. As a result, there is a limit to the actual value density.

本発明の目的は、上記のような”限界を克服して、より
一層の実ｆ！密度の向上および装置の小型化が達成され
る混成集積回路装置を提供するにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a hybrid integrated circuit device that overcomes the above-mentioned limitations and achieves further improvement in actual f! density and miniaturization of the device.

本発明の半導体集積回路装置は、絶縁基板と、こ０絶縁
基板上に形成された配線導体と、こ０配線部体とを含む
前記絶縁基板上の半導体素子搭載領域に絶縁性接着剤に
よシ固着された半導体素子とを含む構成を有する。The semiconductor integrated circuit device of the present invention includes an insulating substrate, a wiring conductor formed on the insulating substrate, and a semiconductor element mounting area on the insulating substrate, which includes an insulating substrate, and an insulating adhesive. It has a configuration including a semiconductor element fixedly attached to the semiconductor element.

元来、導体によりマウントランドを形成し、さらに導電
体によりこの！クントラ／ＦＫ半導体素子を固着するの
は、半導体素子の基板を、最高あるいは最底電位のマウ
ントランドに接続保持させるためでありた。しかし、半
導体素子の中で、集積回路素子は素子内部で電源あるー
は接地端子に接続されているため、素子基板を最高ある
いは最低電位に保持するために、マウントランドを最高
あるいは最低電位にする必要はなく、シたがりて、素子
のマウント材として導電性ｉつ／ト材ｔ−使用する必要
もなく、絶縁性接着剤に半導体素子を絶縁基板上に搭載
固着しても何の障害もないのである。Originally, a conductor formed a mount land, and a conductor further formed this! The reason for fixing the Kuntra/FK semiconductor device was to connect and hold the substrate of the semiconductor device to the mount land at the highest or lowest potential. However, among semiconductor devices, integrated circuit devices are connected to the power supply and ground terminals inside the device, so in order to maintain the device substrate at the highest or lowest potential, the mount land is set to the highest or lowest potential. There is no need or desire to use a conductive material as a mounting material for the device, and there is no problem even if the semiconductor device is mounted and fixed on an insulating substrate using an insulating adhesive. There isn't.

したがりて、従来導体で形成されて−たマウントランド
も不要となるため、マウントランドで占有されていた領
域も配線に用いることが可能となる。Therefore, the mounting land, which was conventionally formed of a conductor, is no longer necessary, so that the area occupied by the mounting land can also be used for wiring.

半導体素子の集積化に伴ない一素子サイズが太きくな？
てきている現在、素子のマウントランドを配線に用いる
ことにより、実装密度は大幅に高められることにある。Isn't the size of each element getting larger as semiconductor elements become more integrated?
Nowadays, packaging density can be greatly increased by using the mounting land of an element for wiring.

つぎに本発明を実施例により説明する。Next, the present invention will be explained by examples.

第２図は本発明の一実施例の平面図である。＠２図にお
いて、絶縁基板１の上の半導体素子搭載領域（マウント
ランド）１３には、このマウントランド１３を放射状に
囲むように多数の配線導体２．２．−・が形成され、こ
れらの配線導体のうちの一つの配線導体から延びて、さ
らに両方向に分岐した配”線導体７およびこの配線導体
７と絶縁ガラス９ｔ−はさんで交差する配線導体８が、
マク／トラ／下１３内に含まれている。さらに、ｉつ／
トラノド内は保護ガラス１０によシ覆われ、その上に絶
縁性接着剤によｐ半導体素子が固着される。FIG. 2 is a plan view of one embodiment of the present invention. @2 In Fig. 2, a semiconductor element mounting area (mount land) 13 on the insulating substrate 1 has a large number of wiring conductors 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 2, 3, 4 wiring conductors 2.2. A wiring conductor 7 is formed which extends from one of these wiring conductors and further branches in both directions, and a wiring conductor 8 intersects with this wiring conductor 7 across the insulating glass 9t. ,
Included in Maku/Tora/Lower 13. Furthermore, i/
The interior of the trunk is covered with a protective glass 10, on which a p-semiconductor element is fixed with an insulating adhesive.

以上のように、本発明によれば２、従来配線導体の形成
されなかりた半導体素子搭載領域内に配線導体が形成さ
れるので、この配線導体Ｋｌ！する面積だけ絶縁基板を
小さくで話、　＊鋏密度が向上し、小形化できる効果が
得られる。As described above, according to the present invention, 2. Since a wiring conductor is formed in the semiconductor element mounting area where no wiring conductor was conventionally formed, this wiring conductor Kl! By reducing the area of the insulating substrate, *The scissor density is improved and the effect of miniaturization can be achieved.

【図面の簡単な説明】[Brief explanation of the drawing]

ＷＮ２図（ａ）（ｂ）はそれぞれ従来の混成集積回路装
置の平面図およびその人−入断面図、第２図は本発明の
一実施例に係る絶縁基板の平面図である。 ｌ・・・・・・絶縁基板４２，７．訃・・・・・配°線
一体、３゜１３・・・・・・半導体素子搭載領域（マウ
ントランド）、５・・・・・・半導体素子、６・・・・
・・ポンディフグワイヤ、９、ｌＯ・・・・・・ガラス
保護膜。 ５４−Ｚ　ヅWN2 (a) and (b) are a plan view and a cross-sectional view of a conventional hybrid integrated circuit device, respectively, and FIG. 2 is a plan view of an insulating substrate according to an embodiment of the present invention. l...Insulating substrate 42, 7. Death...Wiring integrated, 3゜13...Semiconductor element mounting area (mount land), 5...Semiconductor element, 6...
...Pondifugu wire, 9, lO...Glass protective film. 54-Z ㅅ

Claims (1)

【特許請求の範囲】[Claims] 絶縁基板と、？−０絶轍基板上に形成された配線導体素
子とを含むことを特徴とする混成集積回路装置。Insulated substrate? - A hybrid integrated circuit device comprising: a wiring conductor element formed on a zero-rut substrate.
JP56130552A 1981-08-20 1981-08-20 Hybrid integrated circuit device Pending JPS5832442A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56130552A JPS5832442A (en) 1981-08-20 1981-08-20 Hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56130552A JPS5832442A (en) 1981-08-20 1981-08-20 Hybrid integrated circuit device

Publications (1)

Publication Number Publication Date
JPS5832442A true JPS5832442A (en) 1983-02-25

Family

ID=15036995

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56130552A Pending JPS5832442A (en) 1981-08-20 1981-08-20 Hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5832442A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53141576A (en) * 1977-05-16 1978-12-09 Matsushita Electric Ind Co Ltd Fixing device of semiconductor
JPS54133878A (en) * 1978-04-07 1979-10-17 Nec Corp Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53141576A (en) * 1977-05-16 1978-12-09 Matsushita Electric Ind Co Ltd Fixing device of semiconductor
JPS54133878A (en) * 1978-04-07 1979-10-17 Nec Corp Semiconductor device

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