JP3896741B2 - Semiconductor device and TAB tape for semiconductor device - Google Patents

Semiconductor device and TAB tape for semiconductor device Download PDF

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Publication number
JP3896741B2
JP3896741B2 JP33180299A JP33180299A JP3896741B2 JP 3896741 B2 JP3896741 B2 JP 3896741B2 JP 33180299 A JP33180299 A JP 33180299A JP 33180299 A JP33180299 A JP 33180299A JP 3896741 B2 JP3896741 B2 JP 3896741B2
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Prior art keywords
semiconductor device
power supply
plating
window hole
supply lead
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JP2001148444A (en
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幸雄 鈴木
達也 大高
洋 杉本
智夫 大森
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Hitachi Cable Ltd
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Hitachi Cable Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置に関し、特に、ウィンドウホールの形成時に発生する絶縁テープおよび接着剤のバリがワイヤボンディングに影響を与えないようにしたｍＢＧＡ（memory Ball Grid Array）構造の半導体装置および半導体装置用ＴＡＢテープに関する。
【０００２】
【従来の技術】
電子機器の高性能化および小型軽量化等に伴い、これに使用される半導体装置には一層の小型化が要求されている。この要求に対応した半導体装置として、ｍＢＧＡタイプの半導体装置が知られている。
図２は、このタイプの半導体装置の構造を示し、半導体チップと同サイズに構成されたＣＳＰ（Chip Scale Package）の構造を示したものである。
【０００３】
図２の（ａ）において、１は絶縁テープ２の第１の面に接着剤３を介して所定のパターンの配線層４を形成したＴＡＢテープ、５は絶縁テープ２の第２の面に接着剤６を介して搭載された半導体チップ、７はＴＡＢテープ１の中央にワイヤボンディングのために形成され、その領域内に半導体チップ５の電極パッド８を位置させたウィンドウホールを示す。
【０００４】
９は配線層４のボンディングパッドと半導体チップ５の電極パッド８を接続したボンディングワイヤ、１０はワイヤボンディング部を覆うように形成された封止樹脂、１１は配線層４の半田ボール用ランドに搭載された半田ボール、１２は半田ボール１１のリフロー時の流れを防止するとともに配線層４を絶縁して保護するソルダレジスト層を示す。
【０００５】
図２の（ｂ）は、図２の（ａ）において、封止樹脂１０、半田ボール１１およびソルダレジスト層１２を取り除いたものの平面図を示し、このなかで配線層４は、所定の形状の配線リード４ａと、半田ボール用ランド４ｂと、ワイヤボンディングのためのボンディングパッド４ｃを有している。配線リード４ａとボンディングパッド４ｃの幅は、前者が６０μｍ程度、後者が１００μｍ程度に設定されるのが普通である。
【０００６】
絶縁テープ２を金型で打ち抜くことによって形成されたウィンドウホール７の中には、半導体チップ５の電極パッド８が配列されており、これらの電極パッド８とボンディングパッド４ｃが、この部分に施されるワイヤボンディングによるボンディングワイヤ９によって接続されている。
【０００７】
図３の（ａ）は、ウィンドウホール７が形成される前のＴＡＢテープ１の状態を示したもので、配線層４を構成する配線リード４ａ、半田ボール用ランド４ｂおよびボンディングパッド４ｃは、左右の群毎に互いに導通された形にあり、これに金型による打ち抜き加工が施されることによって図３の（ｂ）のようにウィンドウホール７が形成される。
【０００８】
図３の（ｃ）は、図３の（ｂ）のＡの部分を拡大して示したものである。
ボンディングパッド４ｃの先端には、発生リード４ａ、半田ボール用ランド４ｂおよびボンディングパッド４ｃにメッキを施すためのメッキ用給電リード４ｄの残片が残っている。配線リード４ａは、ウィンドウホール７の形成によるメッキ用給電リード４ｄの切断によって独立させられ、これによって所定のパターンを有した配線層４が形成され、ｍＢＧＡ型半導体装置のためのＴＡＢテープ１の構成となる。
【０００９】
【発明が解決しようとする課題】
しかし、従来のＴＡＢテープに基づく半導体装置によると、ウィンドウホール７を打ち抜いたとき、メッキ用給電リード４ｄのウィンドウホール７に面する端末の両側縁部４ｄ′と隣接したａ、ｂの部分に絶縁テープ２および接着剤３のバリが発生し、このバリがボンディングパッド４ｃに位置したりするとワイヤボンディングに支障をきたすことがある。
【００１０】
バリは、メッキ用給電リード４ｄが形成された部分と形成されない部分を同時に打ち抜くために発生するもので、メッキ用給電リード４ｄの有無による打ち抜き性の違いを原因として発生する。即ち、メッキ用給電リード４ｄと隣接するために打ち抜き性のよくないａ、ｂの部分における絶縁テープ２と接着剤３の打ち抜きの残滓が、ウィンドウホール７の縁に生成し、これがバリとなるものである。
【００１１】
従って、本発明の目的は、ウィンドウホールを打ち抜いたときの打ち抜きバリによるワイヤボンディングへの悪影響をなくした半導体装置を提供することにある。
【００１２】
【課題を解決するための手段】
本発明は、上記の目的を達成するため、絶縁テープの第１の面にメッキ用給電リード、ボンディングパッドおよび半田ボール用ランドを有した配線層を接着剤で接着し、前記絶縁テープのワイヤボンディング領域に前記メッキ用給電リードを切断して形成されたウィンドウホールを有するＢＧＡ構造の半導体装置用ＴＡＢテープにおいて、前記メッキ用給電リードは、前記ウィンドウホールに面する部分において３０μｍ以下の幅を有することにより、前記ウィンドウホールの形成時に発生する前記絶縁テープおよび前記接着剤のバリのサイズを所定の値以下に抑えたことを特徴とするＴＡＢテープと、このＴＡＢテープを用いた半導体装置を提供するものである。
【００１３】
【発明の実施の形態】
次に、本発明による半導体装置の実施の形態を説明する。
図１の（ａ）は、図３の（ｂ）のＡに相当する部分を拡大して示したもので、メッキ用給電リード４ｄの全長の幅Ｂが２０μｍに設定されており、さらに、ポリイミドからなる絶縁テープ２と給電リード４ｄの厚さが、それぞれ７５μｍと１８μｍに設定されている。
【００１４】
このようにメッキ用給電リード４ｄの幅を３０μｍ以下に設定すると、ウィンドウホール７を打ち抜くとき、メッキ用給電リード４ｄが存在する部分と存在しない部分の打ち抜き性に差が生じないようになり、良好な打ち抜きが行えるようになる。
【００１５】
この結果、メッキ用給電リード４ｄの両側縁部４ｄ′に隣接した部分ａ、ｂにおけるバリの発生は、所定の水準以下に抑制され、良好なワイヤボンディングの実施が可能になる。メッキ用給電リード４ｄの幅を３０μｍを超えて設定する場合には、打ち抜き性への給電リード４ｄの影響が現れるようになり、ａ、ｂへのバリの生成が大きくなるので避ける必要がある。給電リード４ｄの最低幅としては、３μｍに設定することが好ましい。
【００１６】
図１の（ｂ）は、メッキ用給電リード４ｄの幅寸法と発生バリの大きさとの関係を示したもので、バリは、メッキ用給電リード４ｄの幅が大きくなるにしたがって大きくなる。小幅のメッキ用給電リードのもとにウィンドウホールを打ち抜いたＴＡＢテープを使用すれば、良好なワイヤボンディング性に基づいた良質な半導体装置を構成できることは、このグラフから明らかである。
【００１７】
【発明の効果】
以上説明したように、本発明による半導体装置によれば、ウィンドウホールに面する部分においてメッキ用給電リードの幅を３０μｍ以下に設定することで、絶縁テープと接着剤のバリの発生を抑制してワイヤボンディングへのバリの影響を抑制するものであり、実用性の高い半導体装置を提供することができる。
【図面の簡単な説明】
【図１】 本発明による半導体装置の実施の形態を示す説明図であり、（ａ）は図３のＡの部分の拡大図、（ｂ）はメッキ用給電リードの幅と発生バリの大きさとの関係を示す説明図である。
【図２】 半導体装置の構成を示す説明図であり、（ａ）は半導体装置の断面図、（ｂ）は（ａ）の半導体装置から封止樹脂、半田ボールおよびソルダレジスト層を取り除いた場合の平面図を示す。
【図３】 ＴＡＢテープの構成を示す説明図であり、（ａ）はウィンドウホールを打ち抜く前の平面図、（ｂ）はウィンドウホールを打ち抜いた後の平面図、（ｃ）は（ｂ）のＡの部分の拡大図を示す。
【符号の説明】
１ ＴＡＢテープ
２ 絶縁テープ
３、６ 接着剤
４ 配線層
４ａ 配線リード
４ｂ 半田ボール用ランド
４ｃ ボンディングパッド
４ｄ メッキ用給電リード
５ 半導体チップ
７ ウィンドウホール
８ 電極パッド
９ ボンディングワイヤ
１１ 半田ボール
Ｃ メッキ用給電リードの中心軸[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to an mBGA (memory ball grid array) structure semiconductor device and a semiconductor device in which an insulating tape and a burr of an adhesive generated when forming a window hole do not affect wire bonding . It relates to TAB tape .
[0002]
[Prior art]
As electronic devices become more sophisticated and smaller and lighter, semiconductor devices used therefor are required to be further miniaturized. As a semiconductor device corresponding to this requirement, an mBGA type semiconductor device is known.
FIG. 2 shows the structure of this type of semiconductor device, and shows the structure of a CSP (Chip Scale Package) configured to be the same size as the semiconductor chip.
[0003]
In FIG. 2A , 1 is a TAB tape in which a wiring layer 4 having a predetermined pattern is formed on the first surface of the insulating tape 2 with an adhesive 3, and 5 is bonded to the second surface of the insulating tape 2. A semiconductor chip 7 mounted via the agent 6 is formed for wire bonding in the center of the TAB tape 1 and shows a window hole in which the electrode pad 8 of the semiconductor chip 5 is located.
[0004]
9 is a bonding wire connecting the bonding pad of the wiring layer 4 and the electrode pad 8 of the semiconductor chip 5, 10 is a sealing resin formed so as to cover the wire bonding portion, and 11 is mounted on the solder ball land of the wiring layer 4. The solder balls 12 are solder resist layers that prevent the solder balls 11 from reflowing and insulate and protect the wiring layer 4.
[0005]
Of (b) is 2, in FIG. 2 (a), the sealing resin 10, although removal of the solder balls 11 and the solder resist layer 12 shows a plan view, the wiring layer 4 Among this, the predetermined shape Wiring leads 4a, solder ball lands 4b, and bonding pads 4c for wire bonding are provided. The width of the wiring lead 4a and the bonding pad 4c is usually set to about 60 μm for the former and about 100 μm for the latter.
[0006]
In the window hole 7 formed by punching out the insulating tape 2 with a mold, the electrode pads 8 of the semiconductor chip 5 are arranged, and these electrode pads 8 and the bonding pads 4c are applied to this portion. Are connected by bonding wires 9 by wire bonding.
[0007]
FIG. 3A shows the state of the TAB tape 1 before the window hole 7 is formed. The wiring lead 4a, the solder ball land 4b and the bonding pad 4c constituting the wiring layer 4 are left and right. The window holes 7 are formed as shown in FIG. 3 (b) by being punched by a mold.
[0008]
(C) in FIG. 3, there is shown an enlarged portion A of FIG. 3 (b).
At the tip of the bonding pad 4c, the remaining portions of the generated lead 4a, the solder ball land 4b and the plating power supply lead 4d for plating the bonding pad 4c remain. The wiring lead 4a is made independent by cutting the plating power supply lead 4d by forming the window hole 7, thereby forming the wiring layer 4 having a predetermined pattern, and the configuration of the TAB tape 1 for the mBGA type semiconductor device. It becomes.
[0009]
[Problems to be solved by the invention]
However, according to the conventional semiconductor device based on the TAB tape, when the window hole 7 is punched out, insulation is provided at the portions a and b adjacent to both side edge portions 4d 'of the terminal facing the window hole 7 of the feeding lead 4d for plating. If the tape 2 and the adhesive 3 are burred and the burr is positioned on the bonding pad 4c, the wire bonding may be hindered.
[0010]
The burr is generated due to the punching of the portion where the power supply lead 4d for plating is formed and the portion where the power supply lead 4d is not formed at the same time, and is caused by the difference in punchability depending on the presence or absence of the power supply lead 4d for plating. That is, the punching residue of the insulating tape 2 and the adhesive 3 in the portions a and b, which are not punchable because they are adjacent to the feeding lead 4d for plating, is generated at the edge of the window hole 7 and becomes a burr. It is.
[0011]
Accordingly, an object of the present invention is to provide a semiconductor device in which the adverse effect on wire bonding due to punching burrs when a window hole is punched is eliminated.
[0012]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a wire layer having a power feed lead for plating , a bonding pad, and a land for solder balls on the first surface of an insulating tape with an adhesive, and wire bonding of the insulating tape. in TAB tape for a semiconductor device of BGA structure having a window hole formed by cutting the plating power supply leads in the region, the plating power supply leads have a width of less than 30μm in a portion facing said window hole Accordingly, present invention provides a TAB tape which is characterized in that the burr size of the insulating tape and the adhesive occurring during the formation of the window holes is suppressed below a predetermined value, the semiconductor device using the TAB tape It is.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Next, an embodiment of a semiconductor device according to the present invention will be described.
FIG. 1 (a) is an enlarged view of a portion corresponding to A in FIG. 3 (b) . The overall width B of the plating power supply lead 4d is set to 20 μm. the thickness of the insulating tape 2 and the feed lead 4d made of is set to each of 75μm and 18 [mu] m.
[0014]
Thus, when the width of the plating power supply lead 4d is set to 30 μm or less, when the window hole 7 is punched, there is no difference in punchability between the portion where the power supply lead 4d for plating is present and the portion where it is not present. Punching can be performed.
[0015]
As a result, the occurrence of burrs in the portions a and b adjacent to both side edges 4d 'of the plating power supply lead 4d is suppressed to a predetermined level or less, and good wire bonding can be performed. When the width of the plating power supply lead 4d is set to exceed 30 μm, the influence of the power supply lead 4d on the punching performance appears, and the generation of burrs on a and b becomes large, so it is necessary to avoid it. The minimum width of the power supply lead 4d is preferably set to 3 μm.
[0016]
FIG. 1B shows the relationship between the width dimension of the plating power supply lead 4d and the size of the generated burr. The burr increases as the width of the plating power supply lead 4d increases. From this graph, it is apparent that a high-quality semiconductor device based on good wire bonding can be formed by using a TAB tape with a window hole punched out under a narrow power feed lead.
[0017]
【The invention's effect】
As described above, according to the semiconductor device according to the present invention, by setting the width of the plating feed lead to 30μm or less in the portion facing the window hole, and suppress the occurrence of burrs of the insulating tape with adhesive This suppresses the influence of burrs on wire bonding, and can provide a highly practical semiconductor device.
[Brief description of the drawings]
1A and 1B are explanatory views showing an embodiment of a semiconductor device according to the present invention, in which FIG. 1A is an enlarged view of a portion A in FIG. 3 , and FIG. 1B is a diagram showing the width of a feeding lead for plating and the size of a generated burr; It is explanatory drawing which shows these relationships.
FIGS. 2A and 2B are explanatory diagrams showing a configuration of a semiconductor device, where FIG. 2A is a cross-sectional view of the semiconductor device, and FIG. 2B is a case where a sealing resin, a solder ball, and a solder resist layer are removed from the semiconductor device of FIG. The top view of is shown.
3A and 3B are explanatory views showing the structure of a TAB tape, wherein FIG. 3A is a plan view before punching a window hole, FIG. 3B is a plan view after punching a window hole, and FIG. 3C is a plan view of FIG. The enlarged view of the part of A is shown.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 TAB tape 2 Insulating tape 3, 6 Adhesive 4 Wiring layer 4a Wiring lead 4b Solder ball land 4c Bonding pad 4d Power supply lead for plating 5 Semiconductor chip 7 Window hole 8 Electrode pad 9 Bonding wire 11 Solder ball C Power supply lead for plating Center axis

Claims (2)

絶縁テープの第１の面にメッキ用給電リード、およびボンディングパッドおよび半田ボール用ランドを有した配線層を接着剤で接着し、前記絶縁テープのワイヤボンディング領域に前記メッキ用給電リードを切断して形成されたウィンドウホールを有するＢＧＡ構造のＴＡＢテープと、前記絶縁テープの第２の面に接着され、前記ウィンドウホールを介して前記ボンディングパッドとボンディングワイヤで接続された電極パッドを有した半導体チップを備え、
前記メッキ用給電リードは、前記ウィンドウホールに面する部分において３０μｍ以下の幅を有することを特徴とする半導体装置。 A plating power supply lead and a wiring layer having bonding pads and solder ball lands are bonded to the first surface of the insulating tape with an adhesive, and the plating power supply lead is cut in the wire bonding region of the insulating tape. A TAB tape having a BGA structure having a formed window hole, and a semiconductor chip having an electrode pad bonded to the second surface of the insulating tape and connected to the bonding pad and a bonding wire through the window hole Prepared,
The power supply lead for plating has a width of 30 μm or less at a portion facing the window hole. 絶縁テープの第１の面にメッキ用給電リード、およびボンディングパッドおよび半田ボール用ランドを有した配線層を接着剤で接着し、前記絶縁テープのワイヤボンディング領域に前記メッキ用給電リードを切断して形成されたウィンドウホールを有するＢＧＡ構造の半導体装置用ＴＡＢテープにおいて、
前記メッキ用給電リードは、前記ウィンドウホールに面する部分において３０μｍ以下の幅を有することを特徴とする半導体装置用ＴＡＢテープ。 A plating power supply lead and a wiring layer having bonding pads and solder ball lands are bonded to the first surface of the insulating tape with an adhesive, and the plating power supply lead is cut in the wire bonding region of the insulating tape. in TAB tape for a semiconductor device of BGA structure having the formed window hole,
The TAB tape for a semiconductor device, wherein the feeding lead for plating has a width of 30 μm or less at a portion facing the window hole.
JP33180299A 1999-11-22 1999-11-22 Semiconductor device and TAB tape for semiconductor device Expired - Fee Related JP3896741B2 (en)

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JP5057139B2 (en) * 2007-05-18 2012-10-24 日立電線株式会社 Manufacturing method of tape carrier for semiconductor device
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JP5645371B2 (en) * 2009-05-15 2014-12-24 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． Semiconductor device

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