JP2007242890A - Tape-like wiring substrate and semiconductor device - Google Patents

Tape-like wiring substrate and semiconductor device Download PDF

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JP2007242890A
JP2007242890A JP2006063164A JP2006063164A JP2007242890A JP 2007242890 A JP2007242890 A JP 2007242890A JP 2006063164 A JP2006063164 A JP 2006063164A JP 2006063164 A JP2006063164 A JP 2006063164A JP 2007242890 A JP2007242890 A JP 2007242890A
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Prior art keywords
tape
semiconductor device
wiring
slit
base tape
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Japanese (ja)
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Mitsuhiko Endo
光彦 遠藤
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NEC Electronics Corp
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NEC Electronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

<P>PROBLEM TO BE SOLVED: To provide a tape-like wiring substrate which can suppress warpage in a semiconductor assembly intermediate and in each individual semiconductor device, in such an extent as to cause practically no problem, while avoiding complex steps and increased cost and also avoiding degradation of a reliability after being mounted, and also a semiconductor device. <P>SOLUTION: In a tape-like wiring substrate 1, a wiring layer 5 is formed having pads, wiring lines, and lands for ball electrodes formed by patterning on one major surface of a base tape 6, and openings 7 are extended from the other major surface of the base tape down to the ball electrode lands. Slits 18 are formed between the openings 7 by removing the base tape 6, in a linear form. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、テープ状配線基板及び半導体装置に関し、特に、樹脂封止時に発生する半導体組立中間体及び半導体装置の反りを改善する技術に関するものである。   The present invention relates to a tape-like wiring board and a semiconductor device, and more particularly to a technique for improving the warpage of a semiconductor assembly intermediate and a semiconductor device that occur during resin sealing.

電子機器の小型化薄型化の要求から、テープ状配線基板を用いてパッケージングを行うテープＢＧＡ（Ｔａｐｅ Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）が実用化されており、さらに近年は、１枚のテープ状配線基板からの取り数の向上と樹脂封止金型の共通化の目的で、複数の半導体素子を一括して一体に樹脂封止する一体封止が行われている。   Tape BGA (Tape Ball Grid Array), which uses a tape-like wiring board for packaging, has been put into practical use in response to the demand for miniaturization and thinning of electronic devices, and more recently, from one tape-like wiring board. For the purpose of improving the number of products and sharing the resin-sealing mold, integral sealing is performed in which a plurality of semiconductor elements are collectively sealed with resin.

先ず、テープ状配線基板の例を、図１０〜図１１を用いて説明する。テープ状配線基板１は、図１０に示すように、後に切断され個々の半導体装置となる半導体装置ブロック１４が格子状に複数配置され、その一辺にはテープ送りのためのスプロケットホール１３が形成されている。各半導体装置ブロック１４は、図１０のＡ部拡大平面図である図１１に示すように、めっき用配線１２に囲まれており、めっき用配線１２からのめっき電流によってパッド１５、ボール電極用ランド１６、及び、図示しない内部配線をその内部に形成している。また、前記各ボール電極用ランド１６直下の基材テープには、後にボール電極の搭載に利用される開口部（紙面裏面側、図示せず）が形成されている。   First, an example of a tape-like wiring board will be described with reference to FIGS. As shown in FIG. 10, the tape-like wiring substrate 1 has a plurality of semiconductor device blocks 14 which are cut later and become individual semiconductor devices in a lattice shape, and a sprocket hole 13 for tape feeding is formed on one side thereof. ing. Each semiconductor device block 14 is surrounded by a plating wiring 12 as shown in FIG. 11 which is an enlarged plan view of a portion A in FIG. 10. A pad 15 and a ball electrode land are formed by a plating current from the plating wiring 12. 16 and an internal wiring (not shown) are formed therein. Further, the base tape just below each ball electrode land 16 is formed with an opening (the back side of the paper, not shown) that is used for mounting the ball electrode later.

次に、一体封止による半導体装置の製造方法の例を、図１２〜図１６を用いて説明する。先ず、図１２に示すように、半導体装置ブロック１４内の図中二点鎖線で示す所定の位置に、ダイボンディング材を介して半導体チップを搭載し、前記半導体チップ上の電極と前記半導体装置ブロック１４内のパッド１５を金線を介して接続する。次に、図１３（ａ）及びその断面図である図１３（ｂ）に示すように、半導体装置ブロック１４の領域全体を封止樹脂８によって一括して一体に樹脂封止し、半導体組立中間体１７を得る。その後、図１３（ａ）のＢ部拡大断面図である図１４に示すように、半導体組立中間体１７の基材テープ６の開口部７にボール電極１０を搭載する。ここで、１は配線層５と基材テープ６からなるテープ状配線基板を、３は半導体チップを、４は金線を、９はダイボンディング材を、それぞれ示している。次に、図中、平行する２本の破線で示す位置をダイシングによって切断し、図１５に示すように、個々の半導体装置２が得られる。上記例は、半導体チップ上の電極と半導体装置ブロック内のパッドを金線を用いて接続する、いわゆるワイヤボンディング接続の場合について説明したが、図１６に示すように、半導体チップ上の電極又はテープ状配線基板のパッドにあらかじめはんだバンプ２０を形成しておき、加熱、加圧の少なくとも一方を用いて接続する、いわゆるフリップチップ接続を行う場合もある。   Next, an example of a method for manufacturing a semiconductor device by integral sealing will be described with reference to FIGS. First, as shown in FIG. 12, a semiconductor chip is mounted via a die bonding material at a predetermined position indicated by a two-dot chain line in the drawing in the semiconductor device block 14, and the electrode on the semiconductor chip and the semiconductor device block The pad 15 in 14 is connected through a gold wire. Next, as shown in FIG. 13A and FIG. 13B, which is a cross-sectional view thereof, the entire region of the semiconductor device block 14 is collectively sealed with the sealing resin 8 so as to be integrated into the semiconductor assembly. A body 17 is obtained. Thereafter, as shown in FIG. 14, which is an enlarged cross-sectional view of the B part in FIG. 13A, the ball electrode 10 is mounted on the opening 7 of the base tape 6 of the semiconductor assembly intermediate 17. Here, 1 is a tape-like wiring board composed of the wiring layer 5 and the base tape 6, 3 is a semiconductor chip, 4 is a gold wire, and 9 is a die bonding material. Next, in the figure, the positions indicated by two parallel broken lines are cut by dicing, and individual semiconductor devices 2 are obtained as shown in FIG. In the above example, the electrode on the semiconductor chip and the pad in the semiconductor device block are connected using a gold wire, so-called wire bonding connection. However, as shown in FIG. In some cases, so-called flip-chip connection is performed, in which solder bumps 20 are formed in advance on the pads of the wiring substrate and connected using at least one of heating and pressing.

ボール電極の配置は、図１２を用いて説明したボール電極用ランド１６の配置に対応して、格子状で等間隔の配列が一般的である。しかし、図１７に示すメモリ素子の例のように、テープ状配線基板の配線の引き回しの都合や異なるメモリ容量の半導体装置との互換性の都合から格子状配列の中央部にボール電極１０を配置しない場合や、プリント基板等へ二次実装する場合の応力緩和のため半導体装置２の四隅に電気的な配線の不要なダミーのボール電極１０ａを配置する場合もある。   The arrangement of the ball electrodes is generally a grid-like and equidistant arrangement corresponding to the arrangement of the ball electrode lands 16 described with reference to FIG. However, as in the example of the memory element shown in FIG. 17, the ball electrode 10 is arranged at the center of the lattice arrangement for convenience of routing of the tape-like wiring board and compatibility with semiconductor devices having different memory capacities. In some cases, dummy ball electrodes 10a that do not require electrical wiring may be disposed at the four corners of the semiconductor device 2 in order to relieve stress when secondary mounting is performed on a printed circuit board or the like.

しかし、前述のテープ状配線基板及びそれを用いた半導体装置及びその製造方法は、一括して一体に樹脂封止した際に、半導体組立中間体１７が反るという問題があった。これは、従来個別の半導体装置毎に形成されていた封止樹脂が一体に形成されるため、通常、６０×１０−６／ｄｅｇ程度の封止樹脂の線膨張率と、１５×１０−６／ｄｅｇ程度の基材テープの線膨張率の差によって生ずる応力が累積するために起こっている。また、この半導体組立中間体の反りは、ダイシング後においても個別の半導体装置の反りとして残り、ボール電極のスタンドオフ高さのばらつき（コプラナリティの悪化）となって二次実装を困難にしていた。さらにまた、半導体装置の二次実装時においても、基材テープと実装基板の線膨張率の差によって実装基板の反りが生じたり、接続の信頼性を悪化させていた。 However, the tape-like wiring board, the semiconductor device using the tape-like wiring board, and the manufacturing method thereof have a problem that the semiconductor assembly intermediate body 17 is warped when the resin is sealed together. This is because the sealing resin that is conventionally formed for each individual semiconductor device is integrally formed, so that the linear expansion coefficient of the sealing resin is typically about 60 × 10 −6 / deg, and 15 × 10 −6. This is because the stress generated by the difference in linear expansion coefficient of the base tape of about / deg is accumulated. Further, the warpage of the semiconductor assembly intermediate remains as a warp of individual semiconductor devices even after dicing, and variation in the standoff height of the ball electrode (deterioration of coplanarity) makes secondary mounting difficult. Further, even during the secondary mounting of the semiconductor device, the mounting substrate warps or the connection reliability deteriorates due to the difference in the linear expansion coefficient between the base tape and the mounting substrate.

これに対し、図１８に示すように、ガラスセラミック配線基板２５の半導体チップ搭載領域の周囲に凹部２４又はスリットを形成し、実装基板に二次実装する際の応力を緩和する方法（特許文献１参照）が提案されている。ここで、１１ははんだ等の導体、２１はパッド、２３はアンダーフィル樹脂、２６は実装基板をそれぞれ示している。この方法は、線膨張率の大きい封止樹脂による樹脂封止を行わず、半導体チップの線膨張率に近い線膨張率を有するガラスセラミック配線基板２５を用いることで一次実装時（半導体チップ搭載時）の応力を緩和し、凹部２４又はスリットで二次実装時に発生する応力を緩和するもので、技術分野と解決すべき課題が異なる。従って、仮に樹脂封止を行うとしても、線膨張率の大きい封止樹脂と線膨張率の小さいガラスセラミック配線基板との組合わせとなるため、より大きな半導体装置の反りの発生、樹脂クラックの発生、界面からの水分浸入による信頼性の悪化が懸念され、また、凹部２０が半導体チップ搭載領域の周囲のみに形成されているため、封止樹脂とガラスセラミック基板との間の応力緩和には有効に寄与しない。   On the other hand, as shown in FIG. 18, a method of forming a recess 24 or a slit around the semiconductor chip mounting region of the glass ceramic wiring substrate 25 to relieve stress when secondary mounting is performed on the mounting substrate (Patent Document 1). Have been proposed). Here, 11 is a conductor such as solder, 21 is a pad, 23 is an underfill resin, and 26 is a mounting substrate. This method does not perform resin sealing with a sealing resin having a large linear expansion coefficient, and uses a glass ceramic wiring substrate 25 having a linear expansion coefficient close to that of a semiconductor chip, thereby performing primary mounting (when mounting a semiconductor chip). ) To relieve the stress generated during the secondary mounting by the recess 24 or the slit, and the problems to be solved differ from the technical field. Therefore, even if resin sealing is performed, since a combination of a sealing resin having a high linear expansion coefficient and a glass ceramic wiring board having a low linear expansion coefficient, a larger warp of a semiconductor device and a generation of a resin crack There is concern about deterioration of reliability due to moisture intrusion from the interface, and since the recess 20 is formed only around the semiconductor chip mounting region, it is effective for stress relaxation between the sealing resin and the glass ceramic substrate. Does not contribute.

一次実装時に樹脂封止を行う例としては、図１９に示すように、配線基板２２を複数の部分基板に分割し、熱膨張隔差緩和部１９である分割溝内に熱膨張隔差緩和材料を充填することで応力を低減し、半導体装置の反りを低減する方法（特許文献２参照）が開示されている。ここで、２０ははんだバンプ、２１はパッドをそれぞれ示している。   As an example of performing resin sealing at the time of primary mounting, as shown in FIG. 19, the wiring board 22 is divided into a plurality of partial boards, and the thermal expansion gap relaxation material 19 is filled with the thermal expansion gap relaxation material. Thus, a method for reducing stress and reducing warpage of a semiconductor device (see Patent Document 2) is disclosed. Here, 20 indicates solder bumps, and 21 indicates pads.

また、図２０に示すように、配線基板２２のボール電極１０の間に格子状に凹部２４を形成することで、応力を低減すると共にボール電極間の短絡を防止する方法（特許文献３参照）も開示されている。
特開２００５−１２９８１８号公報（第４〜７頁、第１図） 特開平１１−１３５６７５号公報（第３〜５頁、第１０図） 特開２０００−１２７３２号公報（第２〜３頁、第１図） Also, as shown in FIG. 20, a method of reducing stress and preventing a short circuit between the ball electrodes by forming recesses 24 in a lattice shape between the ball electrodes 10 of the wiring board 22 (see Patent Document 3). Is also disclosed.
Japanese Patent Laying-Open No. 2005-129818 (pages 4-7, FIG. 1) Japanese Patent Laid-Open No. 11-135675 (pages 3 to 5, FIG. 10) Japanese Patent Laid-Open No. 2000-12732 (pages 2 and 3, FIG. 1)

しかしながら、前述の図１９を用いて説明した、配線基板を複数の部分基板に分割し、熱膨張隔差緩和部である分割溝内に熱膨張隔差緩和材料を充填することで応力を低減し、半導体装置の反りを低減する方法には、次のような残された問題点があった。すなわち、この方法は、通常の工程に加え、配線基板に裏面に至らない切り込みを入れ分割溝を形成し、その溝の中に熱膨張隔差緩和材料を充填、硬化した後ドライエッチングで平坦化し、さらに配線基板の反対面から熱膨張隔差緩和材料が露出するまで研磨する工程が追加で必要となるため、工程が複雑でコストアップとなる。また、製法上、充填された熱膨張隔差緩和材料を配線基板の配線層で塞ぐ構造が取れないため、実装後に熱膨張隔差緩和材料を介して侵入した水分が容易に半導体チップ表面に到達し、信頼性を悪化させる恐れがあった。   However, as described above with reference to FIG. 19, the wiring board is divided into a plurality of partial boards, and the stress is reduced by filling the thermal expansion gap relaxation material into the division grooves which are thermal expansion gap relaxation portions, thereby reducing the stress. The method for reducing the warpage of the apparatus has the following remaining problems. That is, in addition to the normal process, this method forms a split groove by cutting into the wiring board that does not reach the back surface, and fills and cures the thermal expansion difference relaxation material in the groove, and then planarizes by dry etching, Furthermore, an additional step of polishing until the thermal expansion gap relieving material is exposed from the opposite surface of the wiring board is necessary, which complicates the process and increases the cost. In addition, because of the manufacturing method, it is not possible to take a structure in which the thermal expansion gap relaxation material filled with the wiring layer of the wiring board is taken, so moisture that has entered through the thermal expansion gap relaxation material after mounting easily reaches the surface of the semiconductor chip, There was a risk of deteriorating reliability.

また、前述の図２０を用いて説明した、基板２２のボール電極１０の間に格子状に凹部２４を形成することで、応力を低減すると共にボール電極間の短絡を防止する方法には、次のような残された問題点があった。すなわち、この方法は、二次実装時の配線基板と実装基板の間の応力緩和効果はあるが、基板２２の封止樹脂８と接する面まで凹部２４が至っていないため、封止樹脂と配線基板の間の応力緩和効果は小さく、複数の半導体装置を一括して一体に樹脂封止した場合の半導体組立中間体の反りや個別に切断後の半導体装置の反りを防止する効果が充分でなかった。   The method of reducing the stress and preventing the short circuit between the ball electrodes by forming the recesses 24 in a lattice shape between the ball electrodes 10 of the substrate 22 described with reference to FIG. There was a problem left behind. That is, this method has a stress relaxation effect between the wiring board and the mounting board at the time of secondary mounting, but since the recess 24 does not reach the surface of the board 22 in contact with the sealing resin 8, the sealing resin and the wiring board. The stress relaxation effect between the two was small, and the effect of preventing the warpage of the semiconductor assembly intermediate when a plurality of semiconductor devices were collectively encapsulated with resin and the warpage of the semiconductor device after individual cutting was not sufficient .

また、前述の図１８〜２０を用いて説明した従来技術は、いずれも個々の半導体装置の応力を低減するものであり、個別の半導体装置となる複数の半導体装置ブロックを有するテープ状配線基板を一体に樹脂封止した状態の半導体組立中間体の応力を吸収し反りを低減する効果は充分では無かった。   The conventional techniques described with reference to FIGS. 18 to 20 described above all reduce the stress of individual semiconductor devices, and a tape-like wiring board having a plurality of semiconductor device blocks to be individual semiconductor devices. The effect of absorbing the stress and reducing the warpage of the semiconductor assembly intermediate in the state of being integrally resin-sealed is not sufficient.

本発明の課題は、工程が複雑でコストアップとなることがなく、実装後の信頼性を悪化させることなしに、実用上問題の無い程度まで半導体組立中間体及び個別の半導体装置の反りを低減できるテープ状配線基板及び半導体装置を提供することである。   The object of the present invention is to reduce the warpage of the semiconductor assembly intermediate and the individual semiconductor devices to the extent that there is no practical problem without complicating the process and increasing the cost and without deteriorating the reliability after mounting. It is to provide a tape-like wiring board and a semiconductor device.

本発明の請求項１記載のテープ状配線基板は、基材テープの一主面に、パッド、配線、ボール電極用ランドがパターニングされた配線層が形成され、基材テープの他の主面から前記ボール電極用ランドに至る開口部を有するテープ状配線基板において、前記開口部間に前記基材テープを線状に除去したスリットを有する。   In the tape-like wiring board according to claim 1 of the present invention, a wiring layer in which pads, wiring, and ball electrode lands are patterned is formed on one main surface of the base tape, and the other main surface of the base tape is used. The tape-like wiring board having an opening reaching the ball electrode land has a slit formed by linearly removing the base tape between the openings.

本発明の請求項２記載の半導体装置は、基材テープと配線層からなるテープ状配線基板の、前記配線層を有する一主面に半導体チップが搭載され、他の主面に開口する前記基材テープの開口部にボール電極が搭載され、前記半導体チップ上の電極が前記ボール電極に電気的に接続された半導体装置において、前記開口部間に前記基材テープを線状に除去したスリットを有する。   According to a second aspect of the present invention, there is provided the semiconductor device according to the second aspect, wherein a semiconductor chip is mounted on one main surface having the wiring layer of a tape-shaped wiring substrate including a base tape and a wiring layer, and the substrate is opened on another main surface. In a semiconductor device in which a ball electrode is mounted in an opening of a material tape, and an electrode on the semiconductor chip is electrically connected to the ball electrode, a slit is formed by linearly removing the base tape between the openings. Have.

本発明の請求項５記載のテープ状配線基板は、基材テープの一主面に、配線層としてパッド、配線、ボール電極用ランドを有する複数の半導体装置ブロックが形成され、前記半導体装置ブロック間にめっき用配線を有するテープ状配線基板において、前記めっき用配線と接する前記基材テープの一部が線状に除去されたスリットを有する。   In the tape-like wiring board according to claim 5 of the present invention, a plurality of semiconductor device blocks having pads, wirings, and ball electrode lands as wiring layers are formed on one main surface of the base tape, and between the semiconductor device blocks. In the tape-like wiring board having the plating wiring, a part of the base tape in contact with the plating wiring has a slit removed in a linear shape.

本発明のテープ状配線基板及び半導体装置によれば、ボール電極用の開口部間に基材テープを線状に除去したスリットが形成されているため、封止樹脂と基材テープの線膨張率の差による応力が緩和され、半導体装置の反りが実用上問題の無い程度に少なくなる。また、本発明のテープ状配線基板によれば、めっき用配線と接する前記基材テープの一部が線状に除去されたスリットを有するため、複数の半導体装置ブロックの配列方向に累積した封止樹脂と基材テープの線膨張率の差による応力が緩和され、半導体組立中間体の反りが実用上問題の無い程度に少なくなる。また、前記スリットは、テープ状配線基板の製造時にボール電極用の開口部と同時に、エッチングやレーザー加工で形成できるため、新たな設備や工程の追加が無くコストアップとなることがない。また、スリット形成位置に配線層を形成しておくことにより、配線層によってスリットを経由した水分の浸入が防止でき、実装後の信頼性が悪化することが無いという優れた産業上の効果が得られる。   According to the tape-like wiring board and the semiconductor device of the present invention, since the slit is formed by linearly removing the base tape between the ball electrode openings, the linear expansion coefficient between the sealing resin and the base tape is formed. The stress due to the difference is relaxed, and the warp of the semiconductor device is reduced to such a level that there is no practical problem. In addition, according to the tape-like wiring substrate of the present invention, since the part of the base tape in contact with the wiring for plating has a slit removed in a linear shape, the sealing accumulated in the arrangement direction of a plurality of semiconductor device blocks The stress due to the difference between the linear expansion coefficients of the resin and the base tape is alleviated, and the warpage of the semiconductor assembly intermediate is reduced to a level that causes no problem in practice. Further, since the slit can be formed by etching or laser processing at the same time as the opening for the ball electrode at the time of manufacturing the tape-like wiring substrate, there is no additional equipment or process and the cost is not increased. In addition, by forming a wiring layer at the slit formation position, it is possible to prevent moisture from entering through the slit by the wiring layer, and an excellent industrial effect that reliability after mounting is not deteriorated is obtained. It is done.

以下、本発明の実施の形態を添付図面を参照し、従来例と同一物には同一の符号を用いて説明する。   DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the accompanying drawings using the same reference numerals for the same components as in the conventional example.

本発明の第１乃至第４の実施形態であるテープ状配線基板及び半導体装置は、個別に分離された状態の半導体装置の反りの低減に関するものである。   The tape-like wiring board and the semiconductor device according to the first to fourth embodiments of the present invention relate to a reduction in warpage of the semiconductor device in a state of being individually separated.

本発明の第１の実施形態であるテープ状配線基板１は、その基材テープ側から見た個別の半導体装置ブロック１４のみを表した図１及びそのＣ部断面図である図２に示すように、基材テープ６の一主面に、パッド、配線、ボール電極用ランドがパターニングされた配線層５が形成され、基材テープ６の他の主面から前記ボール電極用ランドに至る開口部を有するテープ状配線基板１において、前記開口部７間に基材テープ６を線状に除去したスリット１８を有する。図２において、配線層５が基材テープ６の全面に描かれているが、実際には、パッド、配線、ボール電極用ランド、及び、スリットに対応する位置にパターニングされている。   The tape-like wiring substrate 1 according to the first embodiment of the present invention is shown in FIG. 1 showing only an individual semiconductor device block 14 viewed from the base tape side and FIG. Further, a wiring layer 5 in which pads, wirings, and ball electrode lands are patterned is formed on one main surface of the base tape 6, and an opening extending from the other main surface of the base tape 6 to the ball electrode lands. In the tape-like wiring substrate 1 having the slits 18, slits 18 from which the base tape 6 is linearly removed are provided between the openings 7. In FIG. 2, the wiring layer 5 is drawn on the entire surface of the base tape 6, but is actually patterned at positions corresponding to the pads, wiring, ball electrode lands, and slits.

本発明の第１の実施形態であるテープ状配線基板の作用、効果は、次に述べる本実施形態であるテープ状配線基板を用いた本発明の第２の実施形態である半導体装置と同じであるので、後述する。   The operation and effect of the tape-like wiring substrate according to the first embodiment of the present invention is the same as that of the semiconductor device according to the second embodiment of the present invention using the tape-like wiring substrate according to this embodiment described below. This will be described later.

本発明の第２の実施形態である半導体装置２は、その基材テープ側から半導体装置を見た図３及びそのＤ部断面図である図４に示すように、基材テープ６と配線層５からなるテープ状配線基板１の、前記配線層５を有する一主面に半導体チップ３が搭載され、他の主面に開口する前記基材テープ６の開口部７にボール電極１０が搭載され、前記半導体チップ３上の電極が前記ボール電極１０に電気的に接続された半導体装置２において、前記開口部７間に前記基材テープ６を線状に除去したスリット１８を有する。図３及び図４において、１０ａは、二次実装時の応力を分散し、緩和するためのダミーのボール電極を示している。   The semiconductor device 2 according to the second embodiment of the present invention includes a base tape 6 and a wiring layer, as shown in FIG. 3 when the semiconductor device is viewed from the base tape side and FIG. 5, a semiconductor chip 3 is mounted on one main surface having the wiring layer 5 and a ball electrode 10 is mounted on an opening 7 of the base tape 6 opened on the other main surface. In the semiconductor device 2 in which the electrode on the semiconductor chip 3 is electrically connected to the ball electrode 10, a slit 18 is formed between the openings 7 by removing the base tape 6 linearly. 3 and 4, reference numeral 10a denotes a dummy ball electrode for dispersing and relieving stress during secondary mounting.

このように、前記開口部７間に基材テープ６を線状に除去したスリット１８を有することが、本発明の第１の実施形態のテープ状配線基板及び第２の実施形態の半導体装置の特徴である。   As described above, the slit 18 from which the base tape 6 is linearly removed is provided between the openings 7 in the tape-like wiring board according to the first embodiment of the present invention and the semiconductor device according to the second embodiment. It is a feature.

本発明の第１の実施形態のテープ状配線基板及び第２の実施形態の半導体装置によれば、ボール電極用の開口部７間に基材テープ６を線状に除去したスリット１８が形成されているためスリット１８を挟んだ両側の基材テープ６の変位が容易になり、封止樹脂８と基材テープ６の線膨張率の差による応力が緩和され、半導体装置２の反りが実用上問題の無い程度に少なくなる。また、前記スリット１８は、テープ状配線基板１の製造時にボール電極用の開口部７と同時に、エッチングやレーザー加工で形成できるため、新たな設備や工程の追加が無くコストアップとなることがない。また、スリット１８を形成する位置に配線層５を形成しておくことにより、配線層５によってスリット１８を経由して半導体チップ３に至る水分の浸入経路が遮断でき、実装後の信頼性が悪化することが無いという優れた産業上の効果が得られる。   According to the tape-like wiring substrate of the first embodiment of the present invention and the semiconductor device of the second embodiment, the slit 18 is formed between the ball electrode openings 7 by removing the base tape 6 linearly. Therefore, the displacement of the base tape 6 on both sides across the slit 18 is facilitated, the stress due to the difference in linear expansion coefficient between the sealing resin 8 and the base tape 6 is relieved, and the warp of the semiconductor device 2 is practically used. It becomes less to the extent that there is no problem. Further, since the slit 18 can be formed by etching or laser processing simultaneously with the ball electrode opening 7 when the tape-like wiring substrate 1 is manufactured, there is no additional equipment or process, and the cost is not increased. . In addition, by forming the wiring layer 5 at the position where the slit 18 is formed, the wiring layer 5 can block the moisture intrusion route to the semiconductor chip 3 via the slit 18 and the reliability after mounting deteriorates. An excellent industrial effect is obtained.

一次実装後の封止樹脂と基材テープの線膨張率の差による応力は、半導体装置の四隅に行くほど封止樹脂と基材テープの伸縮の差が累積するため大きくなる。また、二次実装後の基材テープと実装基板の線膨張率の差による応力も同様に、半導体装置の四隅に行くほど大きくなる。従って、スリットは、図１及び図３に示すように、半導体装置２と実装基板を電気的に接続するボール電極１０と実装時の応力を分散、緩和するためのダミーのボール電極１０ａの間に形成するのが、一次及び二次実装時の応力緩和ができるため好ましい。   The stress due to the difference between the linear expansion coefficients of the sealing resin after the primary mounting and the base tape increases as the expansion / contraction difference between the sealing resin and the base tape accumulates toward the four corners of the semiconductor device. Similarly, the stress due to the difference in linear expansion coefficient between the base tape after the secondary mounting and the mounting substrate also increases toward the four corners of the semiconductor device. Therefore, as shown in FIG. 1 and FIG. 3, the slit is formed between the ball electrode 10 that electrically connects the semiconductor device 2 and the mounting substrate and the dummy ball electrode 10a for dispersing and relieving stress during mounting. Forming is preferable because stress relaxation during primary and secondary mounting can be achieved.

スリットの形状は、直線状である必要は無く、曲線状であっても良い。また、封止樹脂と基材テープの伸縮方向に直角な方向に設ける方が、応力緩和の点で好ましい。   The shape of the slit need not be linear, but may be curved. In addition, it is preferable in terms of stress relaxation that the sealing resin and the base tape are provided in a direction perpendicular to the expansion / contraction direction.

本発明の第３の実施形態である半導体装置は、図５に示すように、第２の実施形態である半導体装置で説明した前記スリットが、前記半導体装置の底面の隣り合う二辺を結んで形成されている。前記スリットが前記半導体装置の隣り合う二辺を結んで形成されていることにより、前記スリットを挟んだ基材テープ相互の変位がさらに容易になり、本発明の第２の実施形態である半導体装置よりも、半導体装置の四隅に集中する一次及び二次実装時の応力を緩和することができる。   As shown in FIG. 5, in the semiconductor device according to the third embodiment of the present invention, the slit described in the semiconductor device according to the second embodiment connects two adjacent sides of the bottom surface of the semiconductor device. Is formed. Since the slit is formed by connecting two adjacent sides of the semiconductor device, the mutual displacement between the base tapes sandwiching the slit is further facilitated, and the semiconductor device according to the second embodiment of the present invention. As a result, the stress at the time of primary and secondary mounting concentrated on the four corners of the semiconductor device can be relaxed.

本発明の第４の実施形態である半導体装置は、図６に示すように、第３の実施形態である半導体装置で説明した前記スリットに加え、前記半導体装置の底面の向い合う二辺を結んで形成されている。前記スリットが前記半導体装置の向い合う二辺を結んで形成されていることにより、前記スリットで分断されたサイズの半導体素子と同程度まで応力が緩和され、半導体装置の反りが一層改善される。   As shown in FIG. 6, the semiconductor device according to the fourth embodiment of the present invention connects two opposite sides of the bottom surface of the semiconductor device in addition to the slit described in the semiconductor device according to the third embodiment. It is formed with. Since the slit is formed by connecting two opposite sides of the semiconductor device, the stress is relieved to the same extent as the semiconductor element having a size divided by the slit, and the warpage of the semiconductor device is further improved.

なお、本発明の第３及び第４の実施形態の半導体装置において、前記スリットが前記半導体装置の一辺と他の辺を結ぶ配置であっても、基材テープは図８を用いて説明しためっき用配線１２の部分で繋がっているため、ばらばらになることは無い。   In the semiconductor devices of the third and fourth embodiments of the present invention, the base tape is the plating described with reference to FIG. 8 even if the slit is arranged to connect one side of the semiconductor device to the other side. Since it is connected at the portion of the wiring 12 for use, it does not fall apart.

本発明の第５の実施形態であるテープ状配線基板は、複数の半導体装置ブロックを有するテープ状配線基板を一体に樹脂封止した状態の半導体組立中間体の反りの低減に関するものである。   A tape-like wiring board according to a fifth embodiment of the present invention relates to a reduction in warpage of a semiconductor assembly intermediate in a state where a tape-like wiring board having a plurality of semiconductor device blocks is integrally resin-sealed.

本発明の第５の実施形態であるテープ状配線基板は、図７、そのＡ部拡大図である図８及びその断面図である図９に示すように、基材テープ６の一主面に、配線層５としてパッド１５、配線（図示せず）、ボール電極用ランド１６を有する複数の半導体装置ブロック１４が形成され、前記半導体装置ブロック１４間にめっき用配線１２を有するテープ状配線基板において、前記めっき用配線１２と接する前記基材テープ６の一部が線状に除去されたスリット１８を有する。   The tape-like wiring board according to the fifth embodiment of the present invention is formed on one main surface of the base tape 6 as shown in FIG. 7, FIG. 8 which is an enlarged view of the portion A, and FIG. In the tape-like wiring substrate, a plurality of semiconductor device blocks 14 having pads 15, wires (not shown) and ball electrode lands 16 are formed as the wiring layer 5, and the plating wires 12 are provided between the semiconductor device blocks 14. In addition, a part of the base tape 6 in contact with the plating wiring 12 has a slit 18 removed in a linear shape.

このように、前記めっき用配線１２と接する前記基材テープ６の一部が線状に除去されたスリット１８を有することが、本発明の第５の実施形態のテープ状配線基板の特徴である。   As described above, the tape-like wiring board according to the fifth embodiment of the present invention has the slit 18 in which a part of the base tape 6 in contact with the plating wiring 12 is linearly removed. .

本実施形態のテープ状配線基板によれば、めっき用配線と接する前記基材テープの一部が線状に除去されたスリットを有するため、複数の半導体装置ブロックの配列方向に累積した封止樹脂と基材テープの線膨張率の差による応力が緩和され、半導体組立中間体の反りが実用上問題の無い程度に少なくなる。   According to the tape-like wiring substrate of the present embodiment, since the part of the base tape in contact with the wiring for plating has a slit removed in a linear shape, the sealing resin accumulated in the arrangement direction of the plurality of semiconductor device blocks The stress due to the difference between the linear expansion coefficients of the base tape and the base tape is relieved, and the warpage of the semiconductor assembly intermediate is reduced to a level that causes no practical problems.

一般的な長方形のテープ状配線基板では長手方向の伸縮量が大きいので、半導体組立中間体である樹脂封止後のテープ状配線基板の応力を効果的に減らすため、できるだけテープ状配線基板の幅全体に渡って、また、できるだけ連続してスリット設ける方が有利である。しかし、配線層の無い部分にスリットを入れるとテープ状配線基板の強度が得られなくなる恐れがある。本実施形態は、連続したベタの配線層であるめっき用配線に着目し、その裏側の基材テープにスリットを設けることで、テープ状配線基板の強度と樹脂封止後の応力緩和を両立させたものである。これにより、図１８〜２０を用いて説明した従来技術では解決できなかった、個別の半導体装置となる複数の半導体装置ブロックを有するテープ状配線基板を一体に樹脂封止した状態の半導体組立中間体の応力を吸収し反りを低減することができる。   Since a general rectangular tape-shaped wiring board has a large amount of expansion and contraction in the longitudinal direction, the width of the tape-shaped wiring board is as small as possible in order to effectively reduce the stress of the tape-shaped wiring board after resin sealing, which is a semiconductor assembly intermediate. It is advantageous to provide slits throughout and as continuously as possible. However, if a slit is made in a portion where there is no wiring layer, the strength of the tape-like wiring board may not be obtained. This embodiment pays attention to the wiring for plating which is a continuous solid wiring layer, and by providing a slit in the base tape on the back side, the strength of the tape-like wiring board and the stress relaxation after resin sealing are made compatible. It is a thing. Thus, a semiconductor assembly intermediate in which a tape-like wiring board having a plurality of semiconductor device blocks to be individual semiconductor devices is integrally resin-sealed, which cannot be solved by the conventional technology described with reference to FIGS. Therefore, it is possible to reduce the warpage.

図８に示すように、めっき用配線１２は、主配線であるめっき用バスライン１２ａと、めっき用バスライン１２ａに接続され個々の半導体装置ブロック１４にめっき電流を供給するめっき用素子間配線１２ｂからなる。前記スリット１８は、図９に示すように、前記めっき用バスライン１２ａの位置と前記めっき用素子間配線１２ｂの位置の両方に形成可能である。また、前記めっき用素子間配線１２ｂの位置に形成するスリットはテープ状配線基板全面に形成できるため反り防止の効果が大きいが、テープ状配線基板の強度との兼ね合いで、全ての前記めっき用素子間配線１２ｂの位置に設けずに一行おき又は一列おき等のように適宜間引いて配置することができる。また、本実施形態のテープ状配線基板のスリットは、テープ状配線基板の強度確保のため、破線状、一点鎖線状に形成したり、めっき用配線の幅よりも小さい幅で形成しても良い。   As shown in FIG. 8, the plating wiring 12 includes a plating bus line 12a which is a main wiring, and an inter-plating element wiring 12b which is connected to the plating bus line 12a and supplies a plating current to each semiconductor device block 14. Consists of. As shown in FIG. 9, the slit 18 can be formed at both the position of the plating bus line 12a and the position of the plating inter-element wiring 12b. Further, the slits formed at the positions of the inter-plating element wirings 12b can be formed on the entire surface of the tape-like wiring board, so that the effect of preventing warpage is great. However, in consideration of the strength of the tape-like wiring board, Instead of being provided at the position of the inter-wiring line 12b, it can be arranged by being thinned out appropriately such as every other row or every other column. In addition, the slits of the tape-like wiring board of the present embodiment may be formed in a broken line shape, a one-dot chain line shape, or a width smaller than the width of the wiring for plating in order to ensure the strength of the tape-like wiring board. .

本発明のテープ状配線基板及び半導体装置によれば、ボール電極用の開口部間に基材テープを線状に除去したスリットが形成されているため、封止樹脂と基材テープの線膨張率の差による応力が緩和され、半導体装置の反りが実用上問題の無い程度に少なくなる。また、本発明のテープ状配線基板によれば、めっき用配線と接する前記基材テープの一部が線状に除去されたスリットを有するため、複数の半導体装置ブロックの配列方向に累積した封止樹脂と基材テープの線膨張率の差による応力が緩和され、半導体組立中間体の反りが実用上問題の無い程度に少なくなる。また、前記スリットは、テープ状配線基板の製造時にボール電極用の開口部と同時に、エッチングやレーザー加工で形成できるため、新たな設備や工程の追加が無くコストアップとなることがない。また、スリット形成位置に配線層を形成しておくことにより、配線層によってスリットを経由した水分の浸入が防止でき、実装後の信頼性が悪化することが無いという優れた産業上の効果が得られる。   According to the tape-like wiring board and the semiconductor device of the present invention, since the slit is formed by linearly removing the base tape between the ball electrode openings, the linear expansion coefficient between the sealing resin and the base tape is formed. The stress due to the difference is relaxed, and the warp of the semiconductor device is reduced to such a level that there is no practical problem. In addition, according to the tape-like wiring substrate of the present invention, since the part of the base tape in contact with the wiring for plating has a slit removed in a linear shape, the sealing accumulated in the arrangement direction of a plurality of semiconductor device blocks The stress due to the difference between the linear expansion coefficients of the resin and the base tape is alleviated, and the warpage of the semiconductor assembly intermediate is reduced to a level that causes no problem in practice. Further, since the slit can be formed by etching or laser processing at the same time as the opening for the ball electrode at the time of manufacturing the tape-like wiring substrate, there is no additional equipment or process and the cost is not increased. In addition, by forming a wiring layer at the slit formation position, it is possible to prevent moisture from entering through the slit by the wiring layer, and an excellent industrial effect that reliability after mounting is not deteriorated is obtained. It is done.

尚、本発明のテープ状配線基板及び半導体装置は、上記の実施例に限定されるものではなく、例えば、半導体チップを本発明のテープ状配線基板にフリップチップ接続を用いて搭載する等、本発明の要旨を逸脱しない範囲内において種々変更を加え得る。   The tape-like wiring board and the semiconductor device of the present invention are not limited to the above-described embodiments. For example, the semiconductor chip is mounted on the tape-shaped wiring board of the present invention using flip chip connection. Various changes can be made without departing from the scope of the invention.

本発明の第１の実施形態のテープ状配線基板を示す平面図。The top view which shows the tape-shaped wiring board of the 1st Embodiment of this invention. 本発明の第１の実施形態のテープ状配線基板を示す断面図。Sectional drawing which shows the tape-shaped wiring board of the 1st Embodiment of this invention. 本発明の第２の実施形態の半導体装置を示す平面図。The top view which shows the semiconductor device of the 2nd Embodiment of this invention. 本発明の第２の実施形態の半導体装置を示す断面図。Sectional drawing which shows the semiconductor device of the 2nd Embodiment of this invention. 本発明の第３の実施形態の半導体装置を示す平面図。The top view which shows the semiconductor device of the 3rd Embodiment of this invention. 本発明の第４の実施形態の半導体装置を示す平面図。The top view which shows the semiconductor device of the 4th Embodiment of this invention. 本発明の第５の実施形態のテープ状配線基板を示す平面図。The top view which shows the tape-shaped wiring board of the 5th Embodiment of this invention. 図７のＡ部拡大平面図。The A section enlarged plan view of FIG. 図８の断面図。FIG. 9 is a cross-sectional view of FIG. 8. 従来のテープ状配線基板を示す平面図。The top view which shows the conventional tape-shaped wiring board. 図１０のＡ部拡大平面図。The A section enlarged plan view of FIG. 従来の半導体装置の製造方法を説明する平面図。The top view explaining the manufacturing method of the conventional semiconductor device. （ａ）従来の半導体装置の製造方法を説明する平面図。 （ｂ）従来の半導体装置の製造方法を説明する断面図。(A) The top view explaining the manufacturing method of the conventional semiconductor device. (B) Sectional drawing explaining the manufacturing method of the conventional semiconductor device. 図１３（ａ）のＢ部拡大断面図。The B section expanded sectional view of Drawing 13 (a). 従来の半導体装置を示す断面図。Sectional drawing which shows the conventional semiconductor device. 従来の別の半導体装置を示す断面図。Sectional drawing which shows another conventional semiconductor device. 従来の半導体装置のボール電極の配置を説明する平面図。The top view explaining arrangement | positioning of the ball electrode of the conventional semiconductor device. 従来のさらに別の半導体装置を説明する断面図。Sectional drawing explaining another conventional semiconductor device. 従来のさらに別の半導体装置を説明する断面図。Sectional drawing explaining another conventional semiconductor device. 従来のさらに別の半導体装置を説明する断面図。Sectional drawing explaining another conventional semiconductor device.

符号の説明Explanation of symbols

１ テープ状配線基板
２ 半導体装置
３ 半導体チップ
４ 金線
５ 配線層
６ 基材テープ
７ 開口部
８ 封止樹脂
９ ダイボンディング材
１０ ボール電極
１０ａ ダミーのボール電極
１１ はんだ等の導体
１２ めっき用配線
１２ａ めっき用バスライン
１２ｂ めっき用素子間配線
１３ スプロケットホール
１４ 半導体装置ブロック
１５ パッド
１６ ボール電極用ランド
１７ 半導体組立中間体
１８ スリット
１９ 熱膨張隔差緩和部
２０ はんだバンプ
２１ パッド（ランド）
２２ 配線基板
２３ アンダーフィル樹脂
２４ 凹部（溝）
２５ ガラスセラミック配線基板
２６ 実装基板
DESCRIPTION OF SYMBOLS 1 Tape-like wiring board 2 Semiconductor device 3 Semiconductor chip 4 Gold wire 5 Wiring layer 6 Base material tape 7 Opening part 8 Sealing resin 9 Die bonding material 10 Ball electrode 10a Dummy ball electrode 11 Conductor 12 such as solder Plating wiring 12a Plating bus line 12b Plating inter-element wiring 13 Sprocket hole 14 Semiconductor device block 15 Pad 16 Ball electrode land 17 Semiconductor assembly intermediate 18 Slit 19 Thermal expansion difference relaxation part 20 Solder bump 21 Pad (land)
22 Wiring board 23 Underfill resin 24 Recess (groove)
25 Glass ceramic wiring board 26 Mounting board

Claims (5)

基材テープの一主面に、パッド、配線、ボール電極用ランドがパターニングされた配線層が形成され、基材テープの他の主面から前記ボール電極用ランドに至る開口部を有するテープ状配線基板において、前記開口部間に前記基材テープを線状に除去したスリットを有することを特徴とするテープ状配線基板。   A tape-like wiring having a wiring layer formed by patterning pads, wiring, and ball electrode lands on one main surface of the base tape, and having an opening extending from the other main surface of the base tape to the ball electrode land. The board | substrate has a slit which removed the said base material tape linearly between the said opening parts, The tape-shaped wiring board characterized by the above-mentioned. 基材テープと配線層からなるテープ状配線基板の、前記配線層を有する一主面に半導体チップが搭載され、他の主面に開口する前記基材テープの開口部にボール電極が搭載され、前記半導体チップ上の電極が前記ボール電極に電気的に接続された半導体装置において、前記開口部間に前記基材テープを線状に除去したスリットを有することを特徴とする半導体装置。   A semiconductor chip is mounted on one main surface having the wiring layer of a tape-shaped wiring board composed of a base tape and a wiring layer, and a ball electrode is mounted on an opening of the base tape that opens on the other main surface, A semiconductor device in which an electrode on the semiconductor chip is electrically connected to the ball electrode, wherein the semiconductor device has a slit formed by linearly removing the base tape between the openings. 請求項２記載の半導体装置において、前記スリットが、前記半導体装置の底面の隣り合う二辺を結ぶ形状であることを特徴とする半導体装置。   3. The semiconductor device according to claim 2, wherein the slit has a shape connecting two adjacent sides of the bottom surface of the semiconductor device. 請求項２記載の半導体装置において、前記スリットが、前記半導体装置の底面の向い合う二辺を結ぶ形状であることを特徴とする半導体装置。   3. The semiconductor device according to claim 2, wherein the slit has a shape connecting two opposite sides of the bottom surface of the semiconductor device. 基材テープの一主面に、配線層としてパッド、配線、ボール電極用ランドを有する複数の半導体装置ブロックが形成され、前記半導体装置ブロック間にめっき用配線を有するテープ状配線基板において、前記めっき用配線と接する前記基材テープの一部が線状に除去されたスリットを有することを特徴とするテープ状配線基板。
In a tape-like wiring board in which a plurality of semiconductor device blocks having pads, wires, and ball electrode lands as wiring layers are formed on one main surface of a base tape, and plating wires are provided between the semiconductor device blocks, the plating A tape-like wiring board comprising a slit in which a part of the base tape in contact with the wiring for use is linearly removed.
JP2006063164A 2006-03-08 2006-03-08 Tape-like wiring substrate and semiconductor device Pending JP2007242890A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009182004A (en) * 2008-01-29 2009-08-13 Elpida Memory Inc Semiconductor device
US9280173B2 (en) 2013-07-04 2016-03-08 Kabushiki Kaisha Toshiba Electronic device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000012732A (en) * 1998-06-24 2000-01-14 Rohm Co Ltd Structure of bga-type semiconductor device
JP2000058594A (en) * 1998-08-04 2000-02-25 Nec Corp Semiconductor device and manufacture thereof
JP2003289122A (en) * 2003-04-28 2003-10-10 Hitachi Ltd Ball-grid-array type semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000012732A (en) * 1998-06-24 2000-01-14 Rohm Co Ltd Structure of bga-type semiconductor device
JP2000058594A (en) * 1998-08-04 2000-02-25 Nec Corp Semiconductor device and manufacture thereof
JP2003289122A (en) * 2003-04-28 2003-10-10 Hitachi Ltd Ball-grid-array type semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009182004A (en) * 2008-01-29 2009-08-13 Elpida Memory Inc Semiconductor device
US9280173B2 (en) 2013-07-04 2016-03-08 Kabushiki Kaisha Toshiba Electronic device

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