JP4942452B2 - Circuit equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an insertion mount circuit device where a semiconductor device having multiple electrodes is assembled, and to provide a manufacturing method of the same. <P>SOLUTION: The circuit device 10 includes: a base material 15 where a first wiring layer 16 and a second wiring layer 17 are arranged on the upper surface and the lower surface; a first circuit element (a semiconductor element 20A, etc.) and a second circuit element (a package 12A, etc.) arranged on the upper surface and lower surface of a wiring substrate 11; and a seal resin 14 for covering the main surface of the wiring substrate 11, thereby sealing the first circuit element (the semiconductor element 20A, etc.) and metallic fine wire to be used for the connection. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

  The present invention relates to a circuit device and a manufacturing method thereof, and more particularly, to a circuit device provided with an external connection electrode for insertion mounting and a manufacturing method thereof.

  As electronic devices such as mobile phones become smaller and more functional, circuit devices housed therein are mainly provided with a multilayer wiring layer. A circuit device having a multilayer substrate 107 will be described with reference to FIG.

  Here, a circuit device is configured by mounting circuit elements such as a package 105 on the first wiring layer 102 </ b> A formed on the upper surface of the multilayer substrate 107.

  In the multilayer substrate 107, wiring layers are formed on the front surface and the back surface of the base material 101 made of a resin such as glass epoxy. Here, the first wiring layer 102 </ b> A and the second wiring layer 102 </ b> B are formed on the upper surface of the substrate 101. The first wiring layer 102A and the second wiring layer 102B are stacked with an insulating layer 103 interposed therebetween. A third wiring layer 102 </ b> C and a fourth wiring layer 102 </ b> D are stacked on the lower surface of the substrate 101 with an insulating layer 103 interposed therebetween. Each wiring layer is connected at a predetermined location by a connecting portion 104 provided through the insulating layer 103.

  A package 105 is fixed to the uppermost first wiring layer 102A. Here, the package 105 in which the semiconductor element 105A is resin-sealed is surface-mounted via a connection electrode 106 made of solder or the like. In addition to the package 105, passive elements such as chip capacitors and chip resistors, bare semiconductor elements, and the like may be mounted on the surface of the multilayer substrate 107. Here, the thickness of the multilayer substrate 107 is, for example, about 1 mm.

  A method for manufacturing the multilayer substrate 107 having the above-described configuration is as follows. First, the second wiring layer 102B and the third wiring layer 102C are formed on the upper and lower surfaces of the base material 101 made of a resin-based material such as an epoxy resin. These wiring layers are formed by etching or selective plating treatment of the attached conductive foil. Next, the second wiring layer 102B and the third wiring layer 102C are covered with an insulating layer 103 made of resin. Further, a first wiring layer 102A and a fourth wiring layer 102D are formed on the surface of the insulating layer 103. The method of forming these wiring layers is the same as that of the second wiring layer 102B and the like described above. Further, a connection portion 104 that penetrates the insulating layer 103 and connects the first wiring layer 102A and the second wiring layer 102B is formed.

  In the circuit device having the above-described configuration, a bonding material such as solder is welded to the pad-shaped fourth wiring layer 102D formed on the lower surface of the multilayer substrate 107, and is mounted on a motherboard such as a computer or a television. Such a mounting form is generally called surface mounting. However, when surface mounting is performed, at least the planar area of the multilayer substrate 107 is required for mounting the circuit device, and there is a problem that it is difficult to improve the mounting density of the mother board.

One method of solving this problem is to provide an external connection electrode on the end of the substrate and perform mounting by insertion. Technical matters relating to this insertion mounting are described, for example, in Patent Document 2 below. Referring to FIG. 1 of Patent Document 2, a cut portion is provided in the first printed circuit board 21, and a second printed circuit board 41 is inserted and mounted in the cut portion. By performing such insertion mounting, it is possible to reduce the area required for mounting as compared with the case of surface mounting, and it is possible to improve the mounting density on the mother board side to be inserted and mounted.
JP 2002-182270 A JP 2000-31615 A

  However, the technique described in Patent Document 2 described above only describes that a plurality of electronic components are mounted on the side of the board to be inserted, and a bare LSI having a large number of electrodes formed on the surface thereof. Is not considered at all. Further, there has not been proposed a manufacturing method that can efficiently manufacture a circuit device in which a plurality of circuit devices such as LSI are incorporated and mounted.

  The present invention has been made in view of such problems, and a main object of the present invention is to provide a plug-in circuit device incorporating a semiconductor device having a large number of electrodes and a method for manufacturing the same. There is.

The circuit device of the present invention has a first side and a second side opposite to each other, and a third side and a fourth side opposite to each other, and the third side along the first side from the third side. A wiring board having an external connection region provided over the fourth side, and an element placement region surrounded by the external connection region, the second side, the third side, and the fourth side; A plurality of external connection electrodes provided on the first main surface of the wiring board along the first side in the external connection region; and a first wiring layer provided on the first main surface of the wiring board; A first circuit element that is electrically connected and disposed in the element arrangement region; and a sealing resin that seals the element arrangement region and the first circuit element; Side surfaces of the wiring board and side surfaces of the sealing resin corresponding to the second side, the third side, and the fourth side , Ri Do from the side which is separated by dicing, the side surface of the sealing resin which is located between the external connection region and the element arrangement region, abutment surface der of a mold for sealing the sealing resin It is characterized by that.

  According to the circuit device of the present invention, the first circuit element having a large number of electrodes is mounted on the main surface of the wiring board to be inserted and mounted, and the first wiring and the first circuit element on the wiring board are connected to the fine metal wire. Connected via. Further, the main surface of the wiring board is covered with a sealing resin so that the fine metal wire and the first circuit element are sealed. With this configuration, for example, even when a bare LSI having several hundred electrodes is mounted on a wiring board of a circuit device to be plugged and mounted, the LSI and the fine metal wire are covered and protected by a sealing resin. The risk of short-circuiting or disconnection of fine wires can be eliminated.

  In particular, when the pitch between the electrodes formed on the surface of the semiconductor element is about 50 μm or less, it becomes difficult to attach a bump electrode made of solder to this electrode and to flip-chip connect the semiconductor element. Therefore, in the present invention, when a semiconductor element having an electrode with a narrow pitch is applied to a plug-in type circuit device, a metal wire is used for connecting the semiconductor element, and the semiconductor element and the metal wire are sealed with resin.

  Furthermore, according to the method of manufacturing a circuit device of the present invention, the substrate is provided with a block in which a plurality of units are arranged with an external connection region provided with an external electrode to be inserted and mounted outside. Further, after a plurality of units are integrally molded with the sealing resin for each block, the sealing resin and the substrate are separated at the boundary between the units to obtain individual circuit devices. Therefore, since it is not necessary to form the sealing resin for each unit (for each circuit device), the cost for resin sealing is reduced.

  With reference to FIG. 1, the configuration of the circuit device 10 of the present embodiment will be described. 1A is a plan view of the circuit device 10 as viewed from above, FIG. 1B is a plan view of the circuit device 10 as viewed from below, and FIG. 1C is a cross-sectional view of the circuit device 10. FIG. 1D is a perspective view of the circuit device 10.

  Referring to each drawing of FIG. 1, a circuit device 10 of this embodiment includes a wiring board 11 including a base material 15 provided with a first wiring layer 16 and a second wiring layer 17 on an upper surface and a lower surface, and a wiring board 11. The first circuit element (semiconductor element 20A, etc.) and the second circuit element (package 12A, etc.), the first circuit element (semiconductor element 20A, etc.) arranged on the lower surface and the upper surface of the semiconductor device, and the fine metal wires used for the connection are sealed. A sealing resin 14 that covers the main surface of the wiring board 11 is mainly provided so as to be stopped. Furthermore, the circuit device 10 according to the present embodiment is mounted by insertion using an external connection electrode 13 provided along one side of the wiring board 11 and is mounted by insertion on a mother board (not shown) or the like.

  The wiring board 11 includes a base material 15 having a first wiring layer 16 and a second wiring layer 17 formed on the lower surface and the upper surface. Here, the base material 15 is made of a resin material such as glass epoxy in which an epoxy resin is impregnated into a fibrous filler, and has a mechanical strength that does not cause bending or cracking even when pressure is applied during insertion mounting. Have For example, a glass epoxy substrate having a thickness of about 0.5 mm to 1.0 mm has sufficient mechanical strength and can be used as the base material 15.

  The first wiring layer 16 and the second wiring layer 17 are wiring layers made of a metal such as copper provided on each main surface of the base material 15. Here, the first wiring layer 16 and the second wiring layer 17 have a single-layer wiring structure in the figure, but the first wiring layer 16 is formed from a wiring layer formed in two or more layers via an insulating layer. It is also possible to configure the second wiring layer 17. In this case, the multilayer first wiring layers 16 stacked via the insulating layer are connected through the insulating layer. This matter is the same even when the second wiring layer 17 is formed in multiple layers. Further, a through connection portion 23 made of a conductive material provided through the base material 15 in the thickness direction may be provided, and the first wiring layer 16 and the second wiring layer 17 may be electrically connected by the through connection portion 23.

  The first wiring layer 16 and the second wiring layer 17 described above are covered with a coating resin except for a region that becomes an electrical connection region (for example, a pad). Specifically, referring to FIG. 1C, the second wiring layer 17 formed on the upper surface of the base material 15 is covered with the coating resin 21, and the pad 17 </ b> A that is a part of the second wiring layer 17 is formed. The upper surface is exposed without being covered with the coating resin 21. Further, the upper surface of the pad 17A exposed from the coating resin 21 is covered with a plating film 19 made of, for example, gold plating. The first wiring layer 16 formed on the lower surface of the substrate 15 is covered with the coating resin 22, and the surface of the pad 16 </ b> A that is a part of the first wiring layer 16 is partially exposed from the coating resin 22. Yes. Here, the coating resin 22 does not cover the entire surface of the wiring substrate 11, but the coating resin 22 is not formed in the peripheral portion of the lower surface of the wiring substrate 11, and the periphery of the exposed base material 15. The lower surface of the part is covered with a sealing resin 14.

  Referring to FIG. 1C, a package 12A and a chip element 12B are electrically connected as circuit elements to the second wiring layer 17 formed on the upper surface of the wiring board 11. The structure of the package 12A will be described. The semiconductor element 18 fixed to the land is resin-sealed, and a plurality of leads 25 electrically connected to the semiconductor element 18 are externally exposed from two opposing sides of the package 12A. Has been derived. Then, the lead 25 of the package 12A is joined to the upper surface of the pad 17A made of the second wiring layer 17 via a conductive adhesive such as solder. Further, the chip element 12B is a chip capacitor, a chip resistor, or the like, and electrodes at both ends are joined to the pad 17A via solder. Here, as the circuit elements connected to the second wiring layer 17, in addition to the above-described elements, there are a resin-sealed package disposed by surface mounting, a semiconductor element (LSI) mounted by flip chip mounting, and the like. It can be adopted.

  Furthermore, as a circuit element connected to the second wiring layer 17, an element (crystal oscillator) that internally performs crystal vibration can be employed. Since the characteristics of such an element deteriorate when pressure is applied, the predetermined characteristics can be ensured by exposing the element to the outside without sealing with the sealing resin 14.

  Furthermore, the pad 17A to which the chip element 12B is connected is preferably on the lower surface of the wiring board 11 directly above the pad 16A to which the semiconductor element 20B is connected (a position overlapping in a plane). In this way, when the chip element 12B is a capacitor that absorbs noise, the distance between the chip element 12B and the semiconductor element 20B can be shortened, so that the chip element 12B that is a capacitor absorbs noise. Can be increased.

  Furthermore, semiconductor elements 20A and 20B are connected to the first wiring layer 16 formed on the lower surface of the wiring board 11. The semiconductor element 20 </ b> A is arranged face-down on the lower surface of the wiring substrate 11, and its electrode is connected to a pad 16 </ b> A formed of a part of the first wiring layer 16 via a fine metal wire 24. The semiconductor element 20A is, for example, a system LSI or the like in which a large number of electrodes of about 200 or more are provided on the surface. Further, the semiconductor element 20B is arranged face down (flip chip mounting) on the lower surface of the wiring substrate 11, and the electrodes provided on the surface are pads 16A made of the first wiring layer 16 via bump electrodes such as solder balls. To be joined. A pad 16A made of the first wiring layer 16 is provided on the lower surface of the wiring substrate 11 in the region where the semiconductor element 20B is disposed, corresponding to the electrodes provided on the semiconductor element 20B.

  A large number of external connection electrodes 13 are provided along one side (the left side in the figure) of the wiring board 11 shown in FIG. The external connection electrode 13 is composed of, for example, a first wiring layer 16 or a second wiring layer 17 formed in a pad shape of length × width = 2 mm × 1 mm. Here, the external connection electrodes 13 are provided on both the upper surface and the lower surface along one side of the wiring board 11, but the external connection electrodes 13 may be provided only on one of the surfaces. The upper surface of the external connection electrode 13 is covered with a plating film such as gold plating.

  The sealing resin 14 is made of a thermosetting resin or a thermoplastic resin, and is formed so as to cover the lower surface of the wiring board 11 and the semiconductor elements 20A and 20B arranged there in FIG. In order to improve the heat dissipation of the semiconductor element 20A or the like, the sealing resin 14 may be made of a resin material mixed with an inorganic filler such as silica. As a method for forming the sealing resin 14, transfer molding, injection molding, potting, and the like are conceivable. Referring to FIG. 1B, the three side edges (upper side, right side, and lower side) of the wiring board 11 are covered with the sealing resin 14 up to the terminal portion of the wiring board 11. On the other hand, the peripheral portion of the wiring substrate 11 on the left side where a large number of external connection electrodes 13 are provided is not formed with the sealing resin 14, and the main surface of the external connection electrode 13 and the peripheral wiring substrate 11 is external. Is exposed. This is because the wiring board 11 in the region where the external connection electrodes 13 are provided is inserted and mounted on a mother board or the like. Here, by forming the sealing resin 14, the mechanical strength of the entire device is reinforced, and there is an advantage that bending or the like when the circuit device 10 is inserted and mounted is suppressed.

  Referring to FIG. 1D, the peripheral portion of the main surface of wiring substrate 11 on which sealing resin 14 is formed is not covered with coating resin 22 but is in contact with sealing resin 14. In other words, the outer peripheral end of the coating resin 22 is located inside the outer peripheral end of the wiring board 11. This has the advantage that the number of boundaries between different materials exposed to the outside can be reduced, and the pressure resistance and moisture resistance can be improved. Specifically, the coating resin 22 has a function of covering the first wiring layer 16 formed on the upper surface of the wiring substrate 11 to prevent short circuits and contamination, and is generally called a solder resist. Further, the coating resin 22 and the sealing resin 14 having such a function are different in composition even if they are the same resin material. Therefore, when the entire upper surface of the wiring board 11 is covered with the coating resin 22, the boundary between the coating resin 22 and the sealing resin 14 is exposed on the side surface of the circuit device 10 in addition to the boundary between the other materials. The moisture resistance of the circuit device 10 may be deteriorated when moisture enters from the boundary to the inside.

  Therefore, in this embodiment, the coating resin 22 is removed in a region corresponding to the peripheral edge of the wiring board 11 to expose the wiring board 11, and the sealing resin 14 is brought into close contact with the exposed peripheral part of the wiring board 11. ing. As a result, the number of boundaries between different materials exposed from the side surface of the circuit device 10 is reduced, and the moisture resistance is improved. Specifically, the terminal portions of the three sides (the left side, the upper side, and the right side with reference to FIG. 1D) of the main surface of the wiring substrate 11 on which the sealing resin 14 is formed. The coating resin 22 for covering is removed. For example, on the three sides of the wiring board 11, the base material 15 of the wiring board 11 is exposed without being covered with the coating resin 22 in the region of about 2 mm to 0.5 mm from the terminal portion. In this region, since the sealing resin 14 is in close contact with the base material 15 of the wiring board 11, the boundary between different materials exposed on the side surface of the circuit device 10 is reduced, and the moisture resistance and the like are improved.

  Here, when the wiring substrate 11 is provided with the multilayer first wiring layer 16 laminated via the interlayer insulating layer, the interlayer resin layer 22 is removed by removing the coating resin 22 located in the peripheral portion of the wiring substrate 11. The insulating layer is exposed and is in close contact with the sealing resin 14.

  Further, since the first wiring layer 16 and the second wiring layer 17 are located on the inner side of the outer peripheral end portion of the wiring substrate 11, both wiring layers are not exposed from the side surface of the circuit device 10, and both the outside and both sides are exposed. It is well insulated from the wiring layer.

  In this embodiment, referring to FIG. 1C, a semiconductor element 20A (for example, a system LSI) provided with a large number (for example, several hundreds) of electrodes and connected via a thin metal wire 24 is connected to the wiring substrate 11. A sealing resin 14 is formed on the lower surface so that the semiconductor element 20A and the fine metal wires 24 are sealed. Further, the semiconductor element 20B to be flip-chip mounted is also sealed with the sealing resin 14. As a result, the semiconductor elements 20A and 20B and the fine metal wires 24 are covered and protected by the sealing resin 14, so that damage to the semiconductor elements 20A and disconnection / deformation of the fine metal wires 24 are suppressed. Therefore, a system LSI or the like that has conventionally been difficult to place on a board to be plugged in can be taken into the circuit device 10 to be plugged in.

  On the other hand, referring to FIG. 1C, the elements arranged on the upper surface of the wiring substrate 11 are a package 12A and a chip element 12B, and are exposed to the outside without being sealed with a sealing resin. All (or most) of these circuit elements are surface-mounted using a conductive adhesive such as solder, and there is a danger of short-circuiting compared to the semiconductor element 20A or the like connected by a thin metal wire. Is a low circuit element. Therefore, manufacturing cost can be reduced by not covering such a circuit element with sealing resin. However, in order to improve connection reliability, a sealing resin having the same configuration as the sealing resin 14 may be provided on the upper surface of the wiring substrate 11 so as to cover the package 12A and the like.

  Furthermore, since the lower surface of the sealing resin 14 formed by transfer molding using a mold is a flat surface, a heat radiator such as a heat radiating fin is brought into contact with the flat surface of the sealing resin 14 to thereby provide a semiconductor element. Heat generated from 20A or the like can be released to the outside via the sealing resin 14 and the radiator.

  Further, referring to FIG. 1C, the coating resins 21 and 22 are removed from the portion of the wiring substrate 11 where the external connection electrodes 13 are provided. Thus, by not providing the coating resin in the vicinity of the external connection electrode 13, it is possible to improve the contact property between the external connection electrode 13 and the outside during insertion mounting.

  Further, referring to FIG. 1A, a portion of the wiring board 11 provided with the external connection electrode 13 is provided with a cut portion 26 from which the wiring board 11 has been partially removed. For this reason, the width of the portion of the wiring substrate 11 where the external connection electrode 13 is provided (the length in the vertical direction of this portion on the paper surface) is shorter than the other portions of the wiring substrate 11. Therefore, when the wiring board 11 is inserted and mounted, the terminal portion of the cut portion 26 comes into contact with the mounting board on the side to be mounted and functions as a stopper that suppresses excessive insertion of the wiring board 11.

  Furthermore, referring to FIG. 1A, a slit 27 is provided by partially removing an intermediate portion of the side of the wiring substrate 11 provided with the external connection electrode 13. The slit 27 is provided in a portion (lower side or upper side) of the wiring board 11 from which the central portion in the vertical direction is removed, and points in a direction opposite to the original direction when the circuit device 10 is inserted and mounted. This is to prevent the reverse (reverse).

  Next, a method for manufacturing the circuit device having the above-described configuration will be described with reference to FIGS. The method for manufacturing a circuit device according to the present embodiment includes a step of preparing a substrate 30 provided with a block composed of a unit that is a wiring substrate for insertion mounting, a step of arranging circuit elements in the unit of the substrate 30; The process mainly includes a step of forming a sealing resin in common for each block so as to cover the circuit elements, and a step of dividing the sealing resin and the substrate 30 at the boundary between the units to obtain individual circuit devices. ing. Details of each of these steps will be described below.

  Here, each said process may be performed consistently in one factory, and the process until it forms the board | substrate 30 and the process after it may be performed in another factory. That is, the board 30 having the shape shown in FIG. 2 may be prepared, and the board-mounted circuit device may be manufactured using the board 30 in this state.

  The configuration of the substrate 30 will be described with reference to FIG. 2A is a plan view showing the entire substrate 30, FIG. 2B is an enlarged plan view showing one block 31 included in the substrate 30, and FIG. FIG.

  Referring to FIG. 2A, four blocks 31 are arranged on the substrate 30 so as to be separated from each other, and have a strip shape as a whole. Between each block 31, there is provided a slit 32 provided by removing the substrate 30 through the thickness direction. By providing the slit 32, even if the substrate 30 heated to about 200 degrees in a process involving heating such as a bonding process is thermally expanded, the expansion is absorbed by the deformation of the slit 32. Overall warpage and the like are suppressed.

  Two support portions 34 extend at the upper and lower ends of the substrate 30 on the paper surface, and connect the plurality of blocks 31 to an integrated plate-like body. The structure of the support part 34 is the same as that of the block 31, and thin conductive foil is stuck on both surfaces of the base material 15 made of glass epoxy or the like. Further, a guide hole 33 is provided by drilling the support portion 34 in a circular shape in the thickness direction, and this guide hole 33 is used when positioning and transporting the substrate 30 when manufacturing the circuit device. . For example, the board 30 can be transported and positioned by inserting and moving the protrusions of the circuit device manufacturing machine into the guide holes 33. Here, the guide hole 33 is formed through the region where the conductive foil of the support portion 34 is provided.

  Referring to FIG. 2B, two units 35A and 35B are provided inside one block 31. Here, the unit is a unit element constituting one circuit device. Two or more (for example, four or eight) units may be built in the block 31 with the external connection area outside.

  The unit 35A located on the left side on the paper surface includes an external connection region 36A that is a portion to be inserted into a motherboard or the like when plugging and mounting, and an element arrangement region 37A that is a region in which circuit elements such as semiconductor elements are arranged. Consists of. In the external connection region 36A, a large number of external connection electrodes 13 are arranged on the surface along the side. Further, the element arrangement region 37A is provided with a pad 17A to which a semiconductor element is electrically connected in a later process. In addition, the external connection electrode 13 and the pad 17A configured inside the unit 35A are connected to each other via a wiring portion formed of a wiring layer. The unit 35B located on the right side on the paper has the same configuration as the unit 35A described above, and includes an external connection region 36B in which a large number of external connection electrodes 13 are arranged, and an element arrangement region 37B in which circuit elements are arranged. It consists of.

  Inside the block 31, the unit 35A and the unit 35B are adjacent to each other with the external connection area being outside. That is, the external connection area 36A of the unit 35A located on the left side of the block 31 is located on the left side, and the external connection area 36B of the unit 35B located on the right side of the block 31 is located on the right side. The element placement area 37A of the unit 35A and the element placement area 37B of the unit 35B are adjacent to each other inside the block 31. As a result, the element arrangement area 37A of the unit 35A and the element arrangement area 37B of the unit 35B are integrally molded with a sealing resin, and the external connection areas 36A and 36B of both units are exposed to the outside. can do. A specific molding method will be described later.

  The removal region 38 is a region where the conductive foil formed on the upper surface of the base material is removed in the region between the units 35A and 35B and the region between the units 35A and 35B and the support portion 34. . That is, the resin material (for example, the base material 15) constituting the substrate 30 is exposed from the removal region 38. A region between the block 31 and the support portion 34 and a region between the unit 35A and the unit 35B included in the block 31 are cut by dicing in a later step. Therefore, by removing the conductive foil in such a region to form the removal region 38, it is possible to suppress dicer wear and burr generation during dicing.

  Further, the removal region 39 is a region provided inside the above-described removal region 38, and in this removal region 39, the coating resin 22 that is a solder resist that covers the surface of the substrate 30 in the block 31 is removed. . Therefore, the base material 15 located in the lower layer of the conductive foil is exposed inside the removal region 39. For this reason, when the surface of the substrate 30 is covered with the sealing resin, the sealing resin directly contacts a resin material such as a base material constituting the substrate 30 in the removal region 39. Further, in a subsequent process, the sealing resin and the substrate 30 are separated by dicing in the removal region 39. As described above, since the coating resin 22 that is a solder resist is removed, the interface of the dissimilar material in the portion divided by dicing is reduced, and the moisture resistance and the like are improved.

  FIG. 2C is a cross-sectional view in the vertical direction of the block shown in FIG. Referring to this figure, substrate 30 (particularly support portion 34) is composed of base material 15 and conductive foils 45 and 46 formed on both surfaces thereof. The base material 15 is made of a resin material such as a glass epoxy substrate having a thickness of about 0.5 mm to 1.0 mm, for example, and bears the mechanical strength of the entire substrate 30. Since the conductive foil 45 is made of a metal film such as copper having a thickness of about several tens of μm adhered to the upper surface of the base material 15, by selectively etching this metal film, a fine wiring or a small pad can be obtained. Can be formed. The conductive foil 46 is a metal film adhered to the lower surface of the substrate 15, and the configuration thereof is the same as that of the conductive foil 45. Here, when a multilayer wiring structure is formed on the upper surface and the lower surface of the base material 15, the conductive foils 45 and 46 are laminated in a multilayer via an interlayer insulating layer.

  Inside the block 31, the first wiring layer 16 and the second wiring layer 17 are formed by etching the conductive foils 45 and 46. Further, a through connection portion 23 that connects the first wiring layer 16 and the second wiring layer 17 through the base material 15 may be provided.

  In the support portions 34 located at both ends of the substrate 30, the conductive foils 45 and 46 are not etched and are in a solid state. By doing in this way, the mechanical strength of the support part 34 can be improved and the curvature of the board | substrate 30 whole can be suppressed.

  As is clear from the cross-sectional view of FIG. 2C, the conductive foils 45 and 46 are removed in the removal region 38. Therefore, even if the substrate 30 is divided by dicing in the removal region 38, the dicer used for dicing divides only the base material 15 that is an insulating material constituting the substrate 30 and does not contact the conductive foil 45. . For this reason, wear of the dicer and generation of burrs can be suppressed.

  Further, referring to FIG. 2C, the removal region 39 is located inside the removal region 38 and is a region from which the coating resin 22 that covers the first wiring layer 16 has been removed. In the removal region 39, a dicing line D (the substrate 30 is divided along the dicing line D in a later step) is located inside. Since the coating resin 22 is removed and does not exist in the removal region 38, as described above, the boundary between the base material 15 and the coating resin 22 is not exposed to the outer peripheral end, and the moisture resistance and the like are improved.

  Here, the region corresponding to the removal region 39 may also be removed from the coating resin 21 that covers the lower surface of the substrate 15. In this case, the moisture resistance can be improved without exposing the boundary between the base material 15 and the coating resin 21 from the side surface of the outer peripheral end portion of the manufactured circuit device.

  In FIG. 2B, only the upper surface of the block 31 is illustrated, but the lower surface side of the block 31 has substantially the same configuration as the upper surface, and the pad 17A, the external connection electrode 13 and the like are on the lower surface of the block 31. It may be provided. Furthermore, removal regions 38 and 39 may be provided on the back side of the block 31 in the same region as the top surface.

  Referring to FIG. 3, next, circuit elements are electrically connected to the wiring layers of each unit. FIG. 3A is a plan view showing this step, and FIG. 3B is a cross-sectional view of the unit area included in the block 31.

  Referring to FIG. 3A, for each of units 35 </ b> A and 35 </ b> B included in block 31, a circuit element is electrically connected to first wiring layer 16 exposed on the upper surface of substrate 30. Specifically, in the unit 35 </ b> A located on the left side of the block 31, circuit elements are arranged in the element arrangement region 37 </ b> A where the pad 16 </ b> A made of the first wiring layer 16 is exposed. Similarly, in the unit 35B located on the right side of the block 31, circuit elements are arranged on the pads 16A exposed to the element arrangement region 37B. Here, as the circuit elements to be arranged, for example, semiconductor elements 20A and 20B and a chip element 20C are employed.

  Referring to FIG. 3B, in this step, semiconductor element 20A is arranged face up, and semiconductor element 20B is flip-chip mounted face down. The bottom surface of the semiconductor element 20 </ b> A is fixed to the upper surface of the substrate 30 using an insulating adhesive or the like, and the electrode on the upper surface is connected to the pad 16 </ b> A formed of the first wiring layer 16 using the thin metal wire 24. On the other hand, the semiconductor element 20B is disposed with the surface on which the electrode is formed facing downward, and is connected to the pad 16A via a bump electrode made of a conductive bonding material such as solder.

  Here, in the semiconductor element 20A, for example, an electric circuit having a high function for performing video signal processing is formed on the surface, and about 200 electrodes are formed on the surface. The number of pads 16A corresponding to the number of electrodes provided on the semiconductor element 20A is formed in the region where the semiconductor element 20A is placed, and both are wire-bonded using the fine metal wires 24. .

  The above-described element mounting process is performed collectively for all the blocks provided on the substrate 30. Further, in the above description, the circuit element is mounted only on the upper surface of the substrate 30, but the circuit element may be mounted on both the upper surface and the lower surface of the substrate 30. However, in consideration of performing transfer molding using a mold in a later step, it is necessary to bring the lower surface of the substrate 30 into contact with the lower mold. Therefore, when an element is mounted on the lower surface of the substrate 30, it is difficult to bring the lower surface of the substrate 30 into contact with the flat surface of the mold. Therefore, the mounting of the circuit element on the lower surface of the substrate 30 is a molding process which is the next step. It is better to go after the end.

  Next, referring to FIG. 4 and FIG. 5, resin sealing is performed for each block provided on the substrate 30 using a mold. 4 is a cross-sectional view showing this process, FIG. 5 (A) is a plan view of the substrate 30 in a state after this process, and FIG. 5 (B) is a plan view showing one block 31. FIG. 5C is a cross-sectional view of the block 31.

  Referring to FIG. 4, in this step, transfer molding or injection molding using a mold 40 including a lower mold 42 and an upper mold 41 is performed. Specifically, first, the substrate 30 is placed on the upper surface of the lower mold 42, the upper mold 41 and the lower mold 42 are brought into contact with each other, and the circuit element such as the semiconductor element 20A is replaced with the mold 40. In a cavity 43 provided in

  As shown in FIG. 4, the block 31 includes two units 35 </ b> A and 35 </ b> B, and the element arrangement regions 37 </ b> A and 37 </ b> B are housed inside the cavity 43. Further, the upper surfaces of the external connection regions 36A and 36B included in the units 35A and 35B are in contact with the lower surface of the upper mold 41 and are not positioned inside the cavity 43.

  Next, sealing resin is injected into the cavity 43 from a gate (not shown), and the sealing resin is filled into the cavity 43 to seal the circuit elements located inside the block 31 and the upper surface of the substrate 30. Cover with a stop resin. In this step, the two units 35A and 35B included in one block 31 are integrally molded in common. Furthermore, the element arrangement areas 37A and 37B of the two units 35A and 35B are covered with the sealing resin, but the external connection areas 36A and 36B of these units are not covered with the sealing resin and can be inserted and mounted. It ’s like that.

  5A, each of the plurality of blocks 31 included in the substrate 30 is covered with the sealing resin 14 by the method described above. Also in this step, each block 31 is supplied as a plate-like body integrally connected by the support portion 34.

  Referring to FIG. 5B, in one block 31, element arrangement regions 37A, 37B of units 35A, 35B are integrally molded integrally with one sealing resin 14. As a result, resin sealing of two units can be performed in one cavity, and there is an advantage that productivity is improved. Furthermore, the external connection regions 36A and 36B of the units 35A and 35B arranged in the region outside the block 31 are not covered with the sealing resin 14 because they are located outside the cavity as described above.

  FIG. 5C is a vertical cross-sectional view of the block 31 shown in FIG. With reference to this figure, as described above, at the boundary between the block 31 and the support portion 34, the coating resin 22 covering the upper surface of the base material 15 is removed to form a removal region 39. This removal region From 39, the upper surface of the base material 15 is exposed. In the removal region 39, the sealing resin 14 is in direct contact with the exposed upper surface of the base material 15. Here, when the multilayer first wiring layer 16 is formed on the upper surface of the base material 15 via the interlayer insulating film, the uppermost interlayer insulating film is exposed from the coating resin 22 and is covered with the sealing resin 14. The Furthermore, the above-described removal region 39 is also provided between the unit 35A and the unit 35B included in the block 31. That is, the removal region 39 is provided along a region scheduled to be divided by dicing of the substrate 30.

  After the molding process is completed, the substrate 30 is taken out from the mold, and a circuit element is mounted on the pad 17A formed of the second wiring layer 17 by a reflow process using a conductive adhesive such as a brazing material. That is, the package 12A and the chip element 12B shown in FIG. 1C are electrically connected to the second wiring layer 17. This surface mounting process is also performed collectively for all the blocks 31 included in the substrate 30. Further, this surface mounting step may be performed after the next step of dividing the substrate 30 is completed.

  Referring to FIG. 6, next, division by dicing is performed to separate each unit. FIG. 6A is a plan view showing this step, and FIG. 6B is a cross-sectional view showing this step. Here, the substrate 30 and the sealing resin 14 are collectively separated by dicing along the separation lines 44A, 44B, and 44C.

  Referring to FIG. 6A, the separation lines 44A and 44B are defined between the block 31 and the support portions 34 at both ends thereof, and the circuit board is formed by dicing along these separation lines. The support part 34 and the block 31 which are located at the upper and lower ends of 30 can be separated. The separation line 44C is defined between the unit 35A and the unit 35B located inside the block 31, and is included in the block 31 by dicing the substrate 30 and the sealing resin 14 along the separation line 44C. The unit 35A and the unit 35B are separated.

  Referring to FIG. 6B, the separation lines 44A and 44B, which are parts where dicing is performed, are located inside the removal regions 38 and 39, respectively. The removal region 38 is a region where the conductive foil is removed, and the separation lines 44A and 44B are located within the region so that only the resin material such as the base material 15 and the sealing resin 14 is present. Dicing is performed by a dicer. That is, the conductive material such as the conductive foil is not separated by the dicer. This suppresses the wear of the dicer used during dicing and the generation of burrs. Further, such a configuration also has an effect of preventing the wiring layer constituting the circuit device from being exposed to the outside from the side surface of the circuit device.

  Further, the removal region 39 is a region where the coating resin 22 covering the first wiring layer 16 formed on the upper surface of the base material 15 is removed, and the separation lines 44A and 44B are positioned inside this region. , Moisture resistance is improved. That is, when the sealing resin 14 is formed without providing the removal region 39, the boundary between the sealing resin 14 and the coating resin 22 is exposed to the outside from the side surface of the circuit device separated by dicing in this step. When there are many boundaries between different materials exposed to the outside, the moisture resistance and pressure resistance deteriorate. Therefore, in this embodiment, separation lines 44A and 44B are provided in the removal region 39 where the coating resin 22 is removed, and dicing is performed at this position. Thus, the boundary between the coating resin 22 and the sealing resin 14 is located inside the circuit device and is not exposed to the outside. As a result, the number of interfaces of dissimilar materials exposed from the side surface of the circuit device is reduced, and the moisture resistance and pressure resistance are improved.

  The circuit device 10 having the configuration shown in FIG. 1 is configured through the above steps.

It is a figure which shows the structure of the circuit apparatus of this invention, (A) and (B) are top views, (C) is sectional drawing, (D) is a perspective view. It is a figure which shows the manufacturing method of the circuit apparatus of this invention, (A) and (B) are top views, (C) is sectional drawing. It is a figure which shows the manufacturing method of the circuit apparatus of this invention, (A) is a top view, (B) is sectional drawing. It is sectional drawing which shows the manufacturing method of the circuit apparatus of this invention. It is a figure which shows the manufacturing method of the circuit apparatus of this invention, (A) and (B) are top views, (C) is sectional drawing. It is a figure which shows the manufacturing method of the circuit apparatus of this invention, (A) is a top view, (B) is sectional drawing. It is sectional drawing which shows the conventional circuit apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Circuit apparatus 11 Wiring board 12A Package 12B Chip element 13 External connection electrode 14 Sealing resin 15 Base material 16 1st wiring layer 17 2nd wiring layer 18 Semiconductor element 19 Plating film 20A, 20B Semiconductor element 20C Chip element 21 Covering resin 22 Coating resin 23 Through-connection portion 24 Metal thin wire 25 Lead 26 Cut portion 27 Slit 30 Substrate 31 Block 32 Slit 33 Guide hole 34 Support portion 35A, 35B Unit 36A, 36B External connection region 37A, 37B Element placement region 38, 39 Removal region 40 Mold 41 Upper mold 42 Lower mold 43 Cavity 44A, 44B, 44C Separation line 45, 46 Conductive foil

Claims (9)

It has a first side and a second side opposite to each other, and a third side and a fourth side opposite to each other, and is provided from the third side to the fourth side along the first side. A wiring board having an external connection region, and an element placement region surrounded by the external connection region, the second side, the third side, and the fourth side;
A plurality of external connection electrodes provided on the first main surface of the wiring board along the first side in the external connection region;
A first circuit element electrically connected to a first wiring layer provided on the first main surface of the wiring board and disposed in the element disposition region;
A sealing resin for sealing the element arrangement region and the first circuit element;
It said second side edge, the side surface and the side surface of the sealing resin of the wiring substrate corresponding to the third side edge and said fourth side edges of the periphery of the element mounting region, Ri Do from the side which is separated by dicing , the side surface of the sealing resin which is located between the external connection region and the element arrangement region, the circuit and wherein the contact surfaces der Rukoto mold for sealing the sealing resin. A coating resin is formed so that the first wiring layer is covered except for an electrical connection region of the first wiring layer,
The circuit device according to claim 1, wherein a peripheral portion of the wiring substrate is not covered with the coating resin, and a peripheral portion of the wiring substrate is in direct contact with the sealing resin.   The circuit device according to claim 2, wherein the coating resin is not exposed to the outside from the side surface at the second side, the third side, and the fourth side.   4. The circuit device according to claim 2, wherein a region of 0.5 mm to 2 mm from the terminal portion of the wiring board is not covered with the coating resin and directly contacts the sealing resin. 5. .   The circuit device according to claim 1, wherein a surface of the sealing resin on the first main surface side is flat. 5. The circuit device according to claim 2 , wherein the coating resin is not provided in the external connection region provided with the external connection electrode. 6.   The circuit device according to claim 1, further comprising a slit provided by partially removing the wiring board corresponding to the external connection region from the first side. A second circuit element disposed on a second main surface opposite to the first main surface of the wiring board;
The circuit device according to claim 1, wherein the second circuit element is not covered with a sealing resin. 9. The circuit device according to claim 8, wherein the first circuit element is connected via a thin metal wire, and the second circuit element is connected by a conductive adhesive.

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