JPH02166759A - Lead frame - Google Patents
Lead frameInfo
- Publication number
- JPH02166759A JPH02166759A JP63322347A JP32234788A JPH02166759A JP H02166759 A JPH02166759 A JP H02166759A JP 63322347 A JP63322347 A JP 63322347A JP 32234788 A JP32234788 A JP 32234788A JP H02166759 A JPH02166759 A JP H02166759A
- Authority
- JP
- Japan
- Prior art keywords
- island
- frame
- semiconductor chip
- bonding wires
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 24
- 229920005989 resin Polymers 0.000 claims abstract description 14
- 239000011347 resin Substances 0.000 claims abstract description 14
- 239000003779 heat-resistant material Substances 0.000 claims 1
- 230000002093 peripheral effect Effects 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 3
- 229920006015 heat resistant resin Polymers 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005452 bending Methods 0.000 description 2
- 238000007665 sagging Methods 0.000 description 2
- 229920000742 Cotton Polymers 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
- H01L2224/48996—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/48998—Alignment aids
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に用いられるリードフレームに関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a lead frame used in a semiconductor device.
従来のリードフレームの一例を第４図に示す。 An example of a conventional lead frame is shown in FIG.
同図（ａ）は平面図、同図（ｂ）はそのＣ−Ｃ線に沿う
断面図である。図示のように、リードフレームはフレー
ム部１の中心部に方形のアイランド２を有し、この周辺
部に内部リード３と外部リード４を配設し、タイバー５
によってこれらリード３．４をフレーム部１に連結して
いる。FIG. 5(a) is a plan view, and FIG. 2(b) is a cross-sectional view taken along line C--C. As shown in the figure, the lead frame has a rectangular island 2 in the center of a frame part 1, and an inner lead 3 and an outer lead 4 are arranged around this island, and tie bars 5
These leads 3.4 are connected to the frame part 1 by means of the following.
そして、このリードフレームで半導体装置を構成する場
合には、第５図に示すように、アイランド２に半導体チ
ップ６を搭載し、半導体チップ６の電罹バンド６ａと内
部リード３とをボンディングワイヤ７で接続する。更に
、半導体チップ６等を樹脂でパッケージした上で、フレ
ーム部１．及びタイバー５等を切断して完成する。When constructing a semiconductor device using this lead frame, as shown in FIG. Connect with. Furthermore, after packaging the semiconductor chip 6 etc. with resin, the frame portion 1. Then, cut the tie bar 5, etc. to complete the process.
〔発明が解決しようとする課題］
上述した従来のリードフレームは、多ビン化が進むにつ
れて内部リード３の微細化が必要とされ、機械的強度及
び精度の面で不具合を生じない１■ｎ囲で内部リード先
端部の幅及び間隔を微細化することが行われている。一
方、半導体チップ６は高性能化、収率向上のために一層
縮小化されてきており、そのため内部リード３と半導体
チップ６とを接続するボンディングワイヤ７の長さは長
くなる（川向にある。[Problems to be Solved by the Invention] In the conventional lead frame described above, as the number of bins increases, it is necessary to make the internal leads 3 smaller, and it is necessary to make the internal leads 3 finer, and it is necessary to make the internal leads 3 smaller in size than 1. In recent years, the width and spacing of the tips of internal leads have been miniaturized. On the other hand, the semiconductor chip 6 has been further downsized to improve performance and yield, and therefore the length of the bonding wire 7 that connects the internal lead 3 and the semiconductor chip 6 has become longer (on the opposite side).
これらの結果、第５図に示すように、従来のリードフレ
ームではボンディングワイヤ７が上下方向或いは左右方
向に撓み易くなり、ボンディングワイヤ７がアイランド
２に接触し、或いは隣接す名ボンディングワイヤ７に接
触する等して電気的な短絡が生じ、半導体装置の信頼性
が低下される等の問題がある。As a result, as shown in FIG. 5, in the conventional lead frame, the bonding wire 7 tends to bend vertically or horizontally, causing the bonding wire 7 to come into contact with the island 2 or with the adjacent side bonding wire 7. This causes problems such as an electrical short circuit occurring and the reliability of the semiconductor device being reduced.
本発明はこのようなボンディングワイヤにおける短絡を
防止したリードフレームを提供することを目的とする。An object of the present invention is to provide a lead frame that prevents such short circuits in bonding wires.
（課題を解決するための手段〕
本発明のリードフレームは、半導体チップを搭載するア
イランドの周辺部に、耐熱性樹脂からなる枠を表面上に
突出するように形成している。(Means for Solving the Problems) In the lead frame of the present invention, a frame made of heat-resistant resin is formed in a peripheral portion of an island on which a semiconductor chip is mounted so as to protrude above the surface.
上述した構成では、半導体チップとリードとを接続する
ボンディングワイヤの中間部を樹脂枠で支持することが
でき、ボンディングワイヤの撓みを防止してアイランド
、半導体子ツブ端縁、隣接ボンディングワイヤ等に該ボ
ンディングワイヤが接触することを防止する。In the above configuration, the intermediate portion of the bonding wire that connects the semiconductor chip and the lead can be supported by the resin frame, preventing the bonding wire from bending and preventing it from being applied to the island, the edge of the semiconductor chip, the adjacent bonding wire, etc. Prevent bonding wires from coming into contact.
次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）及び（ｂ）は本発明の第１実施例の平面図
及びそのＡ−Ａ線に沿う縦断面図である。FIGS. 1(a) and 1(b) are a plan view of a first embodiment of the present invention and a longitudinal cross-sectional view taken along the line A-A.
図において、１はフレーム部、２はアイランド、３は内
部リード、４は外部リード、５はタイバーである。ここ
で、前記アイランド２には表面の周辺部に、上方に向け
て突出させた耐熱性樹脂にょる枠８を設けている。この
樹脂枠４はアイランドに半導体チップを固着する工程以
降に加わる熱に対し、充分な耐熱性を有する樹脂により
形成している。In the figure, 1 is a frame portion, 2 is an island, 3 is an internal lead, 4 is an external lead, and 5 is a tie bar. Here, the island 2 is provided with a frame 8 made of heat-resistant resin and projecting upward at the peripheral portion of the surface thereof. This resin frame 4 is made of a resin having sufficient heat resistance against the heat applied after the process of fixing the semiconductor chip to the island.
したがって、このリードフレームに対し、第２図に示す
ように、アイランド２に半導体チップ６を固着し、その
電極パッド６ａと内部リード３とをボンディングワイヤ
７で接続したときには、ボンディングワイヤ７の中間部
は樹脂枠８によって支持されるため、ボンディングワイ
ヤ７の垂れを防ぐことができ、アイランドとの短絡を防
ぐことができる。また、樹脂枠８の支持によってボンデ
ィングワイヤ７を左右方向にも安定させることができ、
隣接するボンディングワイヤとの接触をも防止すること
が可能となる。Therefore, when the semiconductor chip 6 is fixed to the island 2 and the electrode pads 6a and the internal leads 3 are connected with the bonding wires 7, as shown in FIG. Since the bonding wire 7 is supported by the resin frame 8, it is possible to prevent the bonding wire 7 from sagging and to prevent a short circuit with the island. Furthermore, the bonding wire 7 can be stabilized in the left-right direction by supporting the resin frame 8.
It is also possible to prevent contact with adjacent bonding wires.
なお、ここでは樹脂枠８の幅は０．３〜１ ｍｍ、高さ
は半導体チップ６の高さと同程度で０．３〜０．５ｍｌ
１１に設定している。Note that here, the width of the resin frame 8 is 0.3 to 1 mm, and the height is approximately the same as the height of the semiconductor chip 6, which is 0.3 to 0.5 ml.
It is set to 11.
第３図（ａ）及び（ｂ）は本発明の第２実施例の平面図
及びそのＢ−Ｂ線に沿う縦断面図である。FIGS. 3(a) and 3(b) are a plan view of a second embodiment of the present invention and a vertical cross-sectional view thereof taken along line B-B.
この実施例では、アイランド２０周辺部に耐熱性樹脂に
よる枠を、内側枠８ａと外側枠８ｂとで二重に構成して
いる。この場合、内側枠８ａの高さは外側枠８ｂの高さ
よりも多少高くし、かつ内側枠８ａは固着する半導体チ
ップ６に可及的に近接して配置している。In this embodiment, a double frame made of heat-resistant resin is constructed around the island 20, consisting of an inner frame 8a and an outer frame 8b. In this case, the height of the inner frame 8a is made somewhat higher than the height of the outer frame 8b, and the inner frame 8a is arranged as close as possible to the semiconductor chip 6 to which it is fixed.
したがって、この構成では樹脂枠８ａ、８ｂが二重に設
けられているため、ボンディングワイヤ７の垂れによる
アイランド２との短絡を一層有効に防止できる。特に、
アイランド２に対して小さい寸法の半導体チップを搭載
する際には有効である。また、これに加えて内側枠８ａ
により、ボンディングワイヤ７と半導体チップ６の端縁
との短絡も防ぐことができる。Therefore, in this configuration, since the resin frames 8a and 8b are provided in duplicate, it is possible to more effectively prevent a short circuit with the island 2 due to sagging of the bonding wire 7. especially,
This is effective when mounting a small semiconductor chip on the island 2. In addition to this, the inner frame 8a
This also prevents a short circuit between the bonding wire 7 and the edge of the semiconductor chip 6.
以上説明したように本発明は、アイランドの周辺部に耐
熱性樹脂からなる枠を表面上に突出するように形成して
いるので、半導体チップとリードとを接続するボンディ
ングワイヤの中間部を樹脂枠で支持することができ、ボ
ンディングワイヤの撓みを防止してアイランド、半導体
チップ端縁。As explained above, in the present invention, a frame made of heat-resistant resin is formed at the periphery of the island so as to protrude above the surface. It can be supported by the island, preventing the bonding wire from bending, and the edge of the semiconductor chip.
隣接ボンディングワイヤ等に該ボンディングワイヤが接
触することを防止でき、半導体装置の多ピン化を実現す
ることができる効果がある。This has the effect of preventing the bonding wire from coming into contact with adjacent bonding wires, etc., and making it possible to increase the number of pins in the semiconductor device.
第１図は本発明の第１実施例を示し、同図（ａ）は平面
図、同図（ｂ）はそのＡ−Ａ線に沿う縦断面図、第２図
は第１図のリードフレームに半導体チップを搭載した状
態を示す縦断面図、第３図は本発明の第２実施例を示し
、同図（ａ）は平面図、同図（ｂ）はそのＢ−Ｂ綿に沿
う縦断面図、第４図は従来のリードフレームを示し、同
図（ａ）は平面図、同図（ｂ）はそのＣ−Ｃ線に沿う継
断面図、第５図は第４図のリードフレームに半導体チッ
プを搭載した状態を示す継断面図である。
１・・・フレーム部、２・・・アイランド、３・・・内
部リード、４・・・外部リード、５・・・タイバー ６
・・・半導体チップ、６ａ・・・電極パッド、７・・・
ボンディングワイヤ、８・・・樹脂枠、８ａ・・・内側
枠、８ｂ・・・外側枠。
第
図
６ 半堪ストチ１．フ。
第５
図
（ｂ）
（ａ）
（ｂ）
第３1 shows a first embodiment of the present invention, FIG. 1A is a plan view, FIG. 3 shows a second embodiment of the present invention, FIG. 3(a) is a plan view, and FIG. 3(b) is a longitudinal section along the B-B cotton. 4 shows the conventional lead frame, FIG. FIG. 3 is a joint cross-sectional view showing a state in which a semiconductor chip is mounted on the device. 1... Frame part, 2... Island, 3... Internal lead, 4... External lead, 5... Tie bar 6
... Semiconductor chip, 6a... Electrode pad, 7...
Bonding wire, 8...Resin frame, 8a...Inner frame, 8b...Outer frame. Figure 6: Half-baked 1. centre. Figure 5 (b) (a) (b) 3rd
Claims (1)
ンドの周囲に配設して半導体チップとの間にボンディン
グワイヤが接続される多数本のリードとを備えるリード
フレームにおいて、前記アイランドの周辺部に耐熱性樹
脂からなる枠を表面上に突出するように形成したことを
特徴とするリードフレーム。1. In a lead frame comprising an island on which a semiconductor chip is mounted and a large number of leads disposed around the island to which bonding wires are connected between the semiconductor chip and the island, a heat-resistant material is provided around the island. A lead frame characterized by a resin frame formed to protrude above the surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63322347A JPH02166759A (en) | 1988-12-21 | 1988-12-21 | Lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63322347A JPH02166759A (en) | 1988-12-21 | 1988-12-21 | Lead frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02166759A true JPH02166759A (en) | 1990-06-27 |
Family
ID=18142628
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63322347A Pending JPH02166759A (en) | 1988-12-21 | 1988-12-21 | Lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02166759A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100445071B1 (en) * | 2001-03-05 | 2004-08-21 | 삼성전자주식회사 | Ultra-thin semiconductor package device having different thickness of die pad and leads, and method for manufacturing the same |
-
1988
- 1988-12-21 JP JP63322347A patent/JPH02166759A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100445071B1 (en) * | 2001-03-05 | 2004-08-21 | 삼성전자주식회사 | Ultra-thin semiconductor package device having different thickness of die pad and leads, and method for manufacturing the same |
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