JPS60101938A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS60101938A
JPS60101938A JP58208637A JP20863783A JPS60101938A JP S60101938 A JPS60101938 A JP S60101938A JP 58208637 A JP58208637 A JP 58208637A JP 20863783 A JP20863783 A JP 20863783A JP S60101938 A JPS60101938 A JP S60101938A
Authority
JP
Japan
Prior art keywords
pads
case
bonding
wire
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58208637A
Other languages
Japanese (ja)
Inventor
Tsutomu Yamashita
力 山下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58208637A priority Critical patent/JPS60101938A/en
Publication of JPS60101938A publication Critical patent/JPS60101938A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/06179—Corner adaptations, i.e. disposition of the bonding areas at the corners of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

PURPOSE:To eliminate wire short-circuit by providing a case for carrying a semiconductor element with a plurality of pads to be connected to inner leads while providing a rectangular pad having a larger area than the ordinary pads at the corner of the case and by selecting a position in this rectangular pad as required. CONSTITUTION:When a plurality of ordinary pads 22 and 23 are formed respectively on two sides adjacent to each other of a ceramic case 11, a rectangular pad 6 having a larger area than these pads is positioned between the pads 22 and 23 at the corner of the case 11. On this case 11, secured is a semiconductor element with electrode terminals connected to the pads 22, 23 and 6, which are further connected to inner leads 32 respectively by means of wires 43. One of the wires 43 is attached to a position on the rectangular pad 6 selected for preventing the entanglement of these wires.

Description

【発明の詳細な説明】 この発明は半導体装置に係り、特にワイヤーボンディン
グに好適するように半導体素子のポンディングパッドの
配置を改良した構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a structure in which the arrangement of bonding pads of a semiconductor element is improved so as to be suitable for wire bonding.

半導体装置の特に集積回路装置、大規模集積回路装置に
おいて、その半導体素子（以後素子と略称する）のポン
ディングパッド（以稜パ、ドと略称する）をリードに接
続し導出するのに一般のワイヤーボンディングによって
いるが、集積度の向上に従って、例えは記憶回路素子に
おいて典型的に見られるようにパッドが素子主面の周辺
部の四辺のうち、対向する２辺近傍に集中しかつ素子の
短辺と長辺との比が大きくなる傾向にある。In semiconductor devices, especially integrated circuit devices and large-scale integrated circuit devices, a general method is used to connect and lead out the bonding pads (hereinafter referred to as pads and pads) of semiconductor elements (hereinafter referred to as elements) to leads. However, as the degree of integration increases, the pads are concentrated near two opposing sides of the four peripheral sides of the main surface of the element, as is typically seen in memory circuit elements. The ratio of the side to the long side tends to increase.

このような構造の素子を例えばセラミック・ケースに内
蔵する場合、セラミックケースは、素子の対向する２辺
近傍に集中したパッドに対向するようにセラミックケー
スのインナーリードを配置することは比較的容易である
。しかしサーディツプケースやモールドケースのインナ
ーリードを形成するベースリボンでは前記セラミック・
ケースのインナーリード配置の様に、素子の対向する２
辺近傍に集中したパッドに対向するようにインナーリー
ドを配置することは非常に困難である。そのためにサー
ディツプケースやモールドケースのインナーリードは素
子の四辺周囲をとり囲む配置となる。When an element with such a structure is built into a ceramic case, for example, it is relatively easy to arrange the inner leads of the ceramic case so as to face the pads concentrated near two opposing sides of the element. be. However, in base ribbons that form the inner leads of cerdip cases and molded cases, the ceramic
Like the inner lead arrangement of the case, two opposing elements
It is very difficult to arrange inner leads so as to face pads concentrated near the sides. For this reason, the inner leads of the cerdip case or molded case are arranged to surround the four sides of the element.

そこで第１図に示すようなパッド２０．２１配置の素子
１でもセラミックーケースにワイヤーボンディングする
場合は第２図のようにワイヤー４１で平行にインナーリ
ード３１にボンディングできるからワイヤーショート等
の問題は無くワイヤーボンディングが可能である。Therefore, when wire-bonding the element 1 with the pads 20 and 21 arranged as shown in Fig. 1 to the ceramic case, it can be bonded to the inner lead 31 in parallel with the wire 41 as shown in Fig. 2, so there is no problem such as wire shorting. Wire bonding is possible.

しかし、同一のパッド配置の素子ｌをサーディツプ・ケ
ースやモールド・ケースにワイヤーボンディングする場
合は、第３図のように２辺にわたるインナーリード５１
へのボンディングワイヤー４２がクロスするのでワイヤ
ーショート等が発生し易すく、歩留低下、信頼性の低下
となる欠点が有った。However, when wire-bonding elements l with the same pad arrangement to a cerdip case or a molded case, inner leads 51 extending over two sides as shown in FIG.
Since the bonding wires 42 to the wires cross each other, wire shorts are likely to occur, which has the disadvantage of lowering yield and reliability.

この発明は上記従来の欠点を改良するための半導体装置
の構造を提供するものである。The present invention provides a structure of a semiconductor device to improve the above-mentioned conventional drawbacks.

この発明は素子におけるポンディングパッドの面積が他
のポンディングパッドよりも大きい面積のパッドを素子
角部に配置したことを特徴とする。The present invention is characterized in that a pad having a larger area than other bonding pads in the element is arranged at a corner of the element.

次にこの発明を図面を参照して詳細に説明する。Next, the present invention will be explained in detail with reference to the drawings.

第４図は素子の中心を含み素子の４分のｌｅ示し、通常
のパッド２２．２３に加え、角に（６）私が他のパッド
よりも大きい面積のパッド６を設けている。第５図、第
６図は第４図に示す素子１１をセラミック・ケース、サ
ーディツプケース又はモールドケースに設置し、ワイヤ
ボンディングを施した状態を示している。FIG. 4 shows a quarter of the element including the center of the element, and in addition to the usual pads 22 and 23, a pad 6 (6) with a larger area than the other pads is provided at the corner. 5 and 6 show the device 11 shown in FIG. 4 installed in a ceramic case, a cerdip case, or a molded case, and subjected to wire bonding.

第４図に示すようにパッドを長方形に形成し７、他のパ
ッドより面積を大きく形成しであると、第５図に示すよ
うに、セラミックケースの場合は、パッド６をワイヤ４
３でインナーリード３２にボンディングする際にパッド
６のうち一辺における隣接パッド２２に近い部分にボン
ディング位置決めを行ない、モールドケース又はサーデ
ィツプ・ケースの場合は第６図に示すようにパッド６の
うち他辺における隣接パッド２３に近い部分にボンディ
ングワイヤー４４によるインナーリード５２へのボンデ
ィング位置決めを行なえば、ワイヤーボンディングでの
ワイヤーショート等の不良は発生しなくなる。As shown in FIG. 4, if the pad is formed into a rectangular shape 7 and has a larger area than other pads, as shown in FIG.
When bonding to the inner lead 32 in step 3, the bonding position is determined on one side of the pad 6 near the adjacent pad 22, and in the case of a molded case or a cerdip case, the other side of the pad 6 is positioned as shown in FIG. By positioning the bonding wire 44 to the inner lead 52 at a portion close to the adjacent pad 23, defects such as wire shorts in wire bonding will not occur.

以上の様に半導体素子主面の周辺部に設ける複数のポン
ディングパッドにおいて、ポンディングパッドの面積が
他のボンディングパットよりも大きいものを素子角部に
配置することによシ、ワイヤーボンディング工程でのワ
イヤーショート等の不良は発生しなくなシ、歩留、信頼
性は向上する。As described above, among the plurality of bonding pads provided on the periphery of the main surface of the semiconductor element, by arranging the bonding pad with a larger area than the other bonding pads at the corner of the element, it is possible to improve the wire bonding process. Defects such as wire shorts will no longer occur, and yield and reliability will improve.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は大規模集積回路装置の素子のポンディングパッ
ド部を説明するための上面図（中心を含む素子の４分１
を示す）、第２図、第３図は第１図の素子をセラミック
・ケース及びモールド・ケースにそれぞれ搭載しワイヤ
ーボンディングした状態を示す上面図（中心を含む素子
、ケースの４分の１を示す、以下同じ）、第４図はこの
発明の１実施例の素子のボンディングバット部を説明す
るための上面図、第５図、第６図は第４図の素子をセラ
ミック・ケース及びモールドケースにそれぞれ搭載しワ
イヤーボンディングした状態を示す上面図である。 １・・・・・・半導体素子、２０．２１，２２，２３゜
６・・・・・・ボンディング・バット、３１．３２・・
・・・・セラミック・ケースのインナーリード部、４１
，４２゜４３．４４・・・・・・ボンディング・ワイヤ
ー、５１゜５２・・・・・・モールド・ケースのインナ
ーリード部、９１．９２・・・・・・セラミック・ケー
スのアイランド部、１０１，１０２・・・・・・モール
ド−ケースのアイランド部。 第２　図 ／ 第３凹 簗４図Figure 1 is a top view (one-fourth of the element including the center) for explaining the bonding pad portion of the element of a large-scale integrated circuit device.
), Figures 2 and 3 are top views showing the device shown in Figure 1 mounted in a ceramic case and a molded case, respectively, and wire bonded (the device including the center and a quarter of the case are shown). FIG. 4 is a top view for explaining the bonding butt portion of an element according to one embodiment of the present invention, and FIGS. 5 and 6 show the element of FIG. 4 in a ceramic case and a molded case. FIG. 3 is a top view showing a state in which the devices are mounted and wire bonded to each other. 1... Semiconductor element, 20.21, 22, 23° 6... Bonding butt, 31.32...
...Inner lead part of ceramic case, 41
, 42゜43.44...Bonding wire, 51゜52...Inner lead part of molded case, 91.92...Island part of ceramic case, 101 , 102... Island part of the mold case. Figure 2/ Figure 3 Concave Figure 4

Claims (1)

【特許請求の範囲】[Claims] 半導体素子を内蔵し、この半導体素子主面の周辺部に設
けた複数のポンディングパッドからパッケージのインナ
ーリードにワイヤーボンディングを施した半導体装置に
おいて、ポンディングパッドの面積が他のポンディング
パッドよりも大きいものを素子角部に配置しパッケージ
のインナーリードの位置に対応してワイヤーボンディン
グに行なったことを％徴とする半導体装置。In a semiconductor device with a built-in semiconductor element and wire bonding from multiple bonding pads provided around the main surface of the semiconductor element to the inner leads of the package, the area of the bonding pad is larger than that of other bonding pads. A semiconductor device characterized by wire bonding, with large wires placed at the corners of the element and corresponding to the positions of the inner leads of the package.
JP58208637A 1983-11-07 1983-11-07 Semiconductor device Pending JPS60101938A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58208637A JPS60101938A (en) 1983-11-07 1983-11-07 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58208637A JPS60101938A (en) 1983-11-07 1983-11-07 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS60101938A true JPS60101938A (en) 1985-06-06

Family

ID=16559531

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58208637A Pending JPS60101938A (en) 1983-11-07 1983-11-07 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS60101938A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63162534U (en) * 1987-04-10 1988-10-24
US5925935A (en) * 1996-10-01 1999-07-20 Samsung Electronics Co., Ltd. Semiconductor chip with shaped bonding pads
WO2008150055A1 (en) * 2007-06-07 2008-12-11 Silicon Works Co., Ltd Pad layout structure of semiconductor chip

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63162534U (en) * 1987-04-10 1988-10-24
US5925935A (en) * 1996-10-01 1999-07-20 Samsung Electronics Co., Ltd. Semiconductor chip with shaped bonding pads
WO2008150055A1 (en) * 2007-06-07 2008-12-11 Silicon Works Co., Ltd Pad layout structure of semiconductor chip
US8258631B2 (en) 2007-06-07 2012-09-04 Silicon Works Co., Ltd. Pad layout structure of semiconductor chip

Similar Documents

Publication Publication Date Title
KR0149798B1 (en) Semiconductor device and method of manufacture and lead frame
JPH0273660A (en) Lead frame for semiconductor device
JPS5992556A (en) Semiconductor device
JPS60101938A (en) Semiconductor device
JPS6211499B2 (en)
JPH06326235A (en) Semiconductor device
JPH07335818A (en) Semiconductor device
JP3179374B2 (en) Lead frame for semiconductor device and semiconductor device
JP2562773Y2 (en) Semiconductor integrated circuit device
JP2587722Y2 (en) Semiconductor device
KR100533750B1 (en) Lead Frame Used for the Fabrication of Semiconductor Package and Semiconductor Package Fabricated Using the Same
JPH077023A (en) Resin sealed semiconductor device
JPH0142346Y2 (en)
JPS59198744A (en) Resin sealed type semiconductor device
JPH0499341A (en) Tab system semiconductor device
JPH02166743A (en) Semiconductor integrated circuit device
JPH01173747A (en) Resin-sealed semiconductor device
JPS6151953A (en) Semiconductor device
JPH04124844A (en) Structure of bonding pad electrode for semiconductor device
JPH0513490A (en) Resin sealed type semiconductor device
JPH05291476A (en) Semiconductor device
JPH05299575A (en) Semiconductor device with built-in memory
JP2000012770A (en) Semiconductor device and manufacture thereof
JPS63269539A (en) Bonding wire for semiconductor integrated circuit
JPH0645503A (en) Lead frame for resin seal type semiconductor device