JPS6151953A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6151953A
JPS6151953A JP59174640A JP17464084A JPS6151953A JP S6151953 A JPS6151953 A JP S6151953A JP 59174640 A JP59174640 A JP 59174640A JP 17464084 A JP17464084 A JP 17464084A JP S6151953 A JPS6151953 A JP S6151953A
Authority
JP
Japan
Prior art keywords
lead
insulator
chip
stitch
fixed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59174640A
Other languages
Japanese (ja)
Inventor
Hisanori Yamashita
尚徳 山下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP59174640A priority Critical patent/JPS6151953A/en
Publication of JPS6151953A publication Critical patent/JPS6151953A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49506—Lead-frames or other flat leads characterised by the die pad an insulative substrate being used as a diepad, e.g. ceramic, plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Ceramic Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain the titled device using a lead frame adaptable to the appliable chip size, by a method wherein an insulator is used as the island and fixed to the back of each lead stitch. CONSTITUTION:A plurality of leads 3 are formed by etching or punching a piece of metallic plate but provided with no islands for elements 1. Instead, the insulator (e.g. film) 6 which enables lead terminals to be fixed at the same time is adhered to the back the stitch of each lead 3. The semiconductor chip 1 is mounted on the insulator 6. This manner unnecessitates the production of various kinds of lead frames at the same time with changes in size of the chip or pellet 1 and also eliminates the variability of lead frames on account of the increase in degree of freedom in chip size selection.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、特に半導体装置のリードフレームのアイラン
ド部に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention particularly relates to an island portion of a lead frame of a semiconductor device.

〔従来の技術〕[Conventional technology]

従来、半導体装置のリードフレームは、リードフレーム
の材料をエツチングまたは金型により所定形状に加工さ
れて形成されておす、通常、第２図に示すように、半導
体素子が搭載されるアイランド部２およびこれらの周辺
から外部に延び素子１の電極とワイヤー４で接続される
複数のリード３とが形成されている。アイランド部２は
タブリード１５で支えられている。Conventionally, a lead frame of a semiconductor device is formed by processing the lead frame material into a predetermined shape by etching or molding.As shown in FIG. A plurality of leads 3 are formed extending from these peripheries to the outside and connected to the electrodes of the element 1 by wires 4. The island portion 2 is supported by a tab lead 15.

また、リード３の数が増えた場合等には、各リードのワ
イヤーポンディング部（ステッチと呼ばれている）を支
えるため、第３図に示すように、各リード３のステッチ
部にフィルム等の絶縁物５を貼りつけた（阿造のものも
あった。In addition, when the number of leads 3 increases, in order to support the wire bonding part (called a stitch) of each lead, as shown in Fig. Insulator 5 was pasted (Azo's was also included).

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、このような形状のリードフレームでは、
半導体チップ１の大きさが異なるたびに１アイランド部
１の大きさが異なるリードフレームを形成しなければな
らなかった。However, with this type of lead frame,
Each time the semiconductor chip 1 has a different size, it is necessary to form a lead frame with a different size of one island portion 1.

本発明の目的は、チップサイズが異なった場合でも対処
し得る半導体装置を提供することにある。An object of the present invention is to provide a semiconductor device that can be used even when the chip sizes are different.

〔問題点を解決するだめの手段〕[Failure to solve the problem]

本発明は、絶縁体（例えばフィルム）をアイシンドとし
て用い、この絶縁体を各リードステッチ部の裏側に固定
したことを特徴とする。The present invention is characterized in that an insulator (for example, a film) is used as the insulation, and this insulator is fixed to the back side of each lead stitch portion.

〔実施例〕〔Example〕

第１図に本発明の一実施例を示す。即ち、一枚の金属板
にエツチングや打抜きを施すことによって複数のり−ド
３を形成しているが、累子１のためのアイランドは設け
ていない。その代わり、各リード３のステッチ部の裏側
に、リード端子の固定を同時に可能に１７た絶縁体（例
えばフィルム）６をはり付けている。半導体チップ１は
絶縁体６上に搭載されている。FIG. 1 shows an embodiment of the present invention. That is, a plurality of leads 3 are formed by etching or punching a single metal plate, but no islands for the resistors 1 are provided. Instead, an insulator (for example, a film) 6 is pasted to the back side of the stitched portion of each lead 3 so that the lead terminals can be fixed at the same time. A semiconductor chip 1 is mounted on an insulator 6.

したがって、チップ１の大きさがかわっても、それに伴
なって各種のリードフレームをつくる必要がなく、チッ
プサイズの選択の自由度が増してリードフレームのバラ
つきもなくなるという利点がある。また、各リード３の
ステッチ表面と絶縁体６の表面との間Ｋ　ＩＪ−ドの厚
さの分だけ段差があう、したがって、従来行なわれてい
たワイヤー短絡防止のだめのアイランド部のディンプル
加工が必要なくなるという利点がある。なお、チップ１
はリード３のステッチおよび絶縁体６を含めて樹脂で封
止される 〔発明の効果〕 このように、本発明によれば、適用できるチップサイズ
に・独１亀性のあるリードフレームを用１ハだ半導体装
置を得ることができる。Therefore, even if the size of the chip 1 changes, there is no need to create various lead frames accordingly, and there is an advantage that the degree of freedom in selecting the chip size is increased and variations in lead frames are eliminated. In addition, there is a step between the stitch surface of each lead 3 and the surface of the insulator 6 by the thickness of the K IJ-de, so it is necessary to dimple the island part to prevent wire short circuits, which was conventionally done. The advantage is that it disappears. In addition, chip 1
The lead frame including the stitches of the leads 3 and the insulator 6 is sealed with resin. [Effects of the Invention] As described above, according to the present invention, a unique lead frame is used for the applicable chip size. A bare semiconductor device can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図ｆａ）　、　（ｂ）は夫々本発明の一実施例を示
す平面図および断面図、第２図は従来例の平面図、第３
図（ａ）　、　（ｂ）は夫々他の従来例の平面図、断面
図である。 １・・・・・・ペレット、２・・・・・・アイランド部
、３・・・・・・リード、４・・・・・・ボンディング
ワイヤー、５・・・・・・フィルム等の絶縁体、６・・
・・・・絶縁体（列えはフィルム）。Figures 1 fa) and 3 (b) are a plan view and a cross-sectional view showing one embodiment of the present invention, respectively, Figure 2 is a plan view of a conventional example, and Figure 3 is a plan view showing an embodiment of the present invention.
Figures (a) and (b) are a plan view and a sectional view of other conventional examples, respectively. 1...Pellet, 2...Island part, 3...Lead, 4...Bonding wire, 5...Insulator such as film , 6...
...Insulator (lined with film).

Claims (1)

【特許請求の範囲】[Claims] 　絶縁体層と、この絶縁体層上に固着された半導体素子
と、この半導体素子の周辺において前記絶縁体層上に夫
々の一部が固定された複数のリードと、各リードの前記
絶縁体層との固定部分と前記半導体素子の電極とを接続
する導電路とを有することを特徴とする半導体装置。an insulating layer, a semiconductor element fixed on the insulating layer, a plurality of leads each partially fixed on the insulating layer around the semiconductor element, and the insulating layer of each lead. A semiconductor device comprising a conductive path connecting a fixed portion of the semiconductor element to an electrode of the semiconductor element.
JP59174640A 1984-08-22 1984-08-22 Semiconductor device Pending JPS6151953A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59174640A JPS6151953A (en) 1984-08-22 1984-08-22 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59174640A JPS6151953A (en) 1984-08-22 1984-08-22 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6151953A true JPS6151953A (en) 1986-03-14

Family

ID=15982124

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59174640A Pending JPS6151953A (en) 1984-08-22 1984-08-22 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6151953A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01120356U (en) * 1988-02-05 1989-08-15
JPH01257360A (en) * 1988-04-06 1989-10-13 Nec Corp Lead frame for semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01120356U (en) * 1988-02-05 1989-08-15
JPH01257360A (en) * 1988-04-06 1989-10-13 Nec Corp Lead frame for semiconductor device

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