JP2681959B2 - Method for manufacturing semiconductor integrated circuit - Google Patents

Method for manufacturing semiconductor integrated circuit

Info

Publication number
JP2681959B2
JP2681959B2 JP63011326A JP1132688A JP2681959B2 JP 2681959 B2 JP2681959 B2 JP 2681959B2 JP 63011326 A JP63011326 A JP 63011326A JP 1132688 A JP1132688 A JP 1132688A JP 2681959 B2 JP2681959 B2 JP 2681959B2
Authority
JP
Japan
Prior art keywords
integrated circuit
circuits
semiconductor integrated
chip
groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP63011326A
Other languages
Japanese (ja)
Other versions
JPH01185930A (en
Inventor
民夫 友杉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63011326A priority Critical patent/JP2681959B2/en
Publication of JPH01185930A publication Critical patent/JPH01185930A/en
Application granted granted Critical
Publication of JP2681959B2 publication Critical patent/JP2681959B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/4813Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は漏話対策を施した半導体集積回路の製造方法
に関する。
TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor integrated circuit with crosstalk countermeasures.

〔従来の技術〕[Conventional technology]

従来、1つの半導体基板上に形成した半導体集積回路
の回路間分離はPN接合に逆バイアスをかける方法、及び
シリコン酸化膜等による分離の方法がとられてきた。例
えば、第4図(a)及び(b)はその一例の平面図及び
断面図であり、1つの半導体サブストレート1の主面に
夫々異なる回路2と回路3を形成し、両回路間に厚い酸
化膜7を形成して回路間分離を行っている。そして、こ
の半導体集積回路はパッケージ8の所定位置にマウント
されている。
Conventionally, as a method for separating circuits of a semiconductor integrated circuit formed on one semiconductor substrate, a method of applying a reverse bias to a PN junction and a method of separating with a silicon oxide film or the like have been used. For example, FIGS. 4 (a) and 4 (b) are a plan view and a sectional view of an example thereof, in which different circuits 2 and 3 are formed on the main surface of one semiconductor substrate 1, respectively, and a thick circuit is formed between the two circuits. The oxide film 7 is formed to separate the circuits. The semiconductor integrated circuit is mounted on the package 8 at a predetermined position.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

上述した従来の半導体集積回路においては、取り扱う
周波数が数百MHzまでの場合には、上述した酸化膜分離
等の手段による回路間分離で特に問題は生じていない。
しかし、近年半導体集積回路の動作周波数として数GHz
また数十GHzが要求されるに至り、半導体集積回路チッ
プ内の回路間の漏話が問題となってきた。即ち、上述し
たPN接合分離や酸化膜分離は回路表面での分離方法であ
り、その下のサブストレート(基板)は共通となってい
る。このため、動作集積回路がGHz領域となったり、半
導体集積回路の利得が大きいと、動作振幅の大きい回路
からサブストレートを通って増幅器入力に回り込む信号
量が無視できなくなってくる。これは、信号波形の乱れ
となり、顕著な場合には発振に至る。
In the above-mentioned conventional semiconductor integrated circuit, when the frequency to be handled is up to several hundred MHz, no particular problem occurs in the circuit separation by means such as the oxide film separation described above.
However, in recent years, the operating frequency of semiconductor integrated circuits is several GHz.
Further, with the demand for several tens of GHz, crosstalk between circuits in a semiconductor integrated circuit chip has become a problem. That is, the above-mentioned PN junction separation and oxide film separation are separation methods on the circuit surface, and the underlying substrate (substrate) is common. For this reason, if the operating integrated circuit is in the GHz range or if the gain of the semiconductor integrated circuit is large, the amount of signal that wraps around the amplifier input through the substrate from the circuit with large operating amplitude cannot be ignored. This causes a disturbance in the signal waveform, and if it is remarkable, it causes oscillation.

この問題を解決する1つの手段としては、半導体集積
回路1つ当たりの増幅器利得を下げればよい。また、利
得が大きい半導体集積回路は2つ以上に分割して独立半
導体集積回路とし、同一パッケージにマウント後ボンデ
ィングワイヤで結ぶ等の手段が採用できる。
As one means for solving this problem, the amplifier gain per semiconductor integrated circuit may be lowered. Further, a semiconductor integrated circuit having a large gain may be divided into two or more pieces to form an independent semiconductor integrated circuit, which is mounted on the same package and then connected by a bonding wire.

しかし、半導体集積回路を2つ以上の独立した回路に
するのでは、実装に不利であり、また同一パッケージに
2チップ以上をマウントするのは信頼性,量産性に問題
がある。即ち、2チップ目をマウントする際に既マウン
トチップのろう材が溶けることがある。また、マウント
時間が1チップの2倍かかる。
However, if the semiconductor integrated circuit is composed of two or more independent circuits, it is disadvantageous for mounting, and mounting two or more chips in the same package has problems in reliability and mass productivity. That is, when mounting the second chip, the brazing material of the already mounted chip may melt. Also, the mounting time is twice as long as one chip.

本発明は、半導体集積回路における漏話を減少すると
ともに、半導体集積回路の信頼性,量産性を向上できる
半導体集積回路の製造方法を提供することを目的として
いる。
An object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit, which can reduce the crosstalk in the semiconductor integrated circuit and improve the reliability and mass productivity of the semiconductor integrated circuit.

〔課題を解決するための手段〕[Means for solving the problem]

本発明の半導体集積回路の製造方法は、同一半導体基
板の表面に複数の回路を形成したチップをその裏面にお
いてパッケージにマウントする工程と、このマウントさ
れた状態で前記回路間の前記半導体基板の表面に所要深
さの溝をレーザ光線の照射により形成して両回路を分離
する工程と、両回路を電気接続する配線を形成する工程
とを含んでいる。
A method of manufacturing a semiconductor integrated circuit according to the present invention includes a step of mounting a chip having a plurality of circuits formed on the front surface of the same semiconductor substrate on a package on the back surface thereof, and a surface of the semiconductor substrate between the circuits in the mounted state. The method includes a step of forming a groove having a required depth by irradiating a laser beam to separate both circuits, and a step of forming a wiring for electrically connecting both circuits.

〔作用〕[Action]

この製造方法では、溝の形成により回路間の漏話を減
少し、かつ1回の工程でチップをパッケージにマウント
することを可能とする。
In this manufacturing method, the crosstalk between circuits is reduced by forming the groove, and the chip can be mounted on the package in one step.

〔実施例〕〔Example〕

次に、本発明を図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.

第1図は本発明の第1実施例を説明するための図であ
り、同図(a)は平面図、同図(b)はそのA−A線断
面図である。
FIG. 1 is a diagram for explaining a first embodiment of the present invention, FIG. 1 (a) is a plan view, and FIG. 1 (b) is a sectional view taken along the line AA.

本実施例では、先ず1つの半導体サブストレート1の
主面に異なる回路2,3を夫々形成した半導体集積回路チ
ップをろう材を用いてパッケージ8にマウントする。
In this embodiment, first, a semiconductor integrated circuit chip having different circuits 2 and 3 formed on the main surface of one semiconductor substrate 1 is mounted on a package 8 using a brazing material.

しかる上で、前記半導体集積回路に対してレーザ光線
を選択的に照射し、回路2,3間に少なくとも深さ5μm
以上の溝4を形成し、この溝4で両回路2,3を分離させ
る。この溝4の深さは少なくとも半導体サブストレート
1の主面に形成したエピタキシャル層等よりも深く形成
することが好ましい。
Then, the semiconductor integrated circuit is selectively irradiated with a laser beam so that the depth between the circuits 2 and 3 is at least 5 μm.
The groove 4 described above is formed, and the two circuits 2 and 3 are separated by this groove 4. It is preferable to form the groove 4 at least deeper than the epitaxial layer or the like formed on the main surface of the semiconductor substrate 1.

しかる上で、ボンディングワイヤ5で回路2と回路3
を電気的に接続する。
Then, the bonding wire 5 is used for the circuit 2 and the circuit 3.
Are electrically connected.

本実施例により完成された半導体集積回路では、回路
2と回路3との間に形成された溝4によってサブストレ
ート1から回り込む漏話を減少させ、両回路間での漏話
減衰量を大きくしている。一方、半導体集積回路チップ
は1回のマウント工程で済み、信頼性,量産性を向上で
きる。
In the semiconductor integrated circuit completed in this embodiment, the groove 4 formed between the circuit 2 and the circuit 3 reduces the crosstalk from the substrate 1 and increases the amount of crosstalk attenuation between the two circuits. . On the other hand, the semiconductor integrated circuit chip requires only one mounting step, and reliability and mass productivity can be improved.

第2図は本発明の第2実施例を説明する図であり、同
図(a)は平面図、同図(b),(c)は夫々同図
(a)のB−B線,C−C線に沿う断面図である。なお、
第1図と同一部分には同一符号を付してある。
FIG. 2 is a diagram for explaining the second embodiment of the present invention. FIG. 2A is a plan view, and FIGS. 2B and 2C are BB line and C in FIG. It is sectional drawing which follows the C line. In addition,
The same parts as those in FIG. 1 are denoted by the same reference numerals.

この実施例では、回路2,3を形成してある半導体集積
回路チップのサブストレート1をパッケージ8にマウン
トした後、レーザ光線により回路2,回路3間に深さ5μ
m以上の溝4Aを形成して両者を分離する。このとき、溝
4Aを形成する箇所の一部を配線6として溝を形成せずに
残し、この配線6により回路2と3を電気接続してい
る。このため、ボンディングワイヤは不必要である。
In this embodiment, after mounting the substrate 1 of the semiconductor integrated circuit chip on which the circuits 2 and 3 are formed in the package 8, the depth between the circuits 2 and 3 is 5 μm by the laser beam.
A groove 4A of m or more is formed to separate the two. At this time, the groove
A part of the portion where 4A is formed is left as a wiring 6 without forming a groove, and the wiring 6 electrically connects the circuits 2 and 3. Therefore, the bonding wire is unnecessary.

この実施例においても、配線6の幅寸法を極力細く形
成すれば漏話特性も第1実施例と比べて大差ない程度に
低減できる。
Also in this embodiment, if the width dimension of the wiring 6 is made as thin as possible, the crosstalk characteristics can be reduced to the same extent as in the first embodiment.

第3図は本発明の第3の実施例を示す図であり、同図
(a)は平面図、同図(b)はそのD−D線に沿う断面
図である。
FIG. 3 is a diagram showing a third embodiment of the present invention, FIG. 3 (a) is a plan view, and FIG. 3 (b) is a sectional view taken along the line D-D.

この実施例では、パッケージ8に半導体集積回路チッ
プをマウントした後に、レーザ光線を利用して回路2,3
間に形成する溝4Bをチップ厚まで堀り、チップを回路2,
3で完全に2分割している。その後、ボンディングワイ
ヤ5により回路2,3を接続することは、第1図の例と同
じである。
In this embodiment, after mounting the semiconductor integrated circuit chip on the package 8, the circuit 2, 3 is utilized by using the laser beam.
Groove the groove 4B to be formed between the chips to the thickness of the chip,
It is completely divided into two at 3. After that, connecting the circuits 2 and 3 by the bonding wire 5 is the same as in the example of FIG.

この実施例では、2分割することにより回路2と回路
3で共通のサブストレート1が独立となり、回路2,3間
の漏話は略零に近くなる。またこの場合、独立した2チ
ップをマウントするのに比べて信頼性の高いマウントを
行うことができ、かつマウント工程が増大されることも
ない。
In this embodiment, by dividing into two, the substrate 1 common to the circuits 2 and 3 becomes independent, and the crosstalk between the circuits 2 and 3 becomes almost zero. Further, in this case, mounting can be performed with higher reliability than mounting two independent chips, and the mounting process is not increased.

また、前記第1乃至第3の実施例においては、いずれ
もレーザ光線で溝を形成する際にシリコン等の塵が回路
表面に付着し、回路ショート等の問題が起こる可能性が
あるので、半導体集積回路チップの保護膜を強化するこ
とが肝要である。
Further, in each of the first to third embodiments, when a groove is formed by a laser beam, dust such as silicon may adhere to the circuit surface, causing a problem such as a circuit short circuit. It is important to strengthen the protective film of the integrated circuit chip.

〔発明の効果〕〔The invention's effect〕

以上説明したように本発明は、チップに形成された回
路の間に所要深さの溝を形成して両回路を分離する工程
を含んでいるので、溝の形成により回路間の漏話を減少
して半導体集積回路チップ内の漏話を減少せしめること
が可能となり、数十GHzといった高周波動作においても
入出力の漏話による結合が減少し、安定した高利得を得
ることができる。また、本発明ではチップをパッケージ
上にマウントした状態でレーザ光線によりチップに溝を
形成するため、マウント前にチップに溝を形成して回路
を分離したチップに比べて、マウント時に加えられる外
力によってチップが溝において割れてしまうようなこと
もない。さらに、本発明において溝によってチップを分
割する場合には、予め分離された複数のチップをそれぞ
れマウントする場合に比べて1回のマウント工程で済む
ことになる。これにより半導体集積回路の信頼性の向上
および量産性の向上が可能となり、しかも製造歩留りを
高めることができる効果がある。
As described above, the present invention includes the step of separating the two circuits by forming a groove having a required depth between the circuits formed on the chip, and thus the formation of the groove reduces crosstalk between the circuits. As a result, the crosstalk in the semiconductor integrated circuit chip can be reduced, and the coupling due to the input / output crosstalk can be reduced even in a high frequency operation such as several tens GHz, and a stable high gain can be obtained. Further, in the present invention, since the groove is formed in the chip by the laser beam in the state where the chip is mounted on the package, compared to a chip in which the circuit is separated by forming the groove in the chip before mounting, the external force applied during mounting causes The chip does not break in the groove. Further, in the present invention, when the chip is divided by the groove, one mounting step is required as compared with the case where a plurality of chips separated in advance are mounted. As a result, the reliability and mass productivity of the semiconductor integrated circuit can be improved, and further, the manufacturing yield can be increased.

【図面の簡単な説明】[Brief description of the drawings]

第1図は本発明の第1実施例を示し、同図(a)は平面
図、同図(b)はそのA−A線断面図,第2図は本発明
の第2実施例を示し、同図(a)は平面図、同図(b)
はそのB−B線断面図、同図(c)はC−C線断面図、
第3図は本発明の第3実施例を示し、同図(a)は平面
図、同図(b)はD−D線断面図、第4図は従来例を示
し、同図(a)は平面図、同図(b)はE−E線断面図
である。 1…サブストレート、2,3…回路、4,4A,4B…溝、5…ボ
ンディングワイヤ、6…配線、7…厚い酸化膜、8…パ
ッケージ。
1 shows a first embodiment of the present invention, FIG. 1 (a) is a plan view, FIG. 1 (b) is a sectional view taken along the line AA, and FIG. 2 shows a second embodiment of the present invention. The figure (a) is a plan view and the figure (b) is
Is a sectional view taken along the line BB, and FIG.
FIG. 3 shows a third embodiment of the present invention, FIG. 3 (a) is a plan view, FIG. 3 (b) is a sectional view taken along the line D-D, and FIG. Is a plan view, and FIG. 6B is a sectional view taken along the line EE. 1 ... Substrate, 2, 3 ... Circuit, 4, 4A, 4B ... Groove, 5 ... Bonding wire, 6 ... Wiring, 7 ... Thick oxide film, 8 ... Package.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】同一半導体基板の表面に複数の回路を形成
したチップをその裏面においてパッケージにマウントす
る工程と、このマウントされた状態で前記回路間の前記
半導体基板の表面に所要深さの溝をレーザ光線の照射に
より形成して両回路を分離する工程と、前記両回路を電
気接続する配線を形成する工程とを含むことを特徴とす
る半導体集積回路の製造方法。
1. A step of mounting a chip having a plurality of circuits formed on the surface of the same semiconductor substrate on a back surface of the chip in a package, and a groove having a required depth on the surface of the semiconductor substrate between the circuits in the mounted state. And a step of forming a wiring for electrically connecting the two circuits by irradiating a laser beam to separate the two circuits, and a method for manufacturing a semiconductor integrated circuit.
JP63011326A 1988-01-21 1988-01-21 Method for manufacturing semiconductor integrated circuit Expired - Lifetime JP2681959B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63011326A JP2681959B2 (en) 1988-01-21 1988-01-21 Method for manufacturing semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63011326A JP2681959B2 (en) 1988-01-21 1988-01-21 Method for manufacturing semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JPH01185930A JPH01185930A (en) 1989-07-25
JP2681959B2 true JP2681959B2 (en) 1997-11-26

Family

ID=11774903

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63011326A Expired - Lifetime JP2681959B2 (en) 1988-01-21 1988-01-21 Method for manufacturing semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JP2681959B2 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4882783A (en) * 1972-02-04 1973-11-05

Also Published As

Publication number Publication date
JPH01185930A (en) 1989-07-25

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