JPS60206058A - Manufacture of multilayer semiconductor device - Google Patents

Manufacture of multilayer semiconductor device

Info

Publication number
JPS60206058A
JPS60206058A JP6094384A JP6094384A JPS60206058A JP S60206058 A JPS60206058 A JP S60206058A JP 6094384 A JP6094384 A JP 6094384A JP 6094384 A JP6094384 A JP 6094384A JP S60206058 A JPS60206058 A JP S60206058A
Authority
JP
Japan
Prior art keywords
substrate
multilayer
semiconductor
semiconductor wafer
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6094384A
Other languages
Japanese (ja)
Other versions
JPH0520906B2 (en
Inventor
Takashi Kato
隆 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6094384A priority Critical patent/JPS60206058A/en
Publication of JPS60206058A publication Critical patent/JPS60206058A/en
Publication of JPH0520906B2 publication Critical patent/JPH0520906B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06551—Conductive connections on the side of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

PURPOSE:To easily obtain the semiconductor device of multilayer structure and high integration degree by means of a conventionally used technique without needing any special technique. CONSTITUTION:Elements are formed on the surface of an Si substrate 11 and fixed to a base 13 via epoxy resin 12, and the back is made abut gainst a polishing plane 15 on a fixing base 14 for a polishing machine and then polished to a thickness of about 50mum. An Si substrate 11' adhered to the base 13 with C22H14 16 is likewise thinly polished, and the backs of both the substrates are adhered to each other. The adhesive 16 is removed by heating and a substrate 18 is produced by trichlene washing. An Si substrate 19 likewise produced via adhesive 20 mainly made of SiO2 is made opposed and pressed with a tool 21. A chip 22 is formed by cutting a multilayer substrate 21, obtained by repetition of this process, with laser beams. The side surface is polished and metallic wirings 24 are applied to the exposed electrode 23; thereafter, the device is completed through a normal method. With this construction, the integration degree of one chip markedly increases with a 70mum thickness per layer: 7mm. in 100 layers.

Description

【発明の詳細な説明】 発明の技術分野 本発明は、集積回路に於ける集積度を向上する為の３次
元構造を有する多層半導体装置を製造する方法に関する
。TECHNICAL FIELD OF THE INVENTION The present invention relates to a method of manufacturing a multilayer semiconductor device having a three-dimensional structure for improving the degree of integration in an integrated circuit.

従来技術と問題点 近年の集積回路に於ける集積度の向上には著しいものが
ある。Prior Art and Problems There has been a remarkable improvement in the degree of integration in integrated circuits in recent years.

然しなから、半導体装置が現在の構造を採る限り、高集
積化もいずれは限界に達するであろうことは疑いのない
ところである。However, there is no doubt that as long as semiconductor devices adopt the current structure, high integration will eventually reach its limit.

そこで、前記のような問題を解消する一手段として、複
数のパッケージを積み重ねて電気的に結合することが行
われている。Therefore, as a means to solve the above-mentioned problems, a plurality of packages are stacked and electrically coupled.

第１図はそのような半導体装置の要部斜面図である。FIG. 1 is a perspective view of essential parts of such a semiconductor device.

図に於いて、１は第１のパンケージ本体、２は第１のパ
ッケージ本体に設けられているピン、３はソケット部、
４は第２のパンケージ本体をそれぞれ示している。In the figure, 1 is the first pan cage body, 2 is a pin provided on the first package body, 3 is a socket part,
4 designates a second pancage body.

この半導体装置で１よ、図示されていないが、第２のパ
ッケージ４にもピンが設けられていて、該ピンをソケッ
ト部３に挿入することに依り第１のパッケージｌと電気
的且つ機械的に結合されるものである。In this semiconductor device 1, although not shown, the second package 4 is also provided with a pin, and by inserting the pin into the socket portion 3, it is electrically and mechanically connected to the first package 1. It is combined with

゛この半導体装置に依ると、成る程度の集積度向上は可
能であるが、それも２〜３倍程度であり、蒸捏期待でき
る技術ではない。``According to this semiconductor device, it is possible to improve the degree of integration to a certain degree, but it is only about two to three times as large, and it is not a technology that can be expected to be improved.

また、半導体装置自体を３次元構造にすることも提案さ
れているが、例えば、分子線エピタキシャル成長（ｍｏ
ｌｅｃｕｌａｒ　ｂｅａｍ　ｅｐｉｔａｘｙ：ＭＢＥ）
法、レーザ・アニール法、選択的エピタキシャル成長法
などの新技術を利用しても、安定性、再現性などの点で
多くの問題を抱えていて、数層以上の多層構造を有する
半導体装置を形成することは不可能に近い。It has also been proposed to make the semiconductor device itself into a three-dimensional structure, but for example, molecular beam epitaxial growth (MO
regular beam epitaxy (MBE)
Even with the use of new technologies such as a method, laser annealing method, and selective epitaxial growth method, there are many problems in terms of stability, reproducibility, etc., and it is difficult to form semiconductor devices with a multilayer structure of several layers or more. It's almost impossible to do.

発明の目的 本発明は、数層以上の多層構造を有する高集積度の半導
体装置を何等特殊な技術を必要とすることなく現用の技
術で容易に製造することができるようにする。OBJECTS OF THE INVENTION The present invention enables a highly integrated semiconductor device having a multilayer structure of several layers or more to be easily manufactured using current technology without requiring any special technology.

発明の構成 本発明に於ける多層半導体装置の製造方法は、半導体ウ
ェハの表面側に諸素子を形成し、次いで、該半導体ウェ
ハを所定厚さにする為に裏面側をラッピング或いはエツ
チング等の技術にて除去し、次いで、２枚の前記所定厚
さにした半導体ウェハの裏面側どうしを導電性膜を介し
貼着して対の半導体ウェハとなし、次いで、該対の半導
体ウェハの所要数を積層して多層半導体ウェハとなし、
次いで、該多層半導体ウェハを分割して多層半導体チッ
プとなし、次いで、該分割に依って露出された該多層半
導体チップの側面に配線を形成する工程が含まれてなる
ことを特徴とする構成を採っている。Structure of the Invention The method for manufacturing a multilayer semiconductor device according to the present invention involves forming various elements on the front side of a semiconductor wafer, and then applying techniques such as lapping or etching on the back side to make the semiconductor wafer a predetermined thickness. Then, the back sides of the two semiconductor wafers having a predetermined thickness are pasted together via a conductive film to form a pair of semiconductor wafers, and then the required number of semiconductor wafers in the pair is determined. Laminated to form a multilayer semiconductor wafer,
Next, the multilayer semiconductor wafer is divided into multilayer semiconductor chips, and then wiring is formed on the side surface of the multilayer semiconductor chip exposed by the division. I'm picking it up.

この構成によれば、極めて高い集積性を有する多層半導
体装置を既存の技術を用い何等の困難もなく実現するこ
とが可能である。According to this configuration, it is possible to realize a multilayer semiconductor device with extremely high integration using existing technology without any difficulty.

発明の実施例 第２図乃至第８図は本発明一実施例を解説する為の工程
要所に於ける半導体ウェハ或いは半導体チップ（第７図
及び第８図）の要部切断側面図及び要部斜面図（第７図
及び第８図）をそれぞれ表し、以下、これ等の図を参照
しつつ説明する。Embodiment of the Invention FIGS. 2 to 8 are cross-sectional side views and essential parts of a semiconductor wafer or semiconductor chip (FIGS. 7 and 8) at key points in the process to explain an embodiment of the present invention. Partial perspective views (FIGS. 7 and 8) are shown, and the following description will be made with reference to these views.

第２図参照 （ａｌ　通常の技法を適用し、シリコン半導体ウェハ、
１１の表面側に諸素子を形成する。See Figure 2 (al) By applying the usual technique, silicon semiconductor wafer,
Various elements are formed on the surface side of 11.

第３図参照 （ｂ）　半導体ウェハ１１の表面側に例えばエポキシ樹
脂１２を施してラッピング・マシーンのウェハ保持台１
３に固着する。Refer to FIG. 3(b) For example, epoxy resin 12 is applied to the front side of the semiconductor wafer 11, and the wafer holding table 1 of the lapping machine is
It sticks to 3.

（Ｃ）　半導体ウェハ１１の裏面側をラッピング・マシ
ーンに於ける固定台１４上に設けられたラップ面１５に
当接し、ウェハ保持台１３を例えば矢印のように左右動
させてラッピングを行う。(C) The back side of the semiconductor wafer 11 is brought into contact with the lapping surface 15 provided on the fixed table 14 of the lapping machine, and the wafer holding table 13 is moved left and right as shown by the arrows to perform lapping.

このようにして、当初、全体で数百〔μｍ〕程度の厚さ
であった半導体ウェハ１１を約５０〔μｍ〕程度の厚さ
にする。In this way, the semiconductor wafer 11, which initially had a total thickness of about several hundred [μm], is made to have a thickness of about 50 [μm].

このように薄くされた半導体ウェハ１１は、その機械的
強度が低下するだけであって、半導体装置としての性能
には何等の影響もないことは勿論である。The semiconductor wafer 11 made thinner in this manner only has its mechanical strength reduced, and it goes without saying that the performance as a semiconductor device is not affected in any way.

第４図参照 （ｄ）　イ列えばピセン（ｐ　ｉ　ｃ　ｅ　ｎ　ｅ　：
　ＣｚｉＨ＋ｎ）ののような熱可塑性接着剤１６でウェ
ハ保持台１３に固着され、半導体ウェハ１１と同様に裏
面側をラッピングすることに依って薄くされた半導体ウ
ェハ１１’を用意する。See Figure 4 (d) Picene:
A semiconductor wafer 11' is prepared, which is fixed to a wafer holder 13 with a thermoplastic adhesive 16 such as CziH+n) and thinned by lapping the back side in the same manner as the semiconductor wafer 11.

（ｅ）　半導体ウェハ１１及び半導体ウェハ１１’の裏
面側どうしを対向させ、例えば銀ペーストのような導電
性膜１７を介して接着する。(e) The back surfaces of the semiconductor wafer 11 and the semiconductor wafer 11' are made to face each other and bonded together via a conductive film 17 such as silver paste.

（ｆｌ　半導体ウェハ１１′をウェハ保持台１３に固着
していた熱可塑性接着剤１６を加熱することに依って除
去し、トリクレンで洗浄する。(fl) The thermoplastic adhesive 16 that had fixed the semiconductor wafer 11' to the wafer holder 13 is removed by heating, and the semiconductor wafer 11' is cleaned with triclean.

このようにして、裏面側どうしを貼着して構成された対
の半導体ウェハ１８が得られる。In this way, a pair of semiconductor wafers 18 having their back sides adhered to each other is obtained.

第５図参照 Ｔｇｌ　対の半導体ウェハ１８にこれと全く同じ工程を
経て作製された対の半導体ウェハ１９を対向させ、接着
剤２０を施してから押圧治具２１で矢印のように押圧力
を加えて接着する。Refer to FIG. 5 Tgl A pair of semiconductor wafers 18 and a pair of semiconductor wafers 19 manufactured through the same process are placed opposite each other, adhesive 20 is applied, and a pressing force is applied using a pressing jig 21 as shown by the arrow. and glue.

この場合の接着剤２０としては二酸化シリコン（ＳｉＯ
ｚ）を主成分とするプロス（商標名：富士通■製）を適
用することができる。In this case, the adhesive 20 is silicon dioxide (SiO
Pros (trade name: manufactured by Fujitsu ■) containing z) as a main component can be applied.

第６図参照 Ｔｈ）　前記（ｇｌの工程を繰り返すことにより、図示
のような多層半導体ウェハ２１が完成する。Refer to FIG. 6 Th) By repeating the step (gl), a multilayer semiconductor wafer 21 as shown in the figure is completed.

第７図参照 （］）　多層半導体ウェハ２１をレーザ・ビームにて切
断し、３次元構造を有する多層半導体チップ２２を形成
する。Refer to FIG. 7 (]) A multilayer semiconductor wafer 21 is cut with a laser beam to form a multilayer semiconductor chip 22 having a three-dimensional structure.

このようにすると、多層半導体チップ２２の側面には、
予め、作り込んであった電極２３が露出される。In this way, on the side surface of the multilayer semiconductor chip 22,
The electrode 23 that has been made in advance is exposed.

第８図参照 （」）多層半導体チップ２２の側面をランピングしてか
ら金属配線２４を形成し、その後、通常の技術を適用し
て完成する。Refer to FIG. 8(''). After ramping the side surfaces of the multilayer semiconductor chip 22, metal interconnections 24 are formed and then completed by applying conventional techniques.

前記工程を経て完成された半導体装置は一層当り７０〔
μｍ〕の厚さであって、１００層を積み重ねると７〔龍
〕になり、１個の多層半導体チップ２２の集積度は従来
の１００倍以上になる。The semiconductor device completed through the above steps has a thickness of 70 [per layer].
[μm] thick, and if 100 layers are stacked, it becomes 7 [dragons], and the degree of integration of one multilayer semiconductor chip 22 is more than 100 times that of the conventional one.

発明の効果 本発明に於ける多層半導体装置の製造方法は、半導体ウ
ニへの表面側に諸素子を形成し、次いで、該半導体ウェ
ハを所定厚さにする為に裏面側をランピング或いはエン
チング等の技術にて除去し、次いで、２枚の前記所定厚
さにした半導体ウェハの裏面側どうしを導電性膜を介し
貼着して対の半導体ウェハとなし、次いで、該対の半導
体ウェハの所要数を積層して多層半導体ウェハとなし、
次いで、該多層半導体ウェハを分割して多層半導体チッ
プとなし、次いで、該分割に依って露出された該多層半
導体チップの側面に配線を形成する工程が含まれてなる
ことを特徴とする構成になっている。Effects of the Invention In the method for manufacturing a multilayer semiconductor device according to the present invention, various elements are formed on the front side of a semiconductor wafer, and then the back side is subjected to ramping, etching, etc. in order to make the semiconductor wafer a predetermined thickness. Then, the back sides of the two semiconductor wafers having a predetermined thickness are bonded together via a conductive film to form a pair of semiconductor wafers, and then the required number of semiconductor wafers in the pair is Stacked to form a multilayer semiconductor wafer,
Next, the multilayer semiconductor wafer is divided into multilayer semiconductor chips, and then wiring is formed on the side surface of the multilayer semiconductor chip exposed by the division. It has become.

この構成を採ることに依って、極めて高い集積性を有す
る多層半導体装置を得ることができ、しかも、それに必
要とされる技術は既存の技術の応用であって、何等特殊
なものではないから容易に実施することが可能である。By adopting this configuration, it is possible to obtain a multilayer semiconductor device with extremely high integration.Moreover, the technology required for this is an application of existing technology and is not anything special, so it is easy to obtain. It is possible to implement

【図面の簡単な説明】[Brief explanation of drawings]

第１図はパッケージを積み重ねることによって高集積化
を図った半導体装置の要部斜面図、第２図−乃至第６図
は本発明一実施例を説明する為の工程要所に於ける半導
体ウェハの要部切断側面図、第７図及び第８図は同じく
半導体チップ要部斜面図をそれぞれ表している。 図に於いて、１１及び１１′は半導体ウェハ、１２はエ
ポキシ樹脂、１３はウェハ保持台、１４は固定台、１５
はラップ面、１６は熱可塑性接着剤、１７は導電性膜、
１８及び１９は対の半導体ウェハ、２０は接着剤、２１
は多層半導体ウェハ、２２は多層半導体チップ、２３は
電極をそれぞれ示している。 特許出願人　富士通株式会社 代理人弁理士　拍　谷　昭　司 代理人弁理士　渡　邊　弘　− 第１図 第２図 第３図 第４図 第５図 第６図Fig. 1 is a perspective view of the main parts of a semiconductor device that achieves high integration by stacking packages, and Figs. , and FIGS. 7 and 8 respectively show oblique views of the essential parts of the semiconductor chip. In the figure, 11 and 11' are semiconductor wafers, 12 is an epoxy resin, 13 is a wafer holding table, 14 is a fixing table, and 15
is a wrap surface, 16 is a thermoplastic adhesive, 17 is a conductive film,
18 and 19 are a pair of semiconductor wafers, 20 is an adhesive, 21
22 represents a multilayer semiconductor wafer, 22 represents a multilayer semiconductor chip, and 23 represents an electrode. Patent Applicant Fujitsu Ltd. Representative Patent Attorney Akio Utoya Representative Patent Attorney Hiroshi Watanabe - Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

【特許請求の範囲】[Claims] 半導体ウェハの表面側に諸素子を形成し、次いで、該半
導体ウェハを所定厚さにする為に裏面側をラッピング或
いはエツチング等の技術にて除去し、次いで、２枚の前
記所定厚さにした半導体ウェハの裏面側どうしを導電性
膜を介し貼着して対の半導体ウェハとなし、次いで、該
対の半導体ウェハの所要数を積層して多層半導体ウェハ
となし、次いで、該多層半導体ウェハを分割して多層半
導体チップとなし、次いで、該分割に依って露出された
該多層半導体チップの側面に配線を形成する工程が含ま
れてなることを特徴とする多層半導体装置の製造方法。Various elements are formed on the front side of a semiconductor wafer, and then the back side of the semiconductor wafer is removed by a technique such as lapping or etching in order to make the semiconductor wafer a predetermined thickness, and then two wafers are made to have the predetermined thickness. The back sides of the semiconductor wafers are attached to each other via a conductive film to form a pair of semiconductor wafers, and then the required number of semiconductor wafers of the pair are stacked to form a multilayer semiconductor wafer. 1. A method for manufacturing a multilayer semiconductor device, comprising the steps of dividing the multilayer semiconductor chip into multilayer semiconductor chips, and then forming wiring on the side surfaces of the multilayer semiconductor chip exposed by the division.
JP6094384A 1984-03-30 1984-03-30 Manufacture of multilayer semiconductor device Granted JPS60206058A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6094384A JPS60206058A (en) 1984-03-30 1984-03-30 Manufacture of multilayer semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6094384A JPS60206058A (en) 1984-03-30 1984-03-30 Manufacture of multilayer semiconductor device

Publications (2)

Publication Number Publication Date
JPS60206058A true JPS60206058A (en) 1985-10-17
JPH0520906B2 JPH0520906B2 (en) 1993-03-22

Family

ID=13156963

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6094384A Granted JPS60206058A (en) 1984-03-30 1984-03-30 Manufacture of multilayer semiconductor device

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JP (1) JPS60206058A (en)

Cited By (10)

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JPS6453440A (en) * 1987-08-25 1989-03-01 Hitachi Ltd Three-dimensional semiconductor integrated circuit device
EP1041624A1 (en) * 1999-04-02 2000-10-04 Interuniversitair Microelektronica Centrum Vzw Method of transferring ultra-thin substrates and application of the method to the manufacture of a multilayer thin film device
WO2009025974A2 (en) * 2007-08-16 2009-02-26 Micron Technology, Inc. Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods
DE102009004168A1 (en) 2008-01-11 2009-07-16 Disco Corp. Layer device manufacturing process
US7692931B2 (en) 2006-07-17 2010-04-06 Micron Technology, Inc. Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods
JP2010183058A (en) * 2009-02-06 2010-08-19 Headway Technologies Inc Layered chip package and method of manufacturing the same
JP2010534951A (en) * 2007-07-27 2010-11-11 テッセラ，インコーポレイテッド Reconfigured wafer stack packaging with pad extension after application
JP2010536171A (en) * 2007-08-03 2010-11-25 テセラ・テクノロジーズ・ハンガリー・ケイエフティー Stacked package using recycled wafer
US7843050B2 (en) 2007-07-24 2010-11-30 Micron Technology, Inc. Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
US7858497B2 (en) 2008-10-22 2010-12-28 Disco Corporation Stacked device manufacturing method

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6453440A (en) * 1987-08-25 1989-03-01 Hitachi Ltd Three-dimensional semiconductor integrated circuit device
EP1041624A1 (en) * 1999-04-02 2000-10-04 Interuniversitair Microelektronica Centrum Vzw Method of transferring ultra-thin substrates and application of the method to the manufacture of a multilayer thin film device
US7692931B2 (en) 2006-07-17 2010-04-06 Micron Technology, Inc. Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods
US8869387B2 (en) 2006-07-17 2014-10-28 Micron Technology, Inc. Methods for making microelectronic die systems
US8906744B2 (en) 2007-07-24 2014-12-09 Micron Technology, Inc. Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
US8198720B2 (en) 2007-07-24 2012-06-12 Micron Technology, Inc. Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
US10056359B2 (en) 2007-07-24 2018-08-21 Micron Technology, Inc. Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
US9653444B2 (en) 2007-07-24 2017-05-16 Micron Technology, Inc. Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
US7843050B2 (en) 2007-07-24 2010-11-30 Micron Technology, Inc. Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
US9165910B2 (en) 2007-07-24 2015-10-20 Micron Technology, Inc. Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
JP2010534951A (en) * 2007-07-27 2010-11-11 テッセラ，インコーポレイテッド Reconfigured wafer stack packaging with pad extension after application
JP2010536171A (en) * 2007-08-03 2010-11-25 テセラ・テクノロジーズ・ハンガリー・ケイエフティー Stacked package using recycled wafer
WO2009025974A3 (en) * 2007-08-16 2009-05-07 Micron Technology Inc Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods
US7947529B2 (en) 2007-08-16 2011-05-24 Micron Technology, Inc. Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods
WO2009025974A2 (en) * 2007-08-16 2009-02-26 Micron Technology, Inc. Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods
US7687375B2 (en) 2008-01-11 2010-03-30 Disco Corporation Lamination device manufacturing method
TWI485762B (en) * 2008-01-11 2015-05-21 Disco Corp The manufacturing method of the laminated apparatus
DE102009004168A1 (en) 2008-01-11 2009-07-16 Disco Corp. Layer device manufacturing process
US7858497B2 (en) 2008-10-22 2010-12-28 Disco Corporation Stacked device manufacturing method
JP2010183058A (en) * 2009-02-06 2010-08-19 Headway Technologies Inc Layered chip package and method of manufacturing the same

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