JP2583764B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for thermally bonding a semiconductor substrate, which is necessary for obtaining a semiconductor integrated circuit device having a laminated structure effective for increasing the density and increasing the speed of a semiconductor integrated circuit. It is about.

(Prior art and its problems) The inventor of the present application has disclosed a structure and a method of thermally bonding a semiconductor substrate on which an insulator having a thermal softening phenomenon is formed as a technique of this kind in Japanese Patent Application No. 60-13502. Proposed. As a method of thermal bonding, a method of performing heat treatment after closely contacting. In order to ensure close contact, under pressure reduction, first heat bonding the peripheral part, then heat treatment under atmospheric pressure, and in the method, propose a method of forming grooves in parts other than the peripheral part did.

These methods have the following disadvantages. Although it is necessary to ensure that only the peripheral portion is thermally bonded, a semiconductor substrate of several microns to several tens of microns is required. There is this It is difficult to correct and adhere. The purpose of performing heat treatment at atmospheric pressure after peripheral heat bonding is to achieve the effect of correcting the warpage of the wafer by atmospheric pressure.However, when pressure higher than atmospheric pressure is required for correction, bonding is performed. Non-uniformity occurs.

On the other hand, recently, a method of bonding wafers using electrostatic attraction has been proposed by Frye et al. Of BTL (J. Electroche
m Soc Vol.133 No.8 p1673) In this method, a voltage is applied between two silicon wafers through an insulating film under atmospheric pressure, and the adhesion is improved by electrostatic attraction generated between the wafers. It is a method of heat bonding in the state of being held. This method is excellent in that the electrostatic attraction force can be increased to atmospheric pressure or higher, but has the following disadvantages.

That is, FIG. 1 shows a state in the case of this method, wherein 1-1 is a trapped bubble, 1-2, 1-5 is a semiconductor substrate, and 1-3, 1-4 are insulator films. However, when air bubbles 1-1 are trapped on the bonding surface,
Cannot be removed, resulting in non-uniform adhesion. Since a thermal oxide film of Si is used for the bonding surface, bonding cannot be performed unless the temperature is higher than 1100 ° C.

Among these drawbacks, Japanese Patent Application No. 60-13502
As proposed in (1), the use of PSG or BPSG, which has a lower thermal softening temperature than the thermal oxide film of Si, can reduce the thermal bonding temperature. However, since the size and location of the air bubble 1-1 trapped inside cannot be controlled, the bonding strength is reduced, and after bonding, one of the semiconductor substrates is thinned to form an SOI structure and then an element is formed. In this case, there is a problem that the yield is reduced.

(Object of the Invention) It is an object of the present invention to provide a method of manufacturing a semiconductor integrated circuit device which removes air bubbles generated on a bonding surface when bonding a semiconductor substrate and enables reliable bonding over the entire surface of the substrate. It is in.

(Features of the Invention) The present invention relates to a method of bonding a semiconductor substrate having an insulating film having thermal softening property formed thereon to another substrate having an insulating film having thermal softening property formed thereon, wherein a voltage is applied between the two substrates. A step of generating an electrostatic attraction force by applying to improve the adhesion required for thermal bonding, and forming a “groove” on at least one surface of the substrate to prevent air bubbles from being generated on the bonding surface, Alternatively, the main feature is that the heat bonding treatment is performed in a reduced-pressure atmosphere or both are used in combination.

 Hereinafter, the present invention will be described in detail with reference to the drawings.

(Embodiment) FIGS. 2 (a), (b), (c) and (d) are diagrams for explaining a first embodiment of the present invention, wherein 2-1 and 2-6 are a silicon substrate and 2-2. , 2-5 is a silicon oxide film used as an insulating film, and 2-3, 2-4 are silicon oxide films containing a large amount of phosphorus used as an insulating film which causes a softening phenomenon by heat treatment. Silicon substrate 2-1 and 2-6 have a thickness of 500
It has a diameter of 10 μm and a diameter of 10 cm. 2-2,2-5 has a thickness of 6000 ° and is obtained by oxidizing silicon in steam. 2-3,2-4 is P
Chemical vapor deposition method (CVD method) using H ₃ , SiH ₄ and O ₂ as raw materials
Has a thickness of 1 μm. further,
2-4 has a lattice-shaped groove 2-8 having a pitch of 1 mm and a width of 100 μm.
Are formed at a depth of 1 μm. Next, the two substrates are brought into contact with each other so as to face each other, and a voltage is applied from the DC voltage source 2-7 between the silicon substrates 2-1 and 2-6. In this state
The silicon oxide film 2 is formed by performing a heat treatment in an N ₂ atmosphere.
-3,2-4 are mutually bonded.

In the embodiment of FIG. 2, the silicon substrates 2-1 and 2-6 are Si
Although a substrate is used, this may be another semiconductor substrate, for example, a compound semiconductor such as GaAs or a Ge substrate, or an integrated circuit element may be formed. The silicon oxide films 2-2 and 2-5 are formed in order to prevent phosphorus contained in the silicon oxide films 2-3 and 2-4 from diffusing into the silicon substrates 2-1 and 2-6 during the heat treatment. And has nothing to do with the adhesive effect.
Therefore, it can be omitted, or another film (for example, a Si ₃ N ₄ film, a CVD SiO ₂ film, or the like) can be used.

Further, the PSG film is used for the silicon oxide films 2-3 and 2-4, but this may be a film having thermosetting properties.
When using BPSG (SiO ₂ containing boron and phosphorus)
Since the thermosetting temperature is lower than PSG, it is possible to heat bond at a lower temperature.

Next, the effects of electrostatic attraction and groove formation in the embodiment of FIG. 2 will be described. 3, 4 and 5 are views showing the bonding state of the substrate after the thermal bonding by an infrared transmission method. FIG. 3 shows a case where only the electrostatic attraction is used without forming a groove. FIG. 4 shows a case where a groove is formed and electrostatic attraction is not used, and FIG. 5 shows a case where both are used. Several white dots 3-2 shown in FIG. 3 are portions where bonding was incomplete due to bubbles trapped inside because no grooves were formed.

Also, FIG. 4 shows that no air bubbles are generated inside due to the formation of the groove, but there is an unbonded portion in the peripheral portion 4-2, and no electrostatic attraction was performed between the two substrates. This indicates that contact was insufficient. On the other hand, in FIG. 5, the entire surface of the silicon substrate having a diameter of 10 cm is the bonding portion 5-1.
Thermal bonding as shown by.

In the first embodiment, the grooves 2-8 shown in FIG. 2 are formed at a pitch of 1 mm, a width of 100 μm, and a depth of 1 μm. However, these grooves are used for removing gas remaining inside during bonding. Obviously, it is not limited to this dimension.

FIG. 6 shows a second embodiment of the present invention.
6 is the same as 2-1 to 2-6, respectively, but in this embodiment, the insulator layers 6-3 and 6-6 which cause a softening phenomenon by heat treatment.
No groove is formed in 4. The bonding substrate is placed in the vacuum container 6-8. Thus, the vacuum vessel 6
By subjecting the substrate to electrostatic adsorption and heat treatment under reduced pressure as shown in FIG. 8, since there is no gas that causes bubbles, almost complete adhesion is possible without forming a groove.

Further, although not shown, it is needless to say that even if the effect of the groove and the effect of the reduced pressure are used together, the respective effects are superimposed and the bubbles can be more effectively removed.

(Effects of the Invention) As described above, according to the first embodiment of the present invention, by forming a groove in a thermosoftening insulator, the effect of electrostatic adsorption is enhanced and bubbles are formed in an arbitrary gas atmosphere. Bonding that does not occur. Further, the second embodiment has an advantage that the formation of the groove is not required by performing the electrostatic attraction and the heat treatment in a vacuum. Furthermore, the foam removal effect can be further improved by using these together. According to the present invention, it is possible to bond with an insulator that does not generate bubbles inside, and as an application field, in the SOI technology of thinning one semiconductor substrate and forming an element there, a high effect that is not affected by bubbles Yield is obtained. By repeatedly performing thinning, element formation, and adhesive thinning, a multilayer stacked LSI can be realized, which has an advantage that a high-density and high-speed integrated circuit can be formed.

[Brief description of the drawings]

FIG. 1 is a sectional view for explaining the disadvantages of the prior art, and FIG.
2 (a) and 2 (c) are a plan view and a cross-sectional view of a substrate having a groove used in the present invention, FIG. 2 (b) is a partially enlarged view of FIG. 2 (c), and FIG. ) Is a cross-sectional view for explaining the process of the present invention, FIGS. 3, 4 and 5 are simulated views of a photograph obtained by inspecting an adhesion state by an infrared transmission method, and FIG. 6 is another view of the present invention. 1 is a schematic cross-sectional view for explaining an embodiment. 1-1: air bubble, 1-2, 1-5 ... semiconductor substrate, 1-3, 1
-4 ... insulating film, 2-1,2-6,6-1,6-6 ... silicon substrate, 2-2,2-5,6-2,6-5 ... silicon oxide film
2-3,2-4,6-3,6-4 ... a silicon oxide film containing a large amount of phosphorus, 2-7 ... DC voltage source, 2-8 ... groove, 3-1,
4-1, 5-1: bonded part, 3-2, 4-2: non-bonded part, 6
-8: Vacuum container.

Claims (3)

(57) [Claims] 1. A first step of forming a first insulator layer which causes a softening phenomenon by heat treatment on a semiconductor substrate or a first substrate on which a semiconductor integrated circuit is formed, and another semiconductor substrate or a semiconductor integrated circuit. A second step of forming a second insulator layer which causes a softening phenomenon by heat treatment on a second substrate formed of any one of the substrates on which the circuit is formed, and the first insulator layer or the second insulator layer; A third step of forming a groove on at least one entire surface of the insulator layer;
Substrate and the second substrate, the first insulator layer and the second
A fourth step of applying a voltage between the two substrates in a state where the two substrates are brought into contact with each other so that the two insulating layers are opposed to each other, and a fifth step of heating while applying the voltage. A method for manufacturing a semiconductor integrated circuit device. 2. A first step of forming a first insulator layer which causes a softening phenomenon by heat treatment on a semiconductor substrate or a first substrate on which a semiconductor integrated circuit is formed, and another semiconductor substrate or semiconductor integrated circuit. A second step of forming a second insulator layer that causes a softening phenomenon by heat treatment on a second substrate formed of any one of the substrates on which circuits are formed; A third step of applying a voltage under reduced pressure between the first and second substrates in a state where the first and second insulating layers are opposed to each other and the two substrates are in contact with each other; A method for manufacturing a semiconductor integrated circuit device, comprising at least a fourth step of heating under a voltage applied state. 3. A first step of forming a first insulator layer which causes a softening phenomenon by heat treatment on a semiconductor substrate or a first substrate on which a semiconductor integrated circuit is formed, and another semiconductor substrate or a semiconductor integrated circuit. A second step of forming a second insulator layer which causes a softening phenomenon by heat treatment on a second substrate formed of any one of the substrates on which the circuit is formed, and the first insulator layer or the second insulator layer; A third step of forming a groove on at least one entire surface of the insulator layer;
Substrate and the second substrate, the first insulator layer and the second
A fourth step of applying a voltage between the two substrates under reduced pressure in a state where the two substrates are brought into contact with each other by facing the insulator layer, and a fifth step of heating while applying a voltage under the reduced pressure.
A method for manufacturing a semiconductor integrated circuit device, comprising at least the steps of: