JP2589994B2 - Wafer bonding method - Google Patents
Wafer bonding methodInfo
- Publication number
- JP2589994B2 JP2589994B2 JP62333867A JP33386787A JP2589994B2 JP 2589994 B2 JP2589994 B2 JP 2589994B2 JP 62333867 A JP62333867 A JP 62333867A JP 33386787 A JP33386787 A JP 33386787A JP 2589994 B2 JP2589994 B2 JP 2589994B2
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- bonding
- wafers
- temperature
- heated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 title claims description 10
- 239000011261 inert gas Substances 0.000 claims description 6
- 230000002093 peripheral effect Effects 0.000 claims description 5
- 235000012431 wafers Nutrition 0.000 description 72
- 239000010408 film Substances 0.000 description 10
- 238000010438 heat treatment Methods 0.000 description 7
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 4
- 229910052799 carbon Inorganic materials 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 238000003672 processing method Methods 0.000 description 2
- 125000005372 silanol group Chemical group 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Formation Of Insulating Films (AREA)
- Element Separation (AREA)
Description
【発明の詳細な説明】 〔概要〕 ウエーハの接着方法に関し、特に２枚の大口径ウエー
ハの接着の場合における未接着領域の発生を防止すると
共に接着処理手段及び接着処理方法の簡単化を実現しう
るようにすることを目的とし、不活性ガス雰囲気中もし
くは真空中で第１のウエーハを加熱し、その上に第１の
ウエーハより低温の第２のウエーハを、外力を加えるこ
となく中心をほぼ一致させるようにして重ね合わせ、第
２のウエーハでの接着面と反対面との温度差を生じさせ
第２のウエーハを接着面に対し凸状に変形させ、続いて
第２のウエーハ内部の温度の均一化に伴う第２のウエー
ハの変形の回復過程で第１のウエーハに対する第２のウ
エーハの接触を中心部から徐々に周縁部に向かって進行
させ最終的に全域において接触させるようにする。DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method of bonding wafers, in particular, to prevent the occurrence of an unbonded area in the case of bonding two large-diameter wafers, and to simplify the bonding processing means and bonding processing method. The first wafer is heated in an inert gas atmosphere or in a vacuum, and a second wafer lower in temperature than the first wafer is placed on the first wafer without applying an external force. The two wafers are superposed so as to match each other, and a temperature difference between the bonding surface of the second wafer and the opposite surface is generated to deform the second wafer into a convex shape with respect to the bonding surface. In the process of recovering the deformation of the second wafer due to the uniformity of the first wafer, the contact of the second wafer with the first wafer is gradually advanced from the center toward the peripheral edge, and finally the entire wafer is brought into contact. To.
本発明はシリコン等からなる２枚のウエーハを接着
し、一方のウエーハを薄膜化してSOI（シリコン・オン
・インシュレータ）基板を得る場合のウエーハの接着方
法に関する。The present invention relates to a method of bonding two wafers made of silicon or the like, and bonding one of the wafers to a thin film to obtain an SOI (silicon-on-insulator) substrate.
Siウエーハを重ね合わせ、熱処理により接着したあと
片方にウエーハを薄膜化した、いわゆる貼り付けSOI基
板は高性能LSI用基板として有用である。A so-called bonded SOI substrate obtained by laminating Si wafers and bonding them by heat treatment and then thinning the wafer on one side is useful as a high-performance LSI substrate.
しかしながら大口径ウエーハを均一に接着することは
容易でなく、大抵の場合部分的に接着していない領域が
発生する。そしてかかる未接着領域の存在はその後の工
程に大きな影響を与え、素子の歩留りを著しく低下させ
る。また熱処理時に未接着領域のSiが剥離し、Si片が飛
散したりすると処理装置を汚染することにもなる。However, it is not easy to bond a large-diameter wafer uniformly, and in most cases, a partially unbonded region occurs. The presence of the unbonded region has a great effect on the subsequent steps, and significantly reduces the yield of the device. In addition, the Si in the unbonded area is peeled off during the heat treatment, and if the Si pieces are scattered, the processing apparatus is contaminated.
本発明はこのような問題点を解決し大口径ウエーハで
も未接着領域の発生を抑え、処理手段、処理工程を簡単
化しうるようにすることを目的とする。SUMMARY OF THE INVENTION It is an object of the present invention to solve such a problem and suppress the occurrence of an unbonded area even in a large-diameter wafer, so that processing means and processing steps can be simplified.
上記目的は本発明により、不活性ガス雰囲気中もしく
は真空中で第１のウエーハを加熱し、その上に第１のウ
エーハより低温の第２のウエーハを、外力を加えること
なく中心をほぼ一致させるようにして重ね合わせ、第２
のウエーハでの接触面と反対面との温度差を生じさせ、
第２のウエーハを接着面に対し凸状に変形させ、続いて
第２のウエーハ内部の温度の均一化に伴う第２のウエー
ハの変形の回復過程で第１のウエーハに対する第２のウ
エーハの接触を中心部から徐々に周縁部に向かって進行
させ、最終的に全域において接触させることを特徴とす
るウエーハの接着方法によって達成される。According to the present invention, the first wafer is heated in an inert gas atmosphere or in a vacuum, and the center of the second wafer having a lower temperature than that of the first wafer is almost aligned without applying an external force. And the second
Causes a temperature difference between the contact surface and the opposite surface of the wafer,
The second wafer is deformed in a convex shape with respect to the bonding surface, and subsequently, the second wafer is brought into contact with the first wafer in a process of recovering the deformation of the second wafer due to the equalization of the temperature inside the second wafer. Is gradually advanced from the central part toward the peripheral part, and finally brought into contact with the whole area.
本発明では不活性ガス雰囲気中あるいは真空中におけ
る第1,第２のウエーハの接着処理ではあるが、第１のウ
エーハを最初に加熱し、この第１のウエーハ上に第２の
ウエーハを外力を加えることなしに単に重ね合わせれば
よい。そしてこの場合かかる重ね合わせによって第２の
ウエーハの接着面と反対面との間に温度差を生じ、この
ため第２のウエーハが接着面に対し凸状に変形し、続い
てかかる状態で第２のウエーハの接着面と反対面との温
度差が小となるにつれて、第２のウエーハは凸状から平
板状に戻りはじめ、これによって第１のウエーハに対
し、第２のウエーハが中心部から周縁部に向かって徐々
に接着される。In the present invention, although the first and second wafers are bonded in an inert gas atmosphere or in a vacuum, the first wafer is first heated, and the second wafer is subjected to an external force on the first wafer. Simply superimpose without adding. In this case, the overlapping causes a temperature difference between the bonding surface of the second wafer and the opposite surface, so that the second wafer is deformed in a convex shape with respect to the bonding surface. As the temperature difference between the bonded surface and the opposite surface of the wafer becomes smaller, the second wafer starts to return from the convex shape to the flat plate shape, whereby the second wafer is moved from the center to the peripheral edge with respect to the first wafer. Glued gradually toward the part.
従って本発明による接着方法によればウエーハ間に間
隙の生ずることもなく、また第１のウエーハの加熱によ
ってウエーハ表面の過剰なシラノール基や吸着している
水分は低減され、新たな空隙の発生が防止されるばかり
でなく、接着処理手段も、従って接着処理方法も簡単化
される。Therefore, according to the bonding method of the present invention, no gap is formed between the wafers, and excess silanol groups and adsorbed moisture on the wafer surface are reduced by heating the first wafer, and new voids are generated. Not only is this prevented, but also the bonding process and thus the bonding process is simplified.
第１図（ａ）に示すようにSiウエーハ１をスチーム酸
化した表面にSiO22を形成する。酸化温度は1100℃、酸
化時間は１時間、Si膜厚は0.5μｍである。As shown in FIG. 1 (a), SiO 2 2 is formed on the surface of the Si wafer 1 steam-oxidized. The oxidation temperature is 1100 ° C., the oxidation time is 1 hour, and the Si film thickness is 0.5 μm.
次いで第１図（ｂ）に示すように不活性ガス雰囲気中
もしくは真空中で片方のウエーハ１をカーボンヒータ３
上に置き50〜500℃の範囲で加熱する。Next, as shown in FIG. 1 (b), one of the wafers 1 is placed in a carbon heater 3 in an inert gas atmosphere or vacuum.
Place on top and heat in the range of 50-500 ° C.
次に第１図（ｃ）に示すように少なくとも加熱中のウ
エーハ１より50℃以上低温のウエーハ４を圧力を加える
ことなく加熱中のウエーハ１上に置く。Next, as shown in FIG. 1 (c), a wafer 4 at least 50.degree. C. lower than the wafer 1 being heated is placed on the wafer 1 being heated without applying pressure.
かかる状態で重ねたウエーハ４の片面が加熱され接着
面に対して凸状に変形したあと熱の伝達とともに接着面
と反対面との温度差が小さくなることにより変形がなく
なり、第１図（ｄ）に示すように下のウエーハ１と均一
に接触する。In this state, one surface of the stacked wafers 4 is heated and deformed in a convex shape with respect to the bonding surface. After that, heat is transmitted and the temperature difference between the bonding surface and the opposite surface is reduced, so that the wafer 4 is not deformed. As shown in ()), the wafer comes into uniform contact with the lower wafer 1.
そして上に置いたウエーハ４の温度が上昇し定常状態
に近くなるまで放置したあと、カーボンヒータ３により
500〜1200℃まで加熱しウエーハ1,4を接着する。Then, after the temperature of the wafer 4 placed thereon is raised and the temperature becomes close to a steady state, the wafer is left by the carbon heater 3.
Heat to 500-1200 ° C and bond wafers 1,4.
このときウエーハ1,4間に電圧をかけて静電圧力を発
生させウエーハ1,4間の密着性を良くすることはより均
一で強固な接着を得るために効果的である。At this time, applying a voltage between the wafers 1 and 4 to generate electrostatic pressure to improve the adhesion between the wafers 1 and 4 is effective to obtain more uniform and strong adhesion.
また片面加熱では接着されたウエーハに反りが発生す
るためその上にさらにカーボンヒータ５を置き均一に加
熱したほうがよい。In addition, since the bonded wafer is warped by single-sided heating, it is better to place a carbon heater 5 on the wafer and heat the wafer uniformly.
700℃以上になったら加熱をやめ接着されたウエーハ
を取り出して、通常の電気炉で700〜1200℃まで加熱し
てもよい。When the temperature reaches 700 ° C. or higher, the heating may be stopped and the bonded wafer may be taken out and heated to 700 to 1200 ° C. in a normal electric furnace.
なお本実施例では酸化膜を積極的に被着させている
が、ウエーハ間の接着性を向上させるためである。しか
し積極的に酸化膜を被着させなくても通常のウエーハの
取り扱いでは自然酸化膜は存在するのでそのまま利用し
てもよく、その際自然酸化膜が一方のウエーハのみ場
合、あるいは本発明の如く不活性ガス雰囲気中或いは真
空中で接着処理を行う場合において両方共自然酸化膜の
生じないようなこともあるが、その場合でも接着は可能
である。なお自然酸化膜の存在のもとでの接着を行った
場合、後加工における加熱の際接着面の自然酸化膜はSi
基板中に拡散して消失する。In this embodiment, the oxide film is positively applied, but this is for improving the adhesiveness between the wafers. However, even if an oxide film is not positively applied, a normal oxide film may be used as it is in a normal wafer handling because the natural oxide film exists, and in that case, when the natural oxide film is only one wafer, or as in the present invention, In both cases where the bonding treatment is performed in an inert gas atmosphere or in a vacuum, a natural oxide film may not be formed in both cases, but bonding is possible even in such a case. When bonding in the presence of a natural oxide film, the natural oxide film on the bonding surface is
It diffuses into the substrate and disappears.
本発明では加熱した第１のウエーハ上に、より低温の
第２のウエーハを圧力を加えずに重ねウエーハを凸状に
変形させ、その後第２のウエーハの変形の回復過程での
中心部から周縁部分への徐々の接触により、第１と第２
のウエーハの全域で均一な接触を得た。In the present invention, a second wafer having a lower temperature is stacked on the heated first wafer without applying pressure, and the wafer is deformed in a convex shape. Then, from the center to the peripheral edge in the recovery process of the deformation of the second wafer With gradual contact with the parts, the first and second
A uniform contact was obtained over the entire area of the wafer.
また第１のウエーハをあらかじめ加熱しておくことに
より、第１のウエーハ表面の過剰にシラノール基や吸着
している水分を低減することができ、その後の加熱にお
いて未接着領域の発生が抑制された。Further, by heating the first wafer in advance, excessive silanol groups and adsorbed moisture on the surface of the first wafer can be reduced, and the occurrence of an unbonded region in subsequent heating is suppressed. .
このことにより大口径ウエーハにおいても未接着領域
の発生は防止され、接着の均一性は大幅に改善されるば
かりではなく、処理手段及び処理方法も簡単化される。As a result, even in a large-diameter wafer, an unbonded region is prevented from being generated, and not only the uniformity of bonding is greatly improved, but also the processing means and the processing method are simplified.
第１図（ａ）〜（ｄ）は本発明の一実施例を示す工程順
断面図である。 図において、 1,4はウエーハ、 2,2′は絶縁膜（SiO2）、 ３はカーボンヒータ、 を示す。1 (a) to 1 (d) are step-by-step sectional views showing an embodiment of the present invention. In the figure, 1, 4 denotes a wafer, 2, 2 ′ denotes an insulating film (SiO 2 ), and 3 denotes a carbon heater.
Claims (1)
のウエーハを加熱し、その上に第１のウエーハより低温
の第２のウエーハを、外力を加えることなく中心をほぼ
一致させるようにして重ね合わせ、第２のウエーハでの
接着面と反対面との温度差を生じさせ、第２のウエーハ
を接着面に対し凸状に変形させ、続いて第２のウエーハ
内部の温度を均一化に伴う第２のウエーハの変形の回復
過程で第１のウエーハに対する第２のウエーハの接触を
中心部から徐々に周縁部に向かって進行させ、最終的に
全域において接触させることを特徴とするウエーハの接
着方法。1. The method according to claim 1, wherein the first step is performed in an inert gas atmosphere or in a vacuum.
Is heated, and a second wafer, which is lower in temperature than the first wafer, is superimposed thereon so that the centers thereof are substantially aligned without applying an external force. Is caused, the second wafer is deformed in a convex shape with respect to the bonding surface, and then the first wafer is recovered in the process of recovering the deformation of the second wafer due to uniforming the temperature inside the second wafer. A second wafer is gradually contacted from the center toward the peripheral edge, and finally contacted over the entire area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62333867A JP2589994B2 (en) | 1987-12-24 | 1987-12-24 | Wafer bonding method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62333867A JP2589994B2 (en) | 1987-12-24 | 1987-12-24 | Wafer bonding method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01169917A JPH01169917A (en) | 1989-07-05 |
| JP2589994B2 true JP2589994B2 (en) | 1997-03-12 |
Family
ID=18270833
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62333867A Expired - Lifetime JP2589994B2 (en) | 1987-12-24 | 1987-12-24 | Wafer bonding method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2589994B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0824100B2 (en) * | 1989-07-19 | 1996-03-06 | 富士通株式会社 | Method for manufacturing SOI substrate |
| US5300175A (en) * | 1993-01-04 | 1994-04-05 | Motorola, Inc. | Method for mounting a wafer to a submount |
| US5843832A (en) * | 1995-03-01 | 1998-12-01 | Virginia Semiconductor, Inc. | Method of formation of thin bonded ultra-thin wafers |
| FR2848337B1 (en) * | 2002-12-09 | 2005-09-09 | Commissariat Energie Atomique | METHOD FOR PRODUCING A COMPLEX STRUCTURE BY ASSEMBLING STRESS STRUCTURES |
| JP4624836B2 (en) * | 2005-03-30 | 2011-02-02 | 信越半導体株式会社 | Manufacturing method of bonded wafer and wafer holding jig used therefor |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61145839A (en) * | 1984-12-20 | 1986-07-03 | Toshiba Corp | Semiconductor wafer bonding method and bonding jig |
| JPS6271215A (en) * | 1985-09-25 | 1987-04-01 | Toshiba Corp | Wafer jointing apparatus |
-
1987
- 1987-12-24 JP JP62333867A patent/JP2589994B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01169917A (en) | 1989-07-05 |
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