JPH06196377A - Bonding method for semiconductor substrates - Google Patents

Bonding method for semiconductor substrates

Info

Publication number
JPH06196377A
JPH06196377A JP32997591A JP32997591A JPH06196377A JP H06196377 A JPH06196377 A JP H06196377A JP 32997591 A JP32997591 A JP 32997591A JP 32997591 A JP32997591 A JP 32997591A JP H06196377 A JPH06196377 A JP H06196377A
Authority
JP
Japan
Prior art keywords
substrate
film
stress
thickness
substrates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP32997591A
Other languages
Japanese (ja)
Inventor
Haruo Shiratori
治男 白鳥
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Metal Mining Co Ltd
Original Assignee
Sumitomo Metal Mining Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Metal Mining Co Ltd filed Critical Sumitomo Metal Mining Co Ltd
Priority to JP32997591A priority Critical patent/JPH06196377A/en
Publication of JPH06196377A publication Critical patent/JPH06196377A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a method wherein a proper internal stress is introduced into a film on a substrate manufactured by a pasting method by utilizing a change in the length of the surface when a substrate to be bonded is deformed elastically. CONSTITUTION:1) Two silicon wafers 1 whose diameter is 100mm and whose thickness is 500mum are prepared, thermal oxide films 2 whose thickness is 0.5mum are formed on individual surfaces. 2) One substrate is sucked to a vacuum suction-type plate whose surface has been formed to be a protrusion shape in a radius of curvature of 50 m, it is deformed, and another substrate is overlapped on it and bonded temporarily. 3) A vacuum suction operation is released, it is confirmed that no exfoliation due to a stress has been caused, the substrates are inserted in a heat treatment furnace, and a heat treatment is executed in a nitrogen atmosphere at 1100 deg.C for two hours. 4) The substrates are polished from the side of the substrate which has been deformed previously, and a film 3 in a thickness of 2 um is left. Thereby, it is possible to introduce a uniform compressive or tensile stress into the inside of a film on a substrate formed by a pasting method.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、張り合わせ法を用いた
半導体素子形成用基板(以下基板と呼ぶ)の製造方法に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a substrate for forming a semiconductor element (hereinafter referred to as a substrate) using a bonding method.

【0002】[0002]

【従来の技術】大面積で良質なシリコン薄膜単結晶を有
するSOI(Silicon on Insulator)基板を得る方法と
して、あるいは表面から深い位置に急峻な不純物濃度勾
配を持つ半導体基板を得る方法として、直接接合法が利
用される。SOI基板を得るには、まず表面を鏡面に仕
上げたシリコン基板を2枚用意し、一方または両方の基
板表面に絶縁膜を形成する。次に基板の絶縁膜(鏡面)
同士を軽く接触させ仮接合状態にし、これを高温で熱処
理して一体化させ接合を完了する。最後に一方の基板を
研磨、エッチングなどにより所望の厚さを残して除去す
るとSOI基板が完成する。急峻な不純物濃度勾配を目
的とする場合には、所望の不純物分布の基板を用意し、
絶縁膜を形成することなく上述の手順で基板同士を直接
接合する。
2. Description of the Related Art As a method for obtaining an SOI (Silicon on Insulator) substrate having a large area and good quality silicon thin film single crystal, or a method for obtaining a semiconductor substrate having a steep impurity concentration gradient at a deep position from the surface, direct contact is performed. Legal is used. In order to obtain an SOI substrate, first, two silicon substrates whose surfaces are mirror-finished are prepared, and an insulating film is formed on the surface of one or both substrates. Next, the insulating film on the substrate (mirror surface)
The two are lightly contacted with each other to be in a temporarily joined state, which is then heat treated at a high temperature to be integrated to complete joining. Finally, one of the substrates is removed by polishing, etching, etc., leaving a desired thickness to complete the SOI substrate. For the purpose of a steep impurity concentration gradient, prepare a substrate with the desired impurity distribution,
The substrates are directly bonded to each other by the procedure described above without forming an insulating film.

【0003】[0003]

【発明が解決しようとする課題】このようにして製作し
た基板に素子を形成するとき、薄膜化した基板(以下、
膜と呼ぶ)の内部応力が素子の性能や製造歩留りを左右
する場合がある。膜の応力の問題はとくにダイヤフラム
や梁などの構造を持つ素子においてより深刻である。た
とえば膜内に圧縮応力が存在すると、膜を利用して形成
したダイヤフラムや梁にたわみが生じ、これを利用する
センサーなどでは原点付近で大きな不感帯を持つ。引っ
張り応力はダイヤフラム用途に限らず一般に好ましいと
考えられるが、これが極端に大きいと基板の反りなどを
生じ素子製造プロセスの障害となる。また膜内で応力が
不均一に分布しているとそれが素子特性のバラツキとな
って現れる。従来の方法においては膜に内部応力を導入
することは不可能であった。このため膜内の応力分布
は、基板の反りや表面の凸凹、またはハンドリングに伴
う基板の変形などの不安定な要因が支配的となってい
た。本発明は、張り合わせ法により製作する基板の膜に
適度な内部応力を導入する方法を提供する。
When an element is formed on the substrate thus manufactured, a thinned substrate (hereinafter, referred to as
Internal stress (which is called a film) may affect the performance of the device and the manufacturing yield. The problem of film stress is more serious in devices having structures such as diaphragms and beams. For example, when a compressive stress is present in the film, the diaphragm or beam formed by using the film is bent, and a sensor or the like using this has a large dead zone near the origin. The tensile stress is generally considered to be preferable not only for the diaphragm application, but if it is extremely large, the substrate warps and the like, which becomes an obstacle to the element manufacturing process. Further, if the stress is unevenly distributed in the film, it appears as variations in device characteristics. In the conventional method, it was impossible to introduce internal stress into the film. Therefore, the stress distribution in the film is dominated by unstable factors such as the warp of the substrate, the unevenness of the surface, or the deformation of the substrate due to handling. The present invention provides a method for introducing an appropriate internal stress into a film of a substrate manufactured by a laminating method.

【0004】[0004]

【問題を解決するための手段】実験によれば、製作した
基板の膜の内部応力は仮接合時の状態で決まり、これに
続く熱処理および薄膜化のための加工工程における応力
の緩和はほとんどない。すなわち、仮接合状態の各々の
基板に引っ張りと圧縮の応力を与えることで、最終的に
仕上げた膜に応力を残すことが可能である。膜の内部応
力の大きさは2枚の基板のはじめの厚さと残す膜の厚さ
および当初の応力とから決まる。本発明ではこのような
接合を行うために基板を弾性的に変形させたときの表面
の長さの変化を利用する。基板の厚み方向の機械的な外
力を与えて、基板をその表面が凸になるように変形させ
ると表面は湾曲の程度に応じて伸長する。もう1枚の基
板をこれに重ねると、表面同士が鏡面であれば互いに吸
着し合い、重ねた基板は先に変形させた基板に沿って凹
に変形する。このとき重ねた基板に作用する外力はその
厚み方向のみであるからこの基板の表面は圧縮を受けて
いる。ここで当初の機械的な力を解除すれば基板に応力
を残すことができる。このとき各基板には引っ張りと圧
縮の応力がその厚さに応じて存在し、この分布は接合一
体化の熱処理後も保存される。一方の基板を薄膜化して
目的の基板に仕上げると、応力は薄膜に集中し、膜厚が
基板全厚さに対して充分小さい場合は、仮接合時の基板
表面の伸縮量に相当する応力が導入される。膜に導入さ
れる応力は基板の最初の伸縮量、すなわち仮接合時の基
板の湾曲の程度で決まるから応力の制御は容易である。
また膜の厚みが無視できない場合でも、最終膜厚、基板
厚さおよび導入すべき応力の大きさから、仮接合時に必
要な湾曲は容易に設計できる。
[Means for Solving the Problem] According to experiments, the internal stress of the film of the manufactured substrate is determined by the state at the time of temporary bonding, and there is almost no relaxation of stress in the subsequent heat treatment and processing steps for thinning. . That is, by applying tensile and compressive stress to each of the temporarily bonded substrates, the stress can be left in the finally finished film. The magnitude of the internal stress of the film is determined by the initial thickness of the two substrates, the thickness of the remaining film, and the initial stress. In the present invention, a change in the surface length when the substrates are elastically deformed is used to perform such bonding. When a mechanical external force in the thickness direction of the substrate is applied to deform the substrate so that its surface becomes convex, the surface expands according to the degree of curvature. When another substrate is placed on top of this, if the surfaces are mirror surfaces, they will stick to each other and the stacked substrates will be deformed concavely along the previously deformed substrate. At this time, the external force acting on the stacked substrates is only in the thickness direction, so that the surface of the substrate is compressed. Here, if the initial mechanical force is released, stress can be left on the substrate. At this time, tensile and compressive stresses are present in each substrate depending on its thickness, and this distribution is preserved even after the heat treatment for joining and unifying. When one of the substrates is thinned to the target substrate, the stress concentrates on the thin film, and if the film thickness is sufficiently smaller than the total thickness of the substrate, the stress equivalent to the expansion and contraction of the substrate surface at the time of temporary bonding is generated. be introduced. Since the stress introduced into the film is determined by the amount of initial expansion and contraction of the substrate, that is, the degree of bending of the substrate during temporary bonding, it is easy to control the stress.
Further, even when the film thickness cannot be ignored, the curvature required for temporary bonding can be easily designed from the final film thickness, the substrate thickness, and the magnitude of the stress to be introduced.

【0005】[0005]

【作用】本方法との比較のため、従来の方法で製作した
場合に張り合わせ基板の膜の内部応力を概算する。まず
材料の熱膨張によって膜に導入される応力を見積もる。
モデルとして径100mm、厚さ500μm のシリコン基
板2枚に各々厚さ0.5μm の熱酸化膜を形成しこれら
を接合して一方を厚さ1μm の膜に仕上げたSOI構造
を考える。用いる基板の表面は完全に平坦で、酸化温度
(10000C)では応力はないものと仮定する。このと
き膜の内部応力は引っ張りで、その大きさは2.9X1
6 dyn/cm2 と見積もられる。次に基板表面の凸凹によ
って膜に導入される応力を見積もる。モデルとして径1
00mm、厚さ500μm で表面が曲率半径10m の凸状
の基板に、完全に平坦な表面を持つ十分に厚い基板を接
合しこれを厚さ1μm の膜に仕上げた構造を考える。こ
の膜の内部応力は5,5X106 dyn/cm2 と見積もられ
る。ここで本方法により導入しうる応力の大きさを示
す。径100mm、厚さ500μm の平坦な基板を2枚用
意し、1枚を曲率半径R(cm)に湾曲させる。これにも
う1枚の基板を沿わせて接合し、先に湾曲させた側の基
板を薄膜化して厚さ1μm の膜に仕上げるとすると、膜
の内部応力は引っ張りでその大きさは、6.6X1010
/Rdyn/ cm2 と計算される。たとえば湾曲の曲率半径
を70m とすると膜には約107 dyn/cm2 の引っ張り応
力が導入される。これは膜全面にわたって引っ張り応力
を残すに充分な値である。
For comparison with this method, the internal stress of the film of the bonded substrate when the conventional method is used will be estimated. First, the stress introduced into the film by the thermal expansion of the material is estimated.
As an model, consider an SOI structure in which two silicon substrates each having a diameter of 100 mm and a thickness of 500 μm are formed with a thermal oxide film having a thickness of 0.5 μm and bonded to each other to finish one of them into a film having a thickness of 1 μm. It is assumed that the surface of the substrate used is perfectly flat and there is no stress at the oxidation temperature (1000 0 C). At this time, the internal stress of the film is tensile and its magnitude is 2.9X1.
It is estimated to be 0 6 dyn / cm 2 . Next, the stress introduced into the film by the unevenness of the substrate surface is estimated. Diameter 1 as a model
Consider a structure in which a sufficiently thick substrate having a completely flat surface is bonded to a convex substrate having a radius of curvature of 10 m and a surface of 00 mm and a thickness of 500 μm, and a film having a thickness of 1 μm is finished. The internal stress of this film is estimated to be 5,5 × 10 6 dyn / cm 2 . Here, the magnitude of stress that can be introduced by this method is shown. Two flat substrates having a diameter of 100 mm and a thickness of 500 μm are prepared, and one is curved to have a radius of curvature R (cm). If another substrate is joined along this, and the curved substrate is thinned to a film with a thickness of 1 μm, the internal stress of the film is tensile and its size is 6. 6 x 10 10
Calculated as / Rdyn / cm 2 . For example, when the radius of curvature is 70 m, a tensile stress of about 10 7 dyn / cm 2 is introduced into the film. This is a value sufficient to leave tensile stress over the entire surface of the film.

【0006】[0006]

【実施例】(実施例1)本発明による実施例を示す。 1)径100mm、厚さ500μm のシリコンウエハを2
枚用意し、各々表面に厚さ0,5μm の熱酸化膜を形成
した。 2)表面を曲率半径50m の凸状に形成した真空吸着式
プレートに基板を吸着して変形させ、この上にもう1 枚
の基板を重ね仮接合した。 3)真空吸着を解除し応力による剥離がないことを確認
したうえで、これを熱処理炉に挿入し窒素雰囲気中、1
100℃、2時間の熱処理を行った。 4)この基板を先に変形させた基板の側から研磨し厚さ
2μm の膜を残した。 5)比較のため従来法で作製した試料を用意し、両者を
支持基板の側から徐々に薄くしていったところいずれも
膜側が凸に変形した。この変形はシリコンと熱酸化膜の
熱膨張係数の差に起因して生じる酸化膜内の圧縮応力に
よるものである。変形の度合いは本方法により製作した
試料の方が明らかに小さく、膜に引っ張りの応力が入っ
ていたことが確認された。
EXAMPLES Example 1 An example according to the present invention will be described. 1) 2 silicon wafers with a diameter of 100 mm and a thickness of 500 μm
One piece was prepared, and a thermal oxide film having a thickness of 0.5 μm was formed on each surface. 2) The substrate was adsorbed and deformed by a vacuum adsorption type plate whose surface had a convex shape with a radius of curvature of 50 m, and another substrate was overlaid and temporarily bonded. 3) After releasing the vacuum adsorption and confirming that there is no peeling due to stress, insert this into a heat treatment furnace and place it in a nitrogen atmosphere for 1
Heat treatment was performed at 100 ° C. for 2 hours. 4) This substrate was polished from the side of the substrate that was previously deformed to leave a film having a thickness of 2 μm. 5) For comparison, a sample prepared by the conventional method was prepared, and both were gradually thinned from the side of the supporting substrate. This deformation is due to compressive stress in the oxide film caused by the difference in thermal expansion coefficient between silicon and the thermal oxide film. The degree of deformation was obviously smaller in the sample produced by this method, and it was confirmed that the film had tensile stress.

【0007】(実施例2) 1) 径100mm、厚さ500μm のシリコンウエハを4
枚用意し、各々表面に厚さ0.1μm の熱酸化膜を形成
した。 2)実施例1の2)、3)の要領で2組の接合基板a、
bを製作し、aについては先に変形させた基板側を、b
については反対側の基板をそれぞれ薄膜化して厚さ5μ
m のSOI膜を残した。 3)これらの基板の支持基板の一部をウエットエッチン
グにより除去して、約3mm角のSOIダイヤフラムを形
成して観察したところ、aでは膜がピンと張ったままで
あるのに対してbでは膜がたるんでいた。試料の製作法
とこの結果を勘案すると、aの基板では膜の内部応力は
引っ張りであり、bの基板では膜の内部応力は圧縮であ
ると結論される。
(Embodiment 2) 1) Four silicon wafers having a diameter of 100 mm and a thickness of 500 μm are prepared.
One sheet was prepared, and a thermal oxide film having a thickness of 0.1 μm was formed on each surface. 2) Two sets of bonded substrates a, as in 2) and 3) of the first embodiment,
b is manufactured, and for a, the substrate side that has been previously deformed is
For the other side, thin the substrate on the opposite side to a thickness of 5μ.
An m 2 SOI film was left. 3) A part of the supporting substrate of these substrates was removed by wet etching, and an SOI diaphragm of about 3 mm square was formed and observed. As a result, the film remained taut in a, whereas the film in b did not. I was slack. Considering the method of manufacturing the sample and this result, it is concluded that the internal stress of the film is tensile on the substrate a and the internal stress of the film is compressive on the substrate b.

【0008】[0008]

【発明の効果】本発明によれば、張り合わせ法により製
作する基板の膜内部に一様に圧縮あるいは引っ張りの応
力を任意に導入することが可能となる。
According to the present invention, it is possible to uniformly introduce a compressive or tensile stress into the inside of a film of a substrate manufactured by a bonding method.

【図面の簡単な説明】[Brief description of drawings]

【図1】従来法による張り合わせ基板の製作工程を示す
説明図。
FIG. 1 is an explanatory view showing a manufacturing process of a bonded substrate by a conventional method.

【図2】本発明の実施例を説明する製作工程図。FIG. 2 is a manufacturing process diagram illustrating an embodiment of the present invention.

【手続補正書】[Procedure amendment]

【提出日】平成3年12月26日[Submission date] December 26, 1991

【手続補正1】[Procedure Amendment 1]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】特許請求の範囲[Name of item to be amended] Claims

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【特許請求の範囲】[Claims]

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 表面を鏡面に仕上げた2枚の半導体素子
形成用基板を、その鏡面同士を接触させ仮接合した後、
熱処理して接合一体化させる直接接合法において、仮接
合にさいして、一方の半導体素子形成用う 基板を接合
面が凸になるように湾曲させ他方の基板をこれに沿わせ
て重ね合わせることで、内部に応力を導入せしめること
を特徴とする半導体基板の接合方法。
1. After two mirror-finished substrates for semiconductor element formation are brought into contact with each other and the mirror-finished surfaces are temporarily joined,
In the direct bonding method in which heat treatment is performed to bond and integrate, during temporary bonding, one of the semiconductor element forming substrates is curved so that the bonding surface is convex and the other substrate is superposed along it. A method for joining semiconductor substrates, wherein stress is introduced into the inside.
JP32997591A 1991-11-19 1991-11-19 Bonding method for semiconductor substrates Pending JPH06196377A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32997591A JPH06196377A (en) 1991-11-19 1991-11-19 Bonding method for semiconductor substrates

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32997591A JPH06196377A (en) 1991-11-19 1991-11-19 Bonding method for semiconductor substrates

Publications (1)

Publication Number Publication Date
JPH06196377A true JPH06196377A (en) 1994-07-15

Family

ID=18227369

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32997591A Pending JPH06196377A (en) 1991-11-19 1991-11-19 Bonding method for semiconductor substrates

Country Status (1)

Country Link
JP (1) JPH06196377A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002536843A (en) * 1999-02-10 2002-10-29 コミツサリア タ レネルジー アトミーク Multilayer structure with internal stress control and method of manufacturing the same
JP2006509377A (en) * 2002-12-09 2006-03-16 コミサリヤ・ア・レネルジ・アトミク Method of manufacturing a structure under stress configured to be separated
JP2008547219A (en) * 2005-06-27 2008-12-25 ザ リージェンツ オブ ザ ユニバーシティ オブ カリフォルニア A method for making distorted crystals without dislocations

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002536843A (en) * 1999-02-10 2002-10-29 コミツサリア タ レネルジー アトミーク Multilayer structure with internal stress control and method of manufacturing the same
JP4889154B2 (en) * 1999-02-10 2012-03-07 コミッサリア ア レネルジー アトミーク エ オ ゼネルジ ザルタナテイヴ Method for producing multilayer structure
JP2006509377A (en) * 2002-12-09 2006-03-16 コミサリヤ・ア・レネルジ・アトミク Method of manufacturing a structure under stress configured to be separated
JP2008547219A (en) * 2005-06-27 2008-12-25 ザ リージェンツ オブ ザ ユニバーシティ オブ カリフォルニア A method for making distorted crystals without dislocations

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