JPS61145839A - Semiconductor wafer bonding method and bonding jig - Google Patents

Semiconductor wafer bonding method and bonding jig

Info

Publication number
JPS61145839A
JPS61145839A JP26881384A JP26881384A JPS61145839A JP S61145839 A JPS61145839 A JP S61145839A JP 26881384 A JP26881384 A JP 26881384A JP 26881384 A JP26881384 A JP 26881384A JP S61145839 A JPS61145839 A JP S61145839A
Authority
JP
Japan
Prior art keywords
semiconductor wafer
wafer
jig
bonding
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP26881384A
Other languages
Japanese (ja)
Other versions
JPH0560250B2 (en
Inventor
Masaru Shinpo
新保　優
Kiyoshi Fukuda
潔 福田
Kazuyoshi Furukawa
和由 古川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP26881384A priority Critical patent/JPS61145839A/en
Publication of JPS61145839A publication Critical patent/JPS61145839A/en
Publication of JPH0560250B2 publication Critical patent/JPH0560250B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67092—Apparatus for mechanical treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment

Abstract

PURPOSE:To easily realize the bonding without remaining bubbles at the inside by deflecting at least one semiconductor waferin such a condition that the center area of grinding surface is convexed and bonding the convexed surface with the other semiconductor wafer. CONSTITUTION:The surfaces for bonding of two sheets of semiconductor wafers 11, 12 are respectively ground as the specular surface. A jig 13 is curved by machining so that the center area is convexed and a semiconductor wafer 11 is supported by this jig 1 so that the ground surface is convexed at the center area. The semiconductor wafer 11 thus supported is placed in contact with the other semiconductor wafer 12 from the center area of convexed portion and the holding of semiconductor wafer 11 by the jig 13 is released. Thereby, the semiconductor wafers 11, 12 are bonded. According to this method, two sheets of semiconductor wafers 11, 12 can be reliably bonded at the entire surface without remaining gas and rigid bonded wafer can be obtained.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、シリコンなどの半導体ウェーハ同士を直接接
着させる方法およびその方法に使用する冶具に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for directly bonding semiconductor wafers such as silicon to each other, and a jig used in the method.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

鏡面研磨されたシリコンなどの二枚の半導体ウェーハを
、その研磨面同士を清浄な条件下で接触させると強固な
接合体ウェーハが得られる。この方法は、ウェーハ間に
接着材等の異種物質を介在させる必要がないため、その
後の高ｍ処理や各種化学処理が自由にでき、またｐｎ接
合や誘電体埋め込みも簡便にできる、といった利点を有
する。When two mirror-polished semiconductor wafers, such as silicon, are brought into contact with their polished surfaces under clean conditions, a strong bonded wafer can be obtained. This method does not require the interposition of different materials such as adhesives between the wafers, so it has the advantage of allowing subsequent high-m processing and various chemical treatments to be carried out freely, as well as simplifying p-n junctions and dielectric embedding. have

ところでこの方法で半導体ウェーハを接着させる場合、
ウェーハの反り等のため周辺部が先に接着し、接合部に
気泡が取り残されることがしばしばある。この対策とし
て、真空中で接着することが考えられる。しかしこれで
は、装置が大掛りなものとなる。By the way, when bonding semiconductor wafers using this method,
Due to warping of the wafer, the peripheral portion often adheres first and air bubbles are often left behind at the bonded portion. As a countermeasure to this problem, bonding in a vacuum may be considered. However, this requires a large-scale device.

〔発明の目的〕[Purpose of the invention]

本発明は、半導体ウェーハ同士を内部に気泡を残すこと
なく簡便に接着する方法およびその方法に使用する治具
を提供することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for simply bonding semiconductor wafers together without leaving any air bubbles inside, and a jig for use in the method.

〔発明の概要〕[Summary of the invention]

本発明の方法は、鏡面研磨された二枚の半導体ウェーハ
の研磨面同士を接着させるに当たって、少なくとも一方
の半導体ウェー八をその研磨南中央部が凸型となるよう
にたわませた状態でその凸型面を他方の半導体ウェーハ
に接触させて、両ウェーハの接着を行なうことを特徴と
する。In the method of the present invention, when bonding the polished surfaces of two mirror-polished semiconductor wafers to each other, at least one of the semiconductor wafers is bent in such a manner that the polished south central portion thereof is convex. It is characterized in that the convex surface is brought into contact with the other semiconductor wafer to bond both wafers together.

本発明の冶具は、上記のように一方に半導体研摩面中央
部を凸型にたわませて保持するためのものであり、表面
中央部が凸型となるようにテーパ面または曲面成型され
その表面に開口する排気孔を有する基台と、この基台に
重ねられ、半導体ウェー八が載置される面の外周部に溝
が形成されかつその溝に沿って前記基台の排気孔と連通
する複数個の排気孔が形成された弾性体からなるチャッ
クを備える。そしてチャック上に載せられた半導体ウェ
ー八を、チャックの排気孔および基台の排気孔を介して
真空吸引することにより、チャックと共に半導体ウェー
八を基台の表面形状を反映して中央部が凸型となる状態
で保持するようにしたものである。As described above, the jig of the present invention is for holding the central part of the semiconductor polishing surface in a convex shape on one side, and has a tapered or curved surface formed so that the central part of the surface is convex. A base having an exhaust hole opening on the surface, and a groove formed on the outer periphery of the surface on which the semiconductor wafer is placed, stacked on the base, and communicating with the exhaust hole of the base along the groove. The chuck is made of an elastic body and has a plurality of exhaust holes formed therein. Then, by vacuum suctioning the semiconductor wafer placed on the chuck through the exhaust hole of the chuck and the exhaust hole of the base, the central part of the semiconductor wafer is raised to reflect the surface shape of the base. It is designed to be held as a mold.

〔発明の効果〕〔Effect of the invention〕

本発明の方法および冶具を用いれば、二枚の半導体ウェ
ー八同士を内部に気泡が残らないように接着して強固な
接合体ウェーハを得ることができる。しかも真空中での
接着と異なり、大掛りな装置を要せず、極めて簡便に接
着を行なうことができる。By using the method and jig of the present invention, it is possible to obtain a strong bonded wafer by bonding two semiconductor wafers together without leaving any air bubbles inside. Moreover, unlike adhesion in a vacuum, the adhesion can be performed extremely easily without the need for large-scale equipment.

〔発明の実施例〕[Embodiments of the invention]

以下本発明の詳細な説明する。 The present invention will be explained in detail below.

第１図（ａ）〜（Ｃ）は−実施例の方法を説明するため
の図である。これらの図において、１１゜１２は接着す
べき二枚の半導体ウェーハであり、それぞれの接着すべ
き面は鏡面研磨されている。FIGS. 1(a) to 1(C) are diagrams for explaining the method of the embodiment. In these figures, reference numerals 11 and 12 indicate two semiconductor wafers to be bonded, and the surfaces of each to be bonded are mirror-polished.

１３は一方の半導体ウェーハ１１を保持する冶具であり
、１４は他方の半導体ウェーハ１２を平坦に支持する支
持台である。第１図（ａ）に示すように、治具１３はそ
の表面が中央部が凸型となるように曲面加工されており
、半導体ウェーハ１１はこの治具１３により研磨面が中
央部凸型となるように保持される。このように保持され
た半導体ウェーハ１１を、第１図（ｂ）に示すように他
方の半導体ウェーハ１２に凸型の中央部から接触させ、
治具１３による半導体ウェーハ１１の保持を解除するこ
とにより、第１図（Ｃ）に示すように、半導体ウェーハ
１１．１２を接着させる。13 is a jig for holding one semiconductor wafer 11, and 14 is a support base for flatly supporting the other semiconductor wafer 12. As shown in FIG. 1(a), the surface of the jig 13 is curved so that the central part is convex, and the semiconductor wafer 11 is polished by this jig 13 so that the central part is convex. It is maintained as follows. The semiconductor wafer 11 held in this way is brought into contact with the other semiconductor wafer 12 from the center of the convex shape, as shown in FIG. 1(b),
By releasing the holding of the semiconductor wafer 11 by the jig 13, the semiconductor wafers 11 and 12 are bonded together as shown in FIG. 1(C).

この方法によれば、二枚の半導体ウェーハ１１゜１２を
残留ガスなしに全面確実に接着させて、強固な接合体ウ
ェー八を得ることができる。According to this method, two semiconductor wafers 11 and 12 can be reliably bonded over the entire surface without residual gas, and a strong bonded wafer can be obtained.

第２図（ａ）（ｂ）は、第１因で示したウェーハ保持治
具１３の具体的な構成例を示す。（ａ）は平面図であり
、（ｂ）はそのＡ−Ａ−断面図である。２４は金属等で
つくった基台であり、表面中央部が凸型となるように曲
面加工されており、表面に開口する排気孔２５が形成さ
れている。FIGS. 2(a) and 2(b) show specific configuration examples of the wafer holding jig 13 shown in the first factor. (a) is a plan view, and (b) is its AA cross-sectional view. Reference numeral 24 denotes a base made of metal or the like, the surface of which is curved so as to have a convex central portion, and has an exhaust hole 25 opening in the surface.

２１は基台２４上に被せられる。半導体ウェー八を載置
するためのラバー・チャックである。このラバー・チャ
ック２１の表面にはその外周部に半導体ウェー八を保持
するための溝２２が形成され、この溝２２に沿って複数
の排気孔２３が形成されている。基台２４の下に排気管
２６が設けられており、この排気管２６を介してラバー
・チャック２１上に載置された半導体ウェーハを真空吸
引するようになっている。21 is placed on the base 24. This is a rubber chuck for mounting semiconductor wafers. A groove 22 for holding a semiconductor wafer is formed on the outer periphery of the surface of the rubber chuck 21, and a plurality of exhaust holes 23 are formed along the groove 22. An exhaust pipe 26 is provided below the base 24, and the semiconductor wafer placed on the rubber chuck 21 is vacuum-suctioned through the exhaust pipe 26.

第３図はこの冶具１３を用いて半導体ウェーハ１１を保
持した様子を示している。図示のように、排気管２６を
介して真空吸引することにより、排気孔２５．２３を介
して半導体ウェーハ１１の外周部が引張られてラバー・
チャック２１が基台２４の表面形状に従ってたわみ、こ
の結果半導体ウェーハ１１は中央部が凸型になった状態
で保持される。FIG. 3 shows how the semiconductor wafer 11 is held using this jig 13. As shown in the figure, by vacuum suction through the exhaust pipe 26, the outer circumference of the semiconductor wafer 11 is pulled through the exhaust hole 25.23, and the rubber
The chuck 21 bends according to the surface shape of the base 24, and as a result, the semiconductor wafer 11 is held in a convex state at the center.

このようにして保持した半導体ウェーハ１１を、第１図
で説明したようにもう一方の半導体ウェーハ１２に接触
させ、ラバー・チャック２１内に空気等を少しずつ導入
して半導体ウェーハ１１のたわみを徐々に回復させる。The semiconductor wafer 11 held in this way is brought into contact with the other semiconductor wafer 12 as explained in FIG. to recover.

これにより、接着面は中央部から周辺部に向かって広が
り、気泡を取り込むことなくウェーハ１１．１２を接着
することができる。As a result, the bonding surface spreads from the center toward the periphery, making it possible to bond the wafers 11 and 12 without introducing air bubbles.

本発明は上記実施例に限られない。例えば第１図の方法
では、半導体つＩ−ハ１２は平坦に支持したが、これも
半導体ウェーハ１１と同様に中央部が凸型となるように
たわませて保持してもよい。The present invention is not limited to the above embodiments. For example, in the method shown in FIG. 1, the semiconductor wafer 12 is supported flatly, but like the semiconductor wafer 11, it may also be held in a bent manner so that the central portion thereof is convex.

また第１図において、支持台１４をゴムなどの弾性体と
し、（ｂ）の状態から治具１３を押しつける荷重を増す
ことにより両ウェーハ１１．１２の接触面積を徐々に増
していく、という方法をとってもよい。さらに本発明の
方法において、半導体ウェーハをたわませるには、例え
ばウェーハの周辺を機械的に保持し中央部を押すことに
よっても可能である。In addition, in FIG. 1, the support table 14 is made of an elastic body such as rubber, and the contact area between both wafers 11 and 12 is gradually increased by increasing the load pressing the jig 13 from the state shown in (b). You can also take Further, in the method of the present invention, the semiconductor wafer can be bent by, for example, mechanically holding the wafer around the wafer and pushing the central part.

また第２図のウェーハ保持治具において、ラバー・チャ
ック２１は他の弾性材料を用いて構成することができる
。また基台２４の表面は必ずしも曲面でなくてもよく、
例えば中央部が凸型となるテーパ面であってもよい。Furthermore, in the wafer holding jig shown in FIG. 2, the rubber chuck 21 can be constructed using other elastic materials. Furthermore, the surface of the base 24 does not necessarily have to be a curved surface,
For example, the tapered surface may have a convex central portion.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（ａ）〜（Ｃ）は本発明の一実施例の方法を説明
するための図、第２図（ａ）（ｂ）はその方法に使用し
たウェーハ保持治具を示す図、第３図はこの保持冶具に
よりウェーハを保持した様子を示す図である。 １１．１２・・・半導体ウェーハ、１３・・・ウェーハ
保持治具、１４・・・ウェーハ支持台、２１・・・ラバ
ー・チャック、２２・・・溝、２３・・・排気孔、２４
・・・基台、２５・・・排気孔、２６・・・排気管。 出願人代理人　弁理士　鈴江武彦 ｋｐ　■ 七 ミ （・ オー１１ 〆１１FIGS. 1(a) to (C) are diagrams for explaining a method according to an embodiment of the present invention, FIGS. 2(a) and (b) are diagrams showing a wafer holding jig used in the method, and FIGS. FIG. 3 is a diagram showing how the wafer is held by this holding jig. 11.12... Semiconductor wafer, 13... Wafer holding jig, 14... Wafer support stand, 21... Rubber chuck, 22... Groove, 23... Exhaust hole, 24
...Base, 25...Exhaust hole, 26...Exhaust pipe. Applicant's agent Patent attorney Takehiko Suzue KP ■ Nanami (・O11 〆11

Claims (2)

【特許請求の範囲】[Claims] （１）鏡面研磨された二枚の半導体ウェーハの研磨面同
士を清浄な条件下で直接接着させて接合体ウェーハを得
る方法において、少なくとも一方の半導体ウェーハの研
磨面を、中央部が凸型となるようにたわませて他方の半
導体ウェーハの研磨面に接触させて接着を行なうことを
特徴とする半導体ウェーハの接着方法。(1) In a method of obtaining a bonded wafer by directly bonding the polished surfaces of two mirror-polished semiconductor wafers together under clean conditions, the polished surfaces of at least one of the semiconductor wafers are shaped so that the central portion thereof is convex. 1. A method for bonding semiconductor wafers, the method comprising bonding a semiconductor wafer by bending the wafer so that the wafer is bent so as to make contact with the polished surface of the other semiconductor wafer. （２）鏡面研磨された二枚の半導体ウェーハの研磨面同
士を清浄な条件下で直接接着させて接合体ウェーハを得
るための治具であって、表面中央部が凸型となるように
テーパ面または曲面成型され、その表面に開口する排気
孔を有する基台と、この基台に重ねられ、半導体ウェー
ハが載置される面の外周部に溝が形成されかつその溝に
沿って前記基台の排気孔と連通する複数個の排気孔が形
成された弾性体からなるチャックとを備え、前記チャッ
ク上に載せられた半導体ウェーハを、チャックの排気孔
および基台の排気孔を介して真空吸引してその中央部が
凸型となる状態で保持するようにしたことを特徴とする
半導体ウェーハの接着治具。(2) A jig for obtaining a bonded wafer by directly bonding the polished surfaces of two mirror-polished semiconductor wafers together under clean conditions, and the jig is tapered so that the center of the surface is convex. A base that is molded into a surface or a curved surface and has an exhaust hole opening on its surface, and a groove is formed on the outer periphery of the surface on which the semiconductor wafer is placed and stacked on the base, and the base is placed along the groove. A chuck made of an elastic body is provided with a plurality of exhaust holes communicating with the exhaust hole of the base, and the semiconductor wafer placed on the chuck is vacuumed through the exhaust hole of the chuck and the exhaust hole of the base. A bonding jig for semiconductor wafers, characterized in that the jig is adapted to hold a semiconductor wafer in a convex state by suction.
JP26881384A 1984-12-20 1984-12-20 Semiconductor wafer bonding method and bonding jig Granted JPS61145839A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26881384A JPS61145839A (en) 1984-12-20 1984-12-20 Semiconductor wafer bonding method and bonding jig

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26881384A JPS61145839A (en) 1984-12-20 1984-12-20 Semiconductor wafer bonding method and bonding jig

Publications (2)

Publication Number Publication Date
JPS61145839A true JPS61145839A (en) 1986-07-03
JPH0560250B2 JPH0560250B2 (en) 1993-09-01

Family

ID=17463609

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26881384A Granted JPS61145839A (en) 1984-12-20 1984-12-20 Semiconductor wafer bonding method and bonding jig

Country Status (1)

Country Link
JP (1) JPS61145839A (en)

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6271215A (en) * 1985-09-25 1987-04-01 Toshiba Corp Wafer jointing apparatus
JPH01133341A (en) * 1987-11-19 1989-05-25 Hitachi Ltd Manufacture of semiconductor device and manufacturing equipment therefor
JPH01169917A (en) * 1987-12-24 1989-07-05 Fujitsu Ltd Bonding process of wafer
JPH023266A (en) * 1987-12-28 1990-01-08 Motorola Inc Bipolar semiconductor device having conductive recombination layer
KR20030052986A (en) * 2001-12-21 2003-06-27 에섹 트레이딩 에스에이 Pick-up tool for mounting semiconductor chips
FR2860178A1 (en) * 2003-09-30 2005-04-01 Commissariat Energie Atomique Stacked hetero-structure plates separating method for forming thin film semiconductor, involves subjecting structure to bending force applied on all or part of structure for separating structure into two along desired separation plane
KR100499317B1 (en) * 2001-03-21 2005-07-04 캐논 가부시끼가이샤 Semiconductor device
US7153759B2 (en) 2004-04-20 2006-12-26 Agency For Science Technology And Research Method of fabricating microelectromechanical system structures
US7192841B2 (en) 2002-04-30 2007-03-20 Agency For Science, Technology And Research Method of wafer/substrate bonding
US7259466B2 (en) 2002-12-17 2007-08-21 Finisar Corporation Low temperature bonding of multilayer substrates
US7361593B2 (en) 2002-12-17 2008-04-22 Finisar Corporation Methods of forming vias in multilayer substrates
WO2010055730A1 (en) * 2008-11-14 2010-05-20 東京エレクトロン株式会社 Bonding apparatus and bonding method
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
US7958628B2 (en) 2003-12-31 2011-06-14 Stats Chippac, Ltd. Bonding tool for mounting semiconductor chips
JP5136411B2 (en) * 2006-06-29 2013-02-06 株式会社ニコン Wafer bonding equipment
WO2014156987A1 (en) 2013-03-26 2014-10-02 芝浦メカトロニクス株式会社 Bonding device and method for manufacturing bonded substrate
WO2015046243A1 (en) 2013-09-25 2015-04-02 芝浦メカトロニクス株式会社 Suction stage, bonding device, and method for manufacturing bonded substrate
CN110168711A (en) * 2017-09-21 2019-08-23 Ev 集团 E·索尔纳有限责任公司 The device and method for engaging substrate

Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH044743B2 (en) * 1985-09-25 1992-01-29
JPS6271215A (en) * 1985-09-25 1987-04-01 Toshiba Corp Wafer jointing apparatus
JPH01133341A (en) * 1987-11-19 1989-05-25 Hitachi Ltd Manufacture of semiconductor device and manufacturing equipment therefor
JPH01169917A (en) * 1987-12-24 1989-07-05 Fujitsu Ltd Bonding process of wafer
JPH023266A (en) * 1987-12-28 1990-01-08 Motorola Inc Bipolar semiconductor device having conductive recombination layer
KR100499317B1 (en) * 2001-03-21 2005-07-04 캐논 가부시끼가이샤 Semiconductor device
KR20030052986A (en) * 2001-12-21 2003-06-27 에섹 트레이딩 에스에이 Pick-up tool for mounting semiconductor chips
US7192841B2 (en) 2002-04-30 2007-03-20 Agency For Science, Technology And Research Method of wafer/substrate bonding
US7361593B2 (en) 2002-12-17 2008-04-22 Finisar Corporation Methods of forming vias in multilayer substrates
US7259466B2 (en) 2002-12-17 2007-08-21 Finisar Corporation Low temperature bonding of multilayer substrates
FR2860178A1 (en) * 2003-09-30 2005-04-01 Commissariat Energie Atomique Stacked hetero-structure plates separating method for forming thin film semiconductor, involves subjecting structure to bending force applied on all or part of structure for separating structure into two along desired separation plane
EP1520669A1 (en) * 2003-09-30 2005-04-06 Commissariat A L'energie Atomique A method for separating plates which are bonded with each other and form a piled structure
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