JPS6099538A - Pin chuck - Google Patents

Pin chuck

Info

Publication number
JPS6099538A
JPS6099538A JP21744884A JP21744884A JPS6099538A JP S6099538 A JPS6099538 A JP S6099538A JP 21744884 A JP21744884 A JP 21744884A JP 21744884 A JP21744884 A JP 21744884A JP S6099538 A JPS6099538 A JP S6099538A
Authority
JP
Japan
Prior art keywords
chuck
peak
wafer
workpiece
connecting pipe
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21744884A
Other languages
Japanese (ja)
Inventor
アーマー・ピー・ニユーカーマンズ
グラハム・ジエイ・サイダル
ジヨセフ・ダブリユ・フランクリン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Varian Medical Systems Inc
Original Assignee
Varian Associates Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Varian Associates Inc filed Critical Varian Associates Inc
Publication of JPS6099538A publication Critical patent/JPS6099538A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70691—Handling of masks or workpieces
    • G03F7/707—Chucks, e.g. chucking or un-chucking operations or structural details
    • G03F7/70708—Chucks, e.g. chucking or un-chucking operations or structural details being electrostatic; Electrostatically deformable vacuum chucks
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70691—Handling of masks or workpieces
    • G03F7/707—Chucks, e.g. chucking or un-chucking operations or structural details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6838—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping with gripping and holding devices using a vacuum; Bernoulli devices

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Jigs For Machine Tools (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔従来の技術と発明の概要〕 光食刻処理をしている間、半導体ウェファが正確に位置
付けるチャックに竪固に取り付けられる。DETAILED DESCRIPTION OF THE PRIOR ART AND SUMMARY OF THE INVENTION During photolithography, a semiconductor wafer is rigidly mounted on a precisely positioned chuck.

最適の結果を得るために、ウェファがチャックに堅固に
取り付けられ、そのチャックが平坦な取付は表面をウェ
ファに提供することが重要である。For optimal results, it is important that the wafer is firmly attached to the chuck and that the chuck provides a flat mounting surface to the wafer.

典型的な従来技術のビンチャックが米国特許第４．２１
３，６９８号（フイルクヨン等、１９８０年７月２２日
発行）に開示されている０第１及び第２図に示すように
、このような従来技術のチャックは、真空源を利用し、
ウェファを多数の金属製支持ポストへと吸引する。この
従来技術のチャックは製造コストが高く、ウェファは、
その金属製チ、ヤツク及び半導体ウェファが異なる熱膨
張係数を有することからひずみを与えることになる。更
に、ウェファ取付は表面は金属であるから、冷間圧接や
次の拡散チェンバの汚染が生じる。A typical prior art bottle chuck is disclosed in U.S. Patent No. 4.21.
No. 3,698 (Filkjon et al., published July 22, 1980), such prior art chucks utilize a vacuum source, as shown in FIGS.
The wafer is sucked onto a number of metal support posts. This prior art chuck is expensive to manufacture and the wafer
The metal chips, jackets, and semiconductor wafers have different coefficients of thermal expansion, which imparts strain. Additionally, the wafer attachment has a metal surface, resulting in cold welding and contamination of the subsequent diffusion chamber.

本発明の図示した好適実施例に従うと、真空ピンチャツ
クは、一体の単一（ｍｏｎｏｌｔｈ這Ｃ）ケイ素から製
造される。チャックの表面は研磨され、環状外側密封表
面が平坦なピーク及び谷のある内側領域を囲むようにエ
ツチングされる。内側領域を貫通してあけられた穴によ
って、真空装置を利用できる゛。処理される半導体ウェ
ファの接触は、環状表面及び内側領域のピークによって
のみなされる。谷を貫通する空気流通路によって、ウェ
ファを平坦なピーク及び環状密封表面へとしっかりと真
空吸引することができる。取付は表面の領域（環状密封
表面及びピークの先端から成る領域）がピンチャツク表
面領域のはぼ４％たらずなので、ウェファと取付は表面
との間に小砂などの異物が入シ込む確率は低い。更に、
チャック及びウェファが同じ材質から製造され得ること
から、ウェファとチャック熱膨張係数は同じになる。更
にまた、チャックとウェファの間の冷間圧接は、壊れた
ピークがばりを付けることなく破砕されるので、チーヤ
ツクの平坦に影響を与えることがない。更に、チャック
のウェファへの冷間圧接が後の処理工程にお−て使用す
る拡散チェンバの汚染を受け得ない。というのはチャッ
ク材が不活性であるからである。In accordance with the illustrated preferred embodiment of the invention, the vacuum pinch chuck is fabricated from a single piece of monolithic silicon. The surface of the chuck is polished and etched such that an annular outer sealing surface surrounds the flat peak and valley inner region. A hole drilled through the inner region allows access to a vacuum device. Contact of the semiconductor wafer being processed is made only by the annular surface and the peak of the inner region. Air flow passages through the valleys allow the wafer to be firmly vacuumed to the flat peak and annular sealing surface. Since the mounting surface area (the area consisting of the annular sealing surface and the tip of the peak) is less than 4% of the pinch surface area, there is a low probability that foreign matter such as small sand will enter between the wafer and the mounting surface. . Furthermore,
Since the chuck and wafer can be manufactured from the same material, the wafer and chuck thermal expansion coefficients will be the same. Furthermore, cold welding between the chuck and the wafer does not affect the flatness of the chuck because the broken peaks are fractured without flashing. Furthermore, cold welding of the chuck to the wafer is not susceptible to contamination of the diffusion chamber used in subsequent processing steps. This is because the chuck material is inert.

本発明の他の好適実施例におｈて、静電力がウェファを
チャックにしっかりと引き付けるために使用される。誘
電体材料がウェファ取付は表面に適用され、ウェファは
アースされ、高電圧がピンチャツクに印加される。真空
源が最初にウェファをチャックと接触させるべく吸引す
るために使用され、その静電力は、ウェファとチャック
との間の距離が小さくなるとウェファをチャックにしっ
かりと保持するのに役立つ。In another preferred embodiment of the invention, electrostatic forces are used to firmly attract the wafer to the chuck. A dielectric material is applied to the wafer attachment surface, the wafer is grounded, and a high voltage is applied to the pinch chuck. A vacuum source is used to initially draw the wafer into contact with the chuck, and the electrostatic force helps to hold the wafer firmly to the chuck as the distance between the wafer and the chuck decreases.

〔実施例〕〔Example〕

第１及び第２図は、通常金属製の別々になったポストが
、処理されるウェファを支持するために使用される従来
技術の典型的外ピンチャックの斜視図及び側面図である
。1 and 2 are perspective and side views of a typical external pin chuck of the prior art in which separate posts, usually made of metal, are used to support the wafer being processed.

第３図は、本発明の図示した好適実施例に従って措成避
れた単一真空ピンチャツク１の斜視図を示す。チャック
１は、直径７．６２　ｃｍ　（ａ　１ｎｃｈ）、厚さ１
．２５ｃｍ　（ｏ、　ｓ　１ｎｃｈ）の一体の単一ケイ
素から成る。チャック１をＧａＡｓ、水晶又はサファイ
アなどの他の結晶材料から製造してもよく、チャック１
によって支、持されるウェファの大きさに応じた他のチ
ャック寸法を使用してもよい。平坦な環状密封表面３は
、内側領域５を囲むチャック１の上表面の外端にそって
設けられている。６個の空気穴７がチャック１を貫通し
てあけられ、真空源への連結を可能にしている。FIG. 3 shows a perspective view of a single vacuum pinch chuck 1 constructed in accordance with the illustrated preferred embodiment of the invention. Chuck 1 has a diameter of 7.62 cm (a 1 nch) and a thickness of 1
．． Consists of 25 cm (o, s 1 nch) of monolithic single silicon. The chuck 1 may be manufactured from other crystalline materials such as GaAs, quartz or sapphire;
Other chuck dimensions may be used depending on the size of the wafer supported by the chuck. A flat annular sealing surface 3 is provided along the outer edge of the upper surface of the chuck 1 surrounding the inner region 5. Six air holes 7 are drilled through the chuck 1 to allow connection to a vacuum source.

第４図はチャックの平面図を示し、第５図はＡ−ＡｉＩ
ｌにそった側面図を示す。内部領域５はビーク１１及び
谷１３を強調するために両図においてスケールが異って
いる。上述した典型的な直径７、　ｅ　２　ｃｍ　（９
１ｎｃｈ）のチャックに対して、ビークの平坦な先端１
１はｚｏｏミクロンｘ２００ミクロンであシ、ビーク１
１の中心はは）丁１０００ミクロンの間隔があけられ、
ビーク１１の平坦な先端は谷１３の底から５０ミクロン
ある。穴７は直径０゜０７　ｅ　ｚｍ（ｏ、　ｏ　ａ　
１ｎｃｈ）で、連結管１５が真空源１７の接続を容易に
するためにチャック１の下側に削り込まれている。いろ
いろなチャックｌが、谷１３からのビーク１１の高さが
１００ミクロンまでのものが構成されｆｃ。Figure 4 shows a top view of the chuck, and Figure 5 shows the A-AiI
A side view along 1 is shown. The internal region 5 is on a different scale in both figures to emphasize the beaks 11 and valleys 13. The typical diameter 7, e 2 cm (9
1nch) chuck, the flat tip of the beak 1
1 is zoo micron x 200 micron, beak 1
The centers of 1 are spaced 1000 microns apart,
The flat tip of beak 11 is 50 microns from the bottom of valley 13. Hole 7 has a diameter of 0°07 e zm (o, o a
1 nch), a connecting tube 15 is cut into the underside of the chuck 1 to facilitate connection of a vacuum source 17. A variety of chucks are constructed with the height of the beak 11 from the valley 13 to 100 microns fc.

第６図は内側領域５の部分を走査電子顕微鏡図のレベル
で示している。これにより、ビーク１１は、他の形状、
例えば角柱を所望なら利用できるけれども、先端が平坦
なピラミッド形状となっている。FIG. 6 shows a portion of the inner region 5 at the level of a scanning electron micrograph. As a result, the beak 11 can have other shapes,
For example, it is shaped like a pyramid with a flat tip, although a square prism could be used if desired.

チャックｌは、（１００）の結晶格子指数（ｏｒｉｅｎ
ｔａｔｔｏｎ）を有する一体の単一ケイ素から製造され
てｂる。他の結晶格子指数を有するケイ素が、他のいろ
いろな幾何学的形状のビーク１１を製造することを望む
ときに使用してもよりＯチャック１が最初に所望の大き
さにカットされ、連続管１３が削り込んで形成される。The chuck l is the crystal lattice index (orien
Manufactured from a single piece of silicon with a tatton. Silicon with other crystal lattice indices can also be used when it is desired to manufacture beaks 11 of various other geometric shapes. 13 is formed by cutting.

上表面（環状密封表面３及び内側領域５から成る表面）
は、周知ノ現代技術を利用してサブミクロンのレベルの
所望の程度の平坦さにゲ１摩される。応力緩和酸化層が
上表面に付着形成され、ビーク１１及び谷１３の所望の
エツチングを可能にするようにバター化された窒化物の
マスクが応力緩和酸化層上に取り付けられる。次に指数
に依存するエツチング（上述した（１００）シリコンに
対しては１（ＯＨのようなもの）がビーク１１及び谷１
３をエツチングするために使用される。最後に、窒化物
のマスクは取９′除かれ、窒化物の耐久性層がＬ６カ緩
和酸化層上に付着形成される。Upper surface (surface consisting of annular sealing surface 3 and inner region 5)
The gel is polished to the desired degree of flatness on the submicron level using well-known modern techniques. A stress-relieving oxide layer is deposited on the top surface and a buttered nitride mask is mounted over the stress-relieving oxide layer to enable the desired etching of peaks 11 and valleys 13. Next, the index-dependent etching (for (100) silicon mentioned above, 1 (like OH) is the peak 11 and valley 1).
Used for etching 3. Finally, the nitride mask is removed 9' and a durable layer of nitride is deposited over the L6 relaxed oxide layer.

使用に際して、チャック１の直径とほぼ等しい直径のウ
ェファがチャック五の上堀凹上に配置されている。平坦
な環状密封表面３がウェファの端のまわりに空気密封を
形成する０述結管１３及び穴７を介して真空が真空源ス
フにより形成され、ウェファが環状表面３及びビーク１
１へと引きつけられる。多くのビーク１１がウェファに
対して複数の平坦な支持点を提供する。In use, a wafer having a diameter approximately equal to the diameter of chuck 1 is placed over the top recess of chuck 5. The flat annular sealing surface 3 forms an airtight seal around the edge of the wafer. A vacuum is created by a vacuum source through the tube 13 and the hole 7 so that the wafer forms an air seal around the edge of the wafer.
Attracted to 1. The many beaks 11 provide multiple flat support points for the wafer.

第７図は、真空及び静電力が第５図に示すようにウェフ
ァ２１をピンチャツク１へと引きつけるために使用され
ている本願発明の他の好適実施例を示している。誘電体
層２３がビンチャック１のビーク１１及び谷１３上に付
着形成されている。FIG. 7 shows another preferred embodiment of the present invention in which vacuum and electrostatic forces are used to attract the wafer 21 to the pinch chuck 1 as shown in FIG. A dielectric layer 23 is deposited over the beaks 11 and valleys 13 of the bottle chuck 1.

誘電体層２３は、例えば厚さ２−３ミクロンの二酸化ケ
イ素から形成してもよい。１０００ボルトのオーダーの
高電圧が電源２５によシチャック１に印加され、ウェフ
ァ２１はアースされている。Dielectric layer 23 may be formed from silicon dioxide, for example, 2-3 microns thick. A high voltage on the order of 1000 volts is applied to the chuck 1 by a power supply 25, and the wafer 21 is grounded.

動作中に、真空源１７は最初にウェファをチャック１に
接近させるべく使用される。次に、電源２５が付勢され
、電源２５の電源の２乗に比例する静電力（チャック五
とウェファ２１との間の距離の２乗に逆比例する）が、
ウェファ２１をチャック１のビーク１１へと引き付ける
ために稼動されるＯピーク１１の領域は、静電力を増加
させるためにその上表面の領域に比較して増加してもよ
く、この場合真空源１７及び環状密封表面３は必要とし
ない０During operation, the vacuum source 17 is used to initially approach the wafer to the chuck 1. Next, the power supply 25 is energized, and an electrostatic force proportional to the square of the power supply of the power supply 25 (inversely proportional to the square of the distance between the chuck 5 and the wafer 21) is generated.
The area of the O-peak 11 activated to attract the wafer 21 to the beak 11 of the chuck 1 may be increased compared to the area of its upper surface in order to increase the electrostatic force, in which case the vacuum source 17 and an annular sealing surface 3 is not required 0

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、従来技術のピンチャツクの斜視図である。 第２図は、第１図に図示の従来技術のピンチャツクの側
面図である。 第３図は、本発明の好適実施例に従って構成されたピン
チャツクの斜視図である。 第４図は、第３図に示すチャックの平面図であるＯ 第５図は、第４図に示すチャックの人−ＡＭにそった側
面図である。 第６図は、第３図に示すチャックの内側領域の拡大図で
ある。 第７図は、静電力が第５図に示すようにウエファヲピン
チャックにしっかりと取り付けるために使用される本発
明の他の好適実施例を示す断面図である。 〔主要符号の説明〕 １．２１−−ウェファ　３−一環状密封表面７−−穴　
１１−−ピーク １３−一谷　１５−一連結管。 １７−−真空源 図面の浄書（内容に変更なし） ＦＩＧ、　Ｉ ＦＩＧ−２ ＦＩＧ、３ 「 ＦＩＧ、４ 手続補正吉 昭和５９年１１月）２−日 １、踵′「庁艮官　志　賀　学　殿 １、　、”Ｊｆｌ’ノ表示ｎｒ４和５９　’ｔ４’Ｆ許
ｒｌｒ！第２１７４４８号２、　発明の名称　ピンチャ
ツク ３、　補正をする者 事件との関係　特許出願人 ′名称　パリアン・アソシエイツ・ インコーホレイテッド ４、代理人 住　所　東京都港区西新槁１丁目６番２１号大和銀行虎
ノ門ビルディング ６、　補正の対象　図　面 ７、　補正の内容　別紙のとおりFIG. 1 is a perspective view of a prior art pinch chuck. FIG. 2 is a side view of the prior art pinchuck shown in FIG. FIG. 3 is a perspective view of a pinch chuck constructed in accordance with a preferred embodiment of the present invention. 4 is a plan view of the chuck shown in FIG. 3. FIG. 5 is a side view of the chuck shown in FIG. 4 along the direction AM. 6 is an enlarged view of the inner region of the chuck shown in FIG. 3; FIG. FIG. 7 is a cross-sectional view of another preferred embodiment of the present invention in which electrostatic forces are used to securely attach the wafer to the pin chuck as shown in FIG. [Explanation of main symbols] 1.21--Wafer 3-Annular sealing surface 7--Hole
11--Peak 13-Tani 15-Series of tubercles. 17--Engraving of the vacuum source drawing (no changes in content) FIG, I FIG-2 FIG, 3 "FIG, 4 Procedural amendment November 1982) Tono1, ,"Jfl'ノdisplay nr4sum59 't4'Fperlrlr! No. 217448 2, Title of the invention Pinchak 3, Relationship to the amended case Patent applicant's name Parian Associates, Inc. 4, Agent address 1-6-21 Nishishingai, Minato-ku, Tokyo, Yamato Bank Toranomon Building 6, Subject of amendment Drawing 7, Contents of amendment As shown in the attached sheet

Claims (1)

【特許請求の範囲】 １、＠加工物を支持するための複数のピークを有し、一
体の結晶物質から構成されるチャックから成る被加工物
を支持する取付は装置。 ２、特許請求の範囲第１項に記載された装置であって、 前記ピークが前記単一の結晶物質をエッチラグすること
により形成されるところの装置。 ３、特許請求の範囲第２項に記載された装置であって、 前記ピークが、実質的に平坦な先端を有するところの装
置。 ４、特許請求の範囲第３項に記載された装置であって、 前記ピークの先端が実質的に同一平面上にあるところの
装置。 ５、特許請求の範囲第４項に記載された装置であって、 前記ピークが実質的に平坦な先端を有するピラミッド形
状であるところの装置。 ６、特許請求の範囲第４項に記載された装置でらって、
更に 実質的に平坦で且つ前記ピークの先端と同一平面上にあ
る環状密封表面から成る装置。 ７、特許請求の範囲第６項に記載された装置であって、
更に、 前記ピークによシ画成される谷と、 真空排気用連結管と、 該連結管を１つ以上の前記釜と連結する、前記チャック
に設けられる１つ以上の穴と、から成るところの装置。 ８、％許請求の範囲第１項に記載された装置であって、 前記結晶物質がケイ素であるところの装置。 ９、特許請求の範囲第８項に記載された装置であって、 前記ケイ素が＜ｉｏｏ＞の結晶格子指数を有するところ
の装置。 １０．　特許請求の範囲第１項に記載された装置であっ
て、 前記被加工物がその結晶物質から成ると仁ろの装置。 １１、特許請求の範囲第１０項に記載された装置であっ
て、 前記被加工物が半導体ウェファから成るところの装置。 １２、特許請求の範囲第４項に記載された装置であって
、更に 前記連結管に接続される真空源から成るところの装置。 １３　特許請求の範囲第４項に記載された装置であって
、更に、 前記ピークを覆う誘電体層と、 前記チャックに接続される高電圧源と、から成るところ
の装置。 １４、％許請求の範囲第１３項に記載された装置であっ
て、 前記被加工物がアースされているところの装置。 １５、特許請求の範囲第１４項に記載された装置であっ
て、更に 前記連結管に接続される真空源から成るところの装置。[Claims] 1. An attachment device for supporting a workpiece consisting of a chuck having a plurality of peaks for supporting the workpiece and composed of an integral crystalline material. 2. The apparatus according to claim 1, wherein the peak is formed by etching and lag the single crystalline material. 3. The apparatus of claim 2, wherein the peak has a substantially flat tip. 4. The device according to claim 3, wherein the tips of the peaks are substantially on the same plane. 5. The device of claim 4, wherein the peak is pyramid-shaped with a substantially flat tip. 6. With the device described in claim 4,
The device further comprises an annular sealing surface that is substantially flat and coplanar with the tip of said peak. 7. The device according to claim 6,
further comprising: a valley defined by the peak; a connecting pipe for evacuation; and one or more holes provided in the chuck that connect the connecting pipe with one or more of the pots. equipment. 8.% Apparatus according to claim 1, wherein the crystalline material is silicon. 9. The device according to claim 8, wherein the silicon has a crystal lattice index of <ioo>. 10. An apparatus according to claim 1, wherein the workpiece is comprised of a crystalline material. 11. The apparatus according to claim 10, wherein the workpiece is a semiconductor wafer. 12. The apparatus according to claim 4, further comprising a vacuum source connected to the connecting pipe. 13. The device according to claim 4, further comprising: a dielectric layer covering the peak; and a high voltage source connected to the chuck. 14.% The apparatus according to claim 13, wherein the workpiece is grounded. 15. The apparatus according to claim 14, further comprising a vacuum source connected to the connecting pipe.
JP21744884A 1983-11-01 1984-10-18 Pin chuck Pending JPS6099538A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US54781183A 1983-11-01 1983-11-01
US547811 1983-11-01

Publications (1)

Publication Number Publication Date
JPS6099538A true JPS6099538A (en) 1985-06-03

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ID=24186226

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Application Number Title Priority Date Filing Date
JP21744884A Pending JPS6099538A (en) 1983-11-01 1984-10-18 Pin chuck

Country Status (5)

Country Link
JP (1) JPS6099538A (en)
DE (1) DE3438980A1 (en)
FR (1) FR2554250A1 (en)
GB (1) GB2149697B (en)
NL (1) NL8403227A (en)

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JPH0488045U (en) * 1990-12-18 1992-07-30
JPH05251544A (en) * 1992-03-05 1993-09-28 Fujitsu Ltd Conveyor
CN102581976A (en) * 2012-03-14 2012-07-18 浙江昀丰新能源科技有限公司 Crystal processing orientation device

Also Published As

Publication number Publication date
GB8427544D0 (en) 1984-12-05
GB2149697B (en) 1987-04-23
FR2554250A1 (en) 1985-05-03
NL8403227A (en) 1985-06-03
GB2149697A (en) 1985-06-19
DE3438980A1 (en) 1985-05-09

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