JP4014813B2 - Semiconductor wafer and inspection method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor wafer and an inspection method thereof, and in particular, by applying a needle to an expansion pad arranged on a dicing line, an integrated circuit can be accurately inspected and evaluated, and yield and reliability are improved. The present invention relates to a semiconductor wafer and an inspection method thereof.
[0002]
[Prior art]
As shown in FIG. 9, generally, a plurality of semiconductor integrated circuits 51 are simultaneously formed on one wafer 70. Then, the wafer 70 is cut (diced) to divide each integrated circuit 51 into chips. FIG. 10 is an enlarged view of the dotted line area 71 of FIG. The integrated circuits 51 are arranged on one wafer 70 with an interval corresponding to the area to be scraped off by a grindstone during dicing. An area scraped off by the grindstone is called a dicing line 53, and serves as a cutting allowance when the wafer 70 is cut to form chips. Therefore, an element (semiconductor element or pad) constituting the final product is not formed on the dicing line.
[0003]
However, the dicing line 53 can be used as follows in addition to the role as a cutting margin. That is, by forming a small integrated circuit such as a DL-TEG (Dicing Line-Test Element Group) 58 on the dicing line 53, information on the operating characteristics of the integrated circuit 51 can be obtained indirectly. The DL-TEG 58 is used for evaluating and inspecting basic operating characteristics of the semiconductor elements constituting the integrated circuit 51. Bonding pads (55, 56) are arranged on the outer periphery of the integrated circuit 51, and an internal circuit 57 is arranged in the center of the integrated circuit 51.
[0004]
In addition, as one step of a series of semiconductor manufacturing processes, a wafer die sort test including discrimination of non-defective / defective products and various evaluations is performed on the integrated circuit 51 in a wafer state before dicing. As shown in FIG. 11, the wafer die sort test is performed by bringing the pins 60 of the fixed (probe) card 59 into electrical contact with the bonding pads (55, 56) of the integrated circuit 51.
[0005]
[Problems to be solved by the invention]
FIG. 12 is a cross-sectional view taken along the line A-A ′ of FIG. 11 and shows a state where the pin 60 extending from the fixed card 59 is in contact with the bonding pad 55. Generally, the pin 60 is made of tungsten (W), and the bonding pads (55, 56) are made of aluminum or the like. Therefore, when the pin 60 comes into contact with the bonding pad 55, the sharp tip of the pin 60 sticks into the bonding pad 55, and the bonding pad (55, 56) made of a softer material than the pin 60 can be damaged. .
[0006]
If the damage received by the bonding pad 55 is large, it becomes difficult for the bonding pad and the bonding wire to come into contact with each other when wire bonding is performed to the chip, resulting in a decrease in yield, such as poor bonding wire contact and increased contact resistance, and reliability. There is a possibility of causing the decline. Further, even if the wire can be bonded once, there is a possibility that contact failure may occur over time due to the influence of vibration or the like.
[0007]
In the wafer die sort test, the power supply potential (VDD), the ground potential (VSS), and various signals are supplied to the integrated circuit 51 through the pins 60 and pads (55, 56). Therefore, demands for reducing the contact resistance between the pin 60 and the pads (55, 56), noise (reflection) and the like are increasing as the integrated circuit 51 is increased in scale and speed. In particular, the enhancement of the ground potential in the integrated circuit 51 is a common important issue. On the other hand, a dedicated ground plane is installed in a part of the packaging member to reduce the VSS impedance. However, in the wafer die sort test, since the length of the pin 60 is longer than that of the bonding wire, it is difficult to perform accurate characteristic evaluation due to an increase in contact resistance, noise generation, and the like.
[0008]
The present invention has been made to solve such problems of the prior art, and an object of the present invention is to accurately test and evaluate an integrated circuit, and to obtain a semiconductor wafer having high yield and reliability. It is to provide an inspection method.
[0009]
[Means for Solving the Problems]
  In order to achieve the above object, a first feature of the present invention is that a plurality of integrated circuits arranged at a predetermined interval, a dicing line arranged between the integrated circuits, and a dicing line are arranged on the dicing line. A semiconductor wafer having an expansion pad, a bonding pad disposed inside an integrated circuit, and an expansion wiring connecting the bonding pad and the expansion padThus, in order to perform a predetermined test on the integrated circuit, it is possible to simultaneously contact the needle with the expansion pad and the bonding pad, and the expansion pad is a small integrated circuit disposed on the dicing line. It is that it is the electrode pad previously arrange | positioned in the inside.
[0010]
According to the feature of the present invention, the bonding pad in the integrated circuit is connected to the expansion pad by the expansion wiring. Therefore, evaluation and inspection of a semiconductor wafer such as a die sort test can be performed by bringing the needle (pin) of the fixed card into contact with the expansion pad. Damage to a bonding pad in an integrated circuit in evaluation / inspection of a semiconductor wafer can be reduced, and contact failure and contact resistance between the bonding pad and a bonding wire can be reduced. Alternatively, the contact resistance (impedance) or noise between the pin and the pad can be reduced.
[0011]
In the first feature of the present invention, one bonding pad may be connected to one extension pad, or a plurality of bonding pads of the same type may be connected to one extension pad.
[0012]
The latter case further has the following two characteristics. First, a plurality of bonding pads of the same type disposed inside a plurality of integrated circuits may be connected to one expansion pad. One extension pad can be shared among multiple integrated circuits. Therefore, the expansion pad can be efficiently arranged on the dicing line. This is particularly useful when a small integrated circuit such as DL-TEG is formed on the dicing line. Second, a plurality of bonding pads of the same type arranged inside one integrated circuit may be connected to one extension pad. As in the first case, the expansion pad can be efficiently arranged on the dicing line.
[0013]
  Also,In the first aspect of the present invention, “a small integrated circuit disposed on a dicing line” means:Unlike an integrated circuit as a final product, which is divided by dicing lines, a small integrated circuit such as a DL-TEG for evaluating and inspecting basic operating characteristics of the integrated circuit in a wafer state is shown. There is no need to locate an expansion pad in search of an empty space in the dicing line, and the expansion pad can be easily provided without significant pattern change.
[0014]
  A second feature of the present invention is a semiconductor wafer having the first feature,Expansion pads and bonding padsSimultaneously contacting a needle (pin) withExpansion pads and bonding padsA method for inspecting a semiconductor wafer having at least a step of performing a predetermined inspection on an integrated circuit in a state where needles (pins) are in contact with each other at the same time.Thus, the extension pad is an electrode pad that is previously arranged in a small integrated circuit arranged on the dicing line.
[0016]
  In the second aspect of the present invention, in the step of performing a predetermined inspection on the integrated circuit, the predetermined inspection is performed in a state where a needle (pin) is further brought into contact with the bonding pad connected to the expansion pad.carry out. That is, the semiconductor wafer is inspected by bringing the pins into contact with the expansion pads and simultaneously bringing the pins into contact with the bonding pads connected to the expansion pads. Increased contact between pin and pad. Therefore, contact resistance (impedance) or noise between the pin and the pad can be reduced.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. In the description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and width, the ratio of dimensions, and the like are different from the actual ones. In addition, it goes without saying that portions with different dimensional relationships and ratios are also included in the drawings.
[0018]
(First embodiment)
The semiconductor wafer according to the first embodiment is a semiconductor wafer on which a plurality of integrated circuits are formed and before performing post-processes such as dicing and packaging. FIG. 1 is a plan view showing a configuration of a semiconductor wafer according to the first embodiment of the present invention. FIG. 1 shows an enlarged part of a plurality of integrated circuits formed on a semiconductor wafer. The semiconductor wafer according to the first embodiment is arranged on a plurality of integrated circuits 1 arranged at predetermined intervals, a dicing line 3 arranged between the integrated circuits 1, and the dicing line 3. At least the expansion pad 2, bonding pads (5, 6) disposed inside the integrated circuit 1, and expansion wiring 4 that connects the bonding pads (5, 6) and the expansion pad 2 are provided.
[0019]
Inside the integrated circuit 1, an internal circuit 7 and bonding pads (5, 6) are arranged. The internal circuit 7 includes, for example, a digital circuit such as a logic circuit and a memory circuit, an analog circuit, and the like, and includes a semiconductor element that can be integrated and a wiring that connects these semiconductor elements. The internal circuit 7 is disposed at the center of the integrated circuit 1, and the bonding pads (5, 6) are disposed on the outer periphery of the internal circuit 7. A part of the bonding pads (5, 6) may be arranged in the central portion of the integrated circuit 1. The bonding pad includes at least a bonding pad (PAD) 5 for supplying a power supply potential (VDD) or inputting / outputting various signals, and a bonding pad (VSS) 6 for supplying a ground potential. ing. In FIG. 1, VSS 6 is arranged at each of the four corners of a rectangular integrated circuit 1, and PAD 5 is arranged at the other corners.
[0020]
The dicing lines 3 are arranged between the integrated circuits 1 arranged in a matrix. Therefore, the dicing line 3 itself has a lattice shape. The dicing line 3 is an area that is scraped off by a grindstone during dicing. Usually, the width of the area scraped off by the grindstone is several tens to several hundreds μm. On the dicing line 3, a DL-TEG (small integrated circuit) 8 for inspecting basic operating characteristics of semiconductor elements constituting the integrated circuit 1 is formed simultaneously with the integrated circuit 1. In the first embodiment, four DL-TEGs 8 are arranged along each side of the rectangular integrated circuit 1. Although not shown in FIG. 1, mask alignment marks for aligning a mask used in the lithography process with respect to the semiconductor wafer are also arranged on the dicing line 3.
[0021]
A plurality of expansion pads 2 are arranged on the dicing line 3. The extension pad 2 and the VSS 6 in the integrated circuit 1 are electrically connected by the extension wiring 4. The arrangement pattern of the extension pads 2 and the extension wirings 4 connected to one integrated circuit 1 is the same for each integrated circuit 1. In the first embodiment, the bonding pads (VSS) 6 and the expansion pads 2 are connected in a one-to-one correspondence. That is, one extension pad 2 is connected to one VSS 6. Further, the extension pad 2 is connected to the nearest VSS 6 and arranged at a position where the length of the extension wiring 4 is the shortest. The manufacturing method of the extension pad 2 and the extension wiring 4 is not particularly limited. For example, the extension pad 2 and the extension wiring 4 may be formed as the uppermost wiring layer in the same process as the bonding pads (5, 6) in the integrated circuit 1, and the bonding pad (5, 6) in the lower wiring layer. It may be created in a different process.
[0022]
FIG. 2 is a plan view showing the arrangement of fixed (probe) cards 9 and pins (10, 11) when performing a wafer die sort test on the semiconductor wafer shown in FIG. As shown in FIG. 2, the normal card 10 and the additional pin 11 are connected to the fixed card 9. The normal pins 10 are in electrical contact with the bonding pads (5, 6) in the integrated circuit 1 respectively. The additional pins 11 are in electrical contact with the expansion pads 2 arranged on the dicing line 3 respectively. Both the normal pin 10 and the additional pin 11 are made of tungsten (W), and the bonding pads (5, 6) and the extension pad 2 are made of aluminum (Al) or the like. The fixed card 9 is formed from a glass epoxy substrate or the like.
[0023]
FIG. 3 is a schematic diagram when the arrangement of the fixed card 9 and the pins (10, 11) with respect to the semiconductor wafer shown in FIG. 2 is viewed from the cross-sectional direction. The normal pin 10 and the additional pin 11 are fixed to the fixed card 9. The tip of the normal pin 10 is pierced into the bonding pad (VSS) 6 inside the integrated circuit 1, and the tip of the additional pin 11 is pierced into the extension pad 2 on the dicing line 3. Although not shown in FIG. 3, the tip of the normal pin 10 pierces the bonding pad (PAD) 5 in the same manner. Thus, the pin (10, 11) and the pad (2, 5, 6) are brought into electrical contact by the hard W pin sticking into the soft Al pad.
[0024]
Next, a semiconductor device inspection method according to the first embodiment will be described.
[0025]
(A) First, with respect to the semiconductor device shown in FIG. 1, as shown in FIGS. 2 and 3, the normal pin 10 and the additional pin 11 are brought into contact with the bonding pad (5, 6) and the extension pad 2, respectively. .
[0026]
(B) Next, a wafer die sort test is performed in a state where the pins (10, 11) are in contact with the pads (2, 5, 6). That is, for each integrated circuit 1 formed on the semiconductor wafer, inspections such as discrimination of non-defective products / defective products and various evaluations are performed. 2 and 3 show a case where a wafer die sort test is performed for each integrated circuit 1. From the viewpoint of shortening the test time, a die sort test may be performed by bringing pins into contact with a plurality of integrated circuits 1 at a time.
[0027]
(C) Next, a predetermined mark is given to the integrated circuit (chip) 1 determined to be defective by the die sort test. Here, “applying a predetermined mark” is to apply an identification material (ink or the like) for identifying a non-defective product / defective product to the defective integrated circuit 1. Thereafter, the dicing line 3 is scraped with a grindstone to divide the semiconductor wafer into semiconductor chips (dicing).
[0028]
(D) Finally, a post-process such as a packaging process is performed only on the non-defective integrated circuit (chip) 1 to which the identification material is not applied to manufacture a final product. On the other hand, a manufacturing process after a die sort test such as a packaging process is not performed on an integrated circuit with a predetermined mark.
[0029]
As described above, the bonding pad (VSS) 6 in the integrated circuit 1 is connected to the extension pad 2 by the extension wiring 4. Then, not only the normal pin 10 of the fixed card 9 is brought into contact with the VSS 6 but also the additional pin 11 is brought into contact with the expansion pad 2. In this state, by performing the die sort test, the contact location is doubled as compared with the case where the normal pin 10 and the VSS 6 are brought into contact with each other. That is, the contact resistance between the pins (10, 11) and the pads (2, 6) with respect to the ground potential can be halved. Therefore, contact resistance (impedance) or noise between the pin and the bonding pad can be reduced. In particular, by reducing the impedance or noise of the VSS 6 that supplies the ground potential, an accurate die sort test can be performed under conditions closer to the actual device, and the integrated circuit 1 can be accurately inspected and evaluated. .
[0030]
The expansion pad 2 is an electrode pad formed on the dicing line 3 that is scraped off in the dicing process. The extension pad 2 is formed in a region where the DL-TEG 8 or the mask alignment mark is not formed on the dicing line 3. Therefore, the provision of the expansion pad 2 makes it possible to effectively use the empty space on the wafer without reducing the area of the area occupied by the integrated circuit 1 or reducing the number of integrated circuits that can be formed on one wafer. Can be used.
[0031]
In the first embodiment, the case where one extension pad 2 is connected to one VSS 6 is shown, but a plurality of extension pads 2 may be connected to one VSS 6. As the number of expansion pads 2 connected to one VSS 6 increases, the contact resistance with respect to the ground potential can be reduced.
[0032]
(Second Embodiment)
In the first embodiment, the semiconductor wafer inspection (die sort test) is performed by bringing the pins (10, 11) into contact with both the expansion pad 2 and the bonding pad 6 connected to the expansion pad 2. Showed the case. The present invention is not limited to this, and the present invention may be carried out by bringing the pin into contact with only the expansion pad 2. In the second embodiment, instead of bringing a pin into contact with the bonding pad 6 in the integrated circuit 1, a die sort test is performed by bringing a pin into contact with the expansion pad 2 on the dicing line 3. explain.
[0033]
The configuration of the semiconductor wafer according to the second embodiment is the same as that of the first embodiment shown in FIG. 1, and the description thereof is omitted here.
[0034]
FIG. 4 shows the arrangement of fixed (probe) cards 12 and pins (13, 14) when performing a wafer die sort test on the integrated circuit 1 formed on the semiconductor wafer according to the second embodiment. It is a top view. As shown in FIG. 4, the other configuration is the same as that shown in FIG. 2 except that the normal pin that is in contact with the bonding pad (VSS) 6 in the integrated circuit 1 is not arranged. As shown in FIG. 4, the normal card 13 and the additional pin 14 are connected to the fixed card 12. The normal pins 13 are in electrical contact with the bonding pads (PAD) 5 in the integrated circuit 1. The additional pins 14 are respectively in electrical contact with the expansion pads 2 arranged on the dicing line 3.
[0035]
FIG. 5 is a schematic diagram when the arrangement of the fixed card 12 and the additional pins 14 with respect to the semiconductor wafer shown in FIG. 4 is viewed from the cross-sectional direction. Except for the point that the tip of the normal pin does not pierce the bonding pad (VSS) 6 inside the integrated circuit 1, the other configuration is the same as FIG. The tip of the additional pin 11 pierces the inside of the expansion pad 2 on the dicing line 3.
[0036]
FIG. 13 shows a state in which the integrated circuit 1 on the semiconductor wafer according to the second embodiment is divided into semiconductor chips and assembled in a package. 13A is a plan view, FIG. 13B is a cross-sectional view taken along the line BB ′, and FIG. 13C is a cross-sectional view taken along the line CC ′. . As shown in FIG. 13, the integrated circuit 1 is disposed on a bed 63, the bed 63 is disposed on a ground plane (VSS reinforced substrate) 62, and the ground plane 62 is disposed on a package outer frame 61. Yes. Bonding pads (PAD) 5 in the integrated circuit 1 are connected to signal bonding pads 64 disposed on the package outer frame 61 by bonding wires 66, respectively. On the other hand, the bonding pads (VSS) 6 in the integrated circuit 1 are respectively connected to the VSS bonding pads 65 arranged on the ground plane 62 by bonding wires 66. By connecting VSS 6 to the ground plane 62, the ground potential of the integrated circuit 1 can be strengthened. Further, since the pins are not in contact with the VSS 6 in the die sort test, the contact state with the wire is good, and it is possible to prevent the occurrence of contact failure and increase in contact resistance.
[0037]
As described above, when the die sort test is performed, the additional pin 14 is brought into contact with the expansion pad 2, and the normal pin is not brought into contact with the bonding pad (VSS) 6 in the integrated circuit 1. Therefore, the bonding pad (VSS) 6 in the integrated circuit 1 is not damaged by the contact of the pins. Therefore, there is no possibility of causing a decrease in yield and a decrease in reliability such as a contact failure between the bonding pad (VSS) 6 and the bonding wire and an increase in contact resistance. In particular, by preventing the pins from contacting the bonding pad (VSS) 6 that supplies the ground potential, the reliability / yield of wire bonding to the bonding pad (VSS) 6 is improved, and the ground potential in the integrated circuit 51 is enhanced. The
[0038]
(Third embodiment)
In the first and second embodiments, the case where the bonding pad (VSS) 6 and the expansion pad 2 are connected in a one-to-one relationship has been described. However, one expansion pad 2 is connected to two or more. It may be shared by the bonding pad (VSS) 6. In the third embodiment, a case will be described in which a plurality of bonding pads 6 of the same type respectively disposed in two adjacent integrated circuits 1 are connected to one expansion pad 15.
[0039]
FIG. 6 is a plan view showing a configuration of a semiconductor wafer according to the third embodiment of the present invention. As shown in FIG. 6, the extension pad 15 disposed on the dicing line 3 is connected to each bonding pad (VSS) 6 in the integrated circuit 1 disposed on both sides of the dicing line 3. That is, as compared with the configuration of the semiconductor wafer shown in FIG. 1, a difference is that a plurality of VSSs 6 in the adjacent integrated circuit 1 share one expansion pad 15. The VSS 6 and the extension pad 15 are connected by the extension wiring 16. Other configurations are the same as those shown in FIG.
[0040]
When the die sort test is performed on the semiconductor wafer shown in FIG. 6, the arrangement of the pins (10, 11) is the arrangement shown in FIG. 2 and FIG. 3 (first embodiment), or FIG. Any of the arrangements (first embodiment) shown in FIG. 5 may be used. That is, the wafer die sort test may be performed with the pins (10, 11) being in contact with both the VSS 6 and the expansion pad 2, or may be performed with the additional pin 14 being in contact with only the expansion pad 2. In the former case, the impedance and noise with respect to the ground potential are reduced, and in the latter case, the reliability and yield of wire bonding to the VSS 6 are improved.
[0041]
As described above, the number of the expansion pads 15 can be halved by connecting the VSS 6 disposed in the two adjacent integrated circuits 1 to one expansion pad 15. Also, the die sort test can be performed using the pin arrangement shown in the first or second embodiment. Therefore, the empty space on the wafer can be used more effectively without impairing the operational effects of the semiconductor wafer and the inspection method thereof according to the first and second embodiments. In particular, it is useful when the area of the DL-TEG 8 or the mask alignment mark is relatively large, or when the empty space of the dicing line is small.
[0042]
In the third embodiment, the case where two bonding pads 6 are connected to one expansion pad 15 has been described. However, the number of bonding pads 6 connected to one expansion pad 15 is limited to two. It is not something. Three or more bonding pads 6 belonging to different integrated circuits 1 may be connected to one expansion pad 15.
[0043]
(Fourth embodiment)
In the third embodiment, the case where a plurality of bonding pads (VSS) 6 belonging to different integrated circuits 1 are connected to one expansion pad has been described. However, the present invention is not limited to the case where a plurality of bonding pads 6 belong to different integrated circuits 1, and a plurality of bonding pads 6 belonging to one integrated circuit 1 are connected to one extension pad. It does not matter. In the fourth embodiment of the present invention, a case where one expansion pad is connected to a plurality of bondings of the same type arranged inside one integrated circuit 1 will be described.
[0044]
FIG. 7 is a plan view showing a configuration of a semiconductor wafer according to the fourth embodiment. As shown in FIG. 7, three bonding pads (VSS) 6 arranged inside one integrated circuit 1 are connected to one expansion pad 18 via an expansion wiring 17, respectively. The VSS 6 for supplying the ground potential is disposed at each of the four corners of the rectangular integrated circuit 1 and further disposed at the center of the two opposite sides. Further, the DL-TEG 8 is not disposed on the dicing line 3 in contact with the two opposing sides.
[0045]
The wafer die sort test can be performed on the semiconductor wafer shown in FIG. 7 with the pins in contact with both the VSS 6 and the expansion pad 18 or with the additional pins in contact with only the expansion pad 18. I do not care. In the former case, the impedance and noise with respect to the ground potential are reduced, and in the latter case, the reliability and yield of wire bonding to the VSS 6 are improved.
[0046]
As described above, even if one extension pad is connected to a plurality of bondings of the same type arranged in one integrated circuit 1, the number of extension pads 18 formed on the dicing line 3 can be reduced. Can be reduced. Therefore, the empty space on the wafer can be used more effectively without impairing the operational effects of the semiconductor wafer and the inspection method according to the first and second embodiments. In particular, it is useful when the area of the DL-TEG 8 or the mask alignment mark is relatively large, or when the empty space of the dicing line 3 is small.
[0047]
In FIG. 7, one extension pad 18 is shared by the three VSS 6 in one integrated circuit 1. However, even if one extension pad 18 is shared between adjacent integrated circuits 1. I do not care. That is, the pattern of the extension wiring 17 may be partially changed, and the six VSS 6 of the two adjacent integrated circuits 1 may share the two extension pads 18.
[0048]
(Fifth embodiment)
In the first to fourth embodiments, the description has been given of the case where the expansion pad is arranged in the region where the DL-TEG 8 on the dicing line 3 is not arranged. However, there are cases where an electrode pad for bringing a pin into contact is also arranged inside the DL-TEG 8. Therefore, in the fifth embodiment of the present invention, a case will be described in which an electrode pad disposed in the DL-TEG 8 is used as an expansion pad.
[0049]
FIG. 8 is a plan view showing a configuration of a semiconductor wafer according to the fifth embodiment. As shown in FIG. 8, the expansion pad 19 is disposed inside the DL-TEG 8. The extension pad 19 and the bonding pad (VSS) 6 are connected by an extension wiring 20. The expansion pad 19 is an electrode pad with which a pin is contacted when the basic operation characteristics of the semiconductor elements constituting the integrated circuit 1 are inspected using the DL-TEG 8. DL-TEGs 8 are arranged along the four sides of the integrated circuit 1. One VSS 6 is connected to one expansion pad 19.
[0050]
Also for the semiconductor wafer shown in FIG. 8, as in the third and fourth embodiments, even if the wafer die sort test is carried out by bringing pins into contact with both the VSS 6 and the extension pad 18, the extension is possible. An additional pin may be brought into contact with only the pad 18 for implementation.
[0051]
As described above, the electrode pad can be used as the extension pad 19 by connecting to the bonding pad (VSS) 6 via the extension wiring 20 to the electrode pad arranged in advance in the DL-TEG 8. Therefore, it is not necessary to arrange the extension pad in the region where the DL-TEG 8 or the mask alignment mark is not arranged on the dicing line. There is no need to locate the expansion pad in search of an empty space in the dicing line 3, and the expansion pad can be easily provided without significant pattern change. In particular, it is useful when the dicing line 3 is filled with DL-TEG 8 and a mask alignment mark, and an empty space for providing an extension pad is not left on the dicing line 3.
[0052]
In FIG. 8, the VSS 6 and the expansion pad 20 are connected in a one-to-one correspondence. However, as shown in the third or fourth embodiment, a plurality of the expansion pads are connected to one expansion pad. VSS6 may be connected, or one or more VSS6 may be connected to a plurality of expansion pads.
[0053]
In the first to fifth embodiments, the expansion pad is connected to the bonding pad (VSS) 6 for supplying the ground potential. However, the present invention is not limited to this. The expansion pad 2 may be connected to other pads (pads for supplying a power supply potential, pads for inputting / outputting signals) 5 constituting the integrated circuit 1.
[0054]
【The invention's effect】
As described above, according to the present invention, an integrated circuit can be accurately inspected and evaluated, and a semiconductor wafer having a high yield and reliability and an inspection method thereof can be provided.
[Brief description of the drawings]
FIG. 1 is a plan view showing a configuration of a semiconductor wafer according to a first embodiment of the present invention, and is an enlarged view of a part of a plurality of integrated circuits formed on the semiconductor wafer.
2 is a plan view showing the arrangement of fixed (probe) cards and pins when a wafer die sort test is performed on the semiconductor wafer shown in FIG. 1; FIG.
3 is a schematic view of the arrangement of fixed cards and pins with respect to the semiconductor wafer shown in FIG. 2 when viewed from a cross-sectional direction.
FIG. 4 is a plan view showing the arrangement of fixed (probe) cards and pins when performing a wafer die sort test on an integrated circuit formed on a semiconductor wafer according to a second embodiment of the present invention. .
5 is a schematic view when the arrangement of the fixed card and the additional pins with respect to the semiconductor wafer shown in FIG. 4 is viewed from the cross-sectional direction.
FIG. 6 is a plan view showing a configuration of a semiconductor wafer according to a third embodiment of the present invention, and is an enlarged view of a part of a plurality of integrated circuits formed on the semiconductor wafer.
FIG. 7 is a plan view showing a configuration of a semiconductor wafer according to a fourth embodiment of the present invention, and is an enlarged view of a part of a plurality of integrated circuits formed on the semiconductor wafer.
FIG. 8 is a plan view showing a configuration of a semiconductor wafer according to a fifth embodiment of the present invention, and is an enlarged view of a part of a plurality of integrated circuits formed on the semiconductor wafer.
FIG. 9 is a plan view showing a general configuration of a general semiconductor wafer in which a plurality of integrated circuits are arranged on one wafer.
10 is an enlarged view of a dotted line area in FIG. 9;
11 is a plan view showing an arrangement of fixing (probe) cards and pins when performing a wafer die sort test on the semiconductor wafer shown in FIG. 10 according to the prior art.
12 is a cross-sectional view taken along the line A-A ′ in FIG. 11;
FIG. 13 shows a state in which an integrated circuit on a semiconductor wafer according to a second embodiment is divided into semiconductor chips and assembled in a package. 13A is a plan view, FIG. 13B is a cross-sectional view taken along the line BB ′, and FIG. 13C is a cross-sectional view taken along the line CC ′. .
[Explanation of symbols]
1 Integrated circuits
2, 15, 18, 19 Expansion pad
3 Dicing line
4, 16, 17, 20 Extended wiring
5 Bonding pads (PAD)
6 Bonding pad (VSS)
7 Internal circuit
8 DL-TEG
9,12 Fixed card
10, 13 Normal pin
11, 14 Additional pin

Claims (5)

A plurality of integrated circuits arranged at predetermined intervals; and
A dicing line disposed between the integrated circuits;
An expansion pad disposed on the dicing line;
A bonding pad disposed inside the integrated circuit;
An extension wiring connecting the bonding pad and the extension pad;
In order to perform a predetermined test on the integrated circuit, it is possible to simultaneously contact a needle with the expansion pad and the bonding pad;
The expansion pad is an electrode pad arranged in advance in a small integrated circuit arranged on the dicing line. The same kind of a plurality of the bonding pads, one of said semiconductor wafer according to claim 1, characterized in that it is connected to the expansion pads. 3. The semiconductor wafer according to claim 2 , wherein a plurality of the bonding pads arranged inside the plurality of integrated circuits are connected to one of the expansion pads. The semiconductor wafer according to claim 2 , wherein a plurality of the bonding pads arranged inside one integrated circuit are connected to one expansion pad. A plurality of integrated circuits arranged at predetermined intervals, a dicing line arranged between the integrated circuits, an expansion pad arranged on the dicing line, and a bonding arranged inside the integrated circuit In a semiconductor wafer having a pad and an extension wiring that connects the bonding pad and the extension pad, a step of bringing a needle into contact with the extension pad and the bonding pad at the same time;
Carrying out a predetermined test on the integrated circuit in a state in which a needle is simultaneously in contact with the expansion pad and the bonding pad;
The method of inspecting a semiconductor wafer, wherein the extension pad is an electrode pad previously disposed in a small integrated circuit disposed on the dicing line.

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