JPS6281724A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6281724A JPS6281724A JP22310485A JP22310485A JPS6281724A JP S6281724 A JPS6281724 A JP S6281724A JP 22310485 A JP22310485 A JP 22310485A JP 22310485 A JP22310485 A JP 22310485A JP S6281724 A JPS6281724 A JP S6281724A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chips
- pad
- time
- testing
- chips
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体装置に関し、特に入出力数の少ないＤＲ
ＡＭ等のＬＳＩに係わるものである。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to a DR device with a small number of inputs and outputs.
It is related to LSI such as AM.
従来、半導体ウェハに格子状に形成された半導体チップ
は、１チツプごとにプロービングを行うことによりダイ
ソート試験が行なわれる。Conventionally, semiconductor chips formed in a grid pattern on a semiconductor wafer are subjected to a die sort test by probing each chip.
しかしながら、従来のダイソート試験では、１枚のウェ
ハの試験を行うために１チツプごとにプローブの移動、
試験を繰返しているため、全体の試験時間は、
（１チツプの試験時間＋移動時間）
Ｘチップ数
の時間がかかる。そこで、試験のスループットを−Ｌげ
るためには、
■、試験時間を短縮化させること、
■、復数のチップを同時に測定すること、が考えられる
が、■に関しては現在可能な限りの短縮化が考えられ、
すでに限界に近い。一方、■の場合は、ＬＳＩのボンデ
ィングパターンそのままを用いてマルチチップの試験は
行なわれているが、その方法だとせいぜい２チップ止ま
りである。However, in conventional die sort testing, in order to test one wafer, the probe must be moved for each chip.
Since the test is repeated, the total test time is (test time for 1 chip + moving time) x number of chips. Therefore, in order to increase the test throughput by -L, it is possible to (1) shorten the test time, and (2) measure multiple chips at the same time. It is thought that
Already close to the limit. On the other hand, in the case of (2), multi-chip testing is performed using the LSI bonding pattern as it is, but this method can only test two chips at most.
ことにより、多数の半導体チップを同時に試験できる半
導体装置を提供することを目的とする。Accordingly, it is an object of the present invention to provide a semiconductor device that can test a large number of semiconductor chips simultaneously.
本発明は、ダイシングラインによって分離されたウェハ
状の複数の半導体チップと、これら半導体チップのダイ
ソート試験を行うパッド集合体と、前記半導体チップの
入出力パッドとパッド集合体を結ぶ配線とを具備するこ
とを特徴とし、多数の半導体チップを同時に試験するこ
とを図ったものである。The present invention comprises a plurality of wafer-shaped semiconductor chips separated by dicing lines, a pad assembly for performing a die sort test on these semiconductor chips, and wiring connecting input/output pads of the semiconductor chips and the pad assembly. It is characterized by the ability to test a large number of semiconductor chips at the same time.
また、本発明において、パッド集合体や配線をダイシン
グライン領域に設ければ、特別な領域を確保することな
く半導体チップの試験が可能となる。また、ウェハスク
ライブ時に前記配線がカットされるので、入出力キャパ
シタの増加等の悪影響を伴うことない。これは、従来、
ダイシングラインがダイシング用の「のりＩｌｌ Ｊを
取るためにだけ用いられ、ダイソート試験時等では無駄
な部分となっていることに注目したものである。Further, in the present invention, if the pad assembly and wiring are provided in the dicing line area, it becomes possible to test the semiconductor chip without securing a special area. Furthermore, since the wiring is cut during wafer scribing, there is no adverse effect such as an increase in input/output capacitors. This is conventionally
This paper focuses on the fact that the dicing line is used only to remove glue for dicing, and is a wasted part during die sorting tests.
〔発明の実施例〕 以下、本発明の一実施例を図を参照して説明する。[Embodiments of the invention] An embodiment of the present invention will be described below with reference to the drawings.
図中の１〜８は、夫々ＬＳＩを形成したウェハ状の半導
体チップである。これら半導体チップ−８間のダイシン
グライン９ａが設けられた領域には、これら半導体チッ
プ１〜８のダイソート試験を行うパッド集合体１０が設
けられている。前記ダイシングライン９ａ及び他のダイ
シングライン１０ｂ、１０ｃ、１０ｄ・・・が設けられ
た領域には、半導体チップ１〜８のボンディング用の入
出力パッド（図示せず）とパッド集合体１ｏを結ぶＩＭ
ｕの配線１１・・・が夫々設けられている。1 to 8 in the figure are wafer-shaped semiconductor chips each forming an LSI. In the area where the dicing lines 9a between these semiconductor chips 8 are provided, a pad assembly 10 for performing a die sort test on these semiconductor chips 1 to 8 is provided. In the area where the dicing line 9a and the other dicing lines 10b, 10c, 10d, . . .
Wires 11 . . . are provided respectively.
こうした構造の半導体装置によれば、半導体チップ１〜
８のダイソート試験時は、プローブ針をパッド集合体１
０に当接するだけで８個の半導体チップ１〜８を同時に
試験することができる。従って、ｎ個の半導体チップを
全部試験する時間は、（１個のチップの試験時間＋移動
時間）×チップ数÷ｎ
となり、従来の１ ／ ｎで済むことが確認できる。According to the semiconductor device having such a structure, semiconductor chips 1 to
During the die sort test in step 8, the probe needle is attached to pad assembly 1.
Eight semiconductor chips 1 to 8 can be tested at the same time by simply contacting the terminal. Therefore, it can be confirmed that the time required to test all n semiconductor chips is (test time for one chip + moving time) x number of chips ÷ n, which is 1/n compared to the conventional method.
また、試験終了後に良品をパッケージングする際、ウェ
ハスクライブ時に前記配線１１．１２はカットされるの
で、入出力キャパシタンスの増加等の悪影響を回避でき
る。更に、特別な領域をウェハ上に設けることなくパッ
ド集合体１０の領域を確保できる。更には、プローブ針
が直接入出力パッドに当たることがないため、プローブ
針で入出力パッドを損傷する恐れもない。なお、入力パ
ッドだけならば全チップを接続してしまい１本にまとめ
ることも可能なので、１カ所のテストパッドで全半導体
チップのテストを行うことも考えられる。Further, when packaging non-defective products after the test, the wirings 11 and 12 are cut during wafer scribing, so that adverse effects such as an increase in input/output capacitance can be avoided. Furthermore, the area for the pad assembly 10 can be secured without providing a special area on the wafer. Furthermore, since the probe needle does not directly hit the input/output pad, there is no risk of damaging the input/output pad with the probe needle. Note that if there are only input pads, it is possible to connect all the chips and combine them into one, so it is also possible to test all the semiconductor chips with one test pad.
なお、上記実施例では、パッド集合体をダイシングライ
ン領域に設けた場合について述べたが、これに限らず、
ウェハの他の領域にパッド集合体を設けても複数の半導
体チップのダイソート試験を同時に行うことができる。In addition, although the above embodiment describes the case where the pad assembly is provided in the dicing line area, the present invention is not limited to this.
Even if pad assemblies are provided in other areas of the wafer, die sort testing of a plurality of semiconductor chips can be performed simultaneously.
以上詳述した如く本発明によれば、パッド集合体の存在
により、複数の半導体チップを同時にダイソート試験で
きる半導体装置を提供できる。As described in detail above, according to the present invention, it is possible to provide a semiconductor device in which a plurality of semiconductor chips can be simultaneously die-sorted tested due to the presence of the pad assembly.
図は本発明の一実施例に係る半導体装置の説明図である
。
１〜８・・・半導体チップ、９ａｓ９ｂ１９ｃ・・・ダ
イシングライン、１０・・・パッド集合体、１１・・・
配線。The figure is an explanatory diagram of a semiconductor device according to an embodiment of the present invention. 1-8... Semiconductor chip, 9as9b19c... Dicing line, 10... Pad assembly, 11...
wiring.
Claims (2)
複数の半導体チップと、これら半導体チップのダイソー
ト試験を行うパッド集合体と、前記半導体チップの入出
力パッドとパッド集合体を結ぶ配線とを具備することを
特徴とする半導体装置。(1) A plurality of wafer-shaped semiconductor chips separated by dicing lines, a pad assembly for performing a die sort test on these semiconductor chips, and wiring connecting the input/output pads of the semiconductor chips and the pad assembly. A semiconductor device characterized by:
域に設けられていることを特徴とする特許請求の範囲第
１項記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the pad assembly and wiring are provided in a dicing line area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22310485A JPS6281724A (en) | 1985-10-07 | 1985-10-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22310485A JPS6281724A (en) | 1985-10-07 | 1985-10-07 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6281724A true JPS6281724A (en) | 1987-04-15 |
Family
ID=16792886
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22310485A Pending JPS6281724A (en) | 1985-10-07 | 1985-10-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6281724A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01198051A (en) * | 1988-02-03 | 1989-08-09 | Tokyo Electron Ltd | Semiconductor integrated circuit |
| US5285082A (en) * | 1989-11-08 | 1994-02-08 | U.S. Philips Corporation | Integrated test circuits having pads provided along scribe lines |
| US5923047A (en) * | 1997-04-21 | 1999-07-13 | Lsi Logic Corporation | Semiconductor die having sacrificial bond pads for die test |
| US5981971A (en) * | 1997-03-14 | 1999-11-09 | Kabushiki Kaisha Toshiba | Semiconductor ROM wafer test structure, and IC card |
| US7372072B2 (en) * | 2004-12-15 | 2008-05-13 | Infineon Technologies Ag | Semiconductor wafer with test structure |
-
1985
- 1985-10-07 JP JP22310485A patent/JPS6281724A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01198051A (en) * | 1988-02-03 | 1989-08-09 | Tokyo Electron Ltd | Semiconductor integrated circuit |
| US5285082A (en) * | 1989-11-08 | 1994-02-08 | U.S. Philips Corporation | Integrated test circuits having pads provided along scribe lines |
| US5981971A (en) * | 1997-03-14 | 1999-11-09 | Kabushiki Kaisha Toshiba | Semiconductor ROM wafer test structure, and IC card |
| US5923047A (en) * | 1997-04-21 | 1999-07-13 | Lsi Logic Corporation | Semiconductor die having sacrificial bond pads for die test |
| US7372072B2 (en) * | 2004-12-15 | 2008-05-13 | Infineon Technologies Ag | Semiconductor wafer with test structure |
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