JPH04152543A - Integrated circuit structure body provided with self-inspection function; sorting method of good integrated circuit chip by using it - Google Patents

Abstract

PURPOSE:To surely judge, in a nondestructive manner, whether integrated circuit chips for an operating frequency which by far exceeds conventional operating frequencies such as Josephson integrated circuit chips or the like are good or not by a method wherein an integrated circuit under test and a test circuit are juxtaposed in different regions which are situated on the same board and which can be divided. CONSTITUTION:An integrated circuit 31 under test which is subjected to the judgment of whether it is good or not and a test circuit 32 which tests the integrated circuit 31 under test and which extracts a test data are juxtaposed in different regions 21, 22 which are situated on the same board 21 and which can be divided. Bonding pads 35 for test use which are required to connect the test circuit 32 to an external analysis apparatus are provided only in the region 22 which is situated on said board 20 and in which the test circuit 32 is formed. For example, a Josephson integrated circuit 31 under test is formed in a first region 21 of a board 20; a Josephson test circuit 32 which performs the operation test of the Josephson integrated circuit 31 under test and which extracts a test data is formed in a second region 22. The Josephson test circuit 32 is connected to the Josephson integrated circuit 31 under test by using interconnections 33 on the board 20.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to a Josephson integrated circuit,
The present invention relates to technology for reliably determining the quality of integrated circuits that can operate much faster than existing semiconductor integrated circuits, and for selecting only good products.

[Conventional technology] Even if the semiconductors are of the same type, the operating principle is
Even at the present time, Josephson integrated circuits are expected to operate more than ten times faster than existing semiconductor integrated circuits while consuming less than one fraction of the power. In fact, there are expectations that if this technology is implemented in high density, it will be possible to realize extremely high-speed, extremely large-capacity computers in the future.

Moreover, recently, as reported in the morning editions of various newspapers on December 13, 1989, the present applicant was the first in the world to
He also succeeded in putting the so-called Josephson computer into operation. This means that the operating principle of the Josephson computer has been proven, and we have reached the stage where research is finally underway to create a practical, high-performance Josephson computer.

However, the implementation technique of the integrated circuit itself as described above is required. Since this inherently provides an environment for high-speed signal transmission, it is a technology that we would like to transfer to Josephson integrated circuit technology if possible.

However, there are drawbacks; once individual integrated circuit chips are mounted on a system board, bonding
The pads are destroyed when they are mounted, so even if it is later discovered that one of the integrated circuit chips installed is defective, it is necessary to remove all the chips and reattach only the good ones. It is not possible.

Therefore, even in conventional semiconductor technology, flip chip bonding technology is two sides of the same coin, and before each integrated circuit chip is mounted on the system board,
There is a need for technology to perform non-destructive testing in advance and sort out good and defective products, and this is generally shown in Figures 5 (a) and (b).
It was done in the manner shown.

Semiconductor integrated circuit chip to be tested 10.1 to be judged good or bad
0 generally includes a plurality of bonding pads 12.0 along its periphery. ... are formed, so a thin terminal wire 11 called a micro-prober bin is connected to them. ... are brought into contact with each other, and the other end is connected to a semiconductor device-based analysis device (usually a computer), not shown. Of course, this is natural since the object to be inspected is a semiconductor integrated circuit chip, but generally the temperature environment for measurement may be room temperature.

It is true that according to such a method, the operation test of the semiconductor integrated circuit chip 10 under test can be performed non-destructively without contaminating or damaging each bonding pad 1z of the semiconductor integrated circuit chip 10 under test. If only the components are selected, automatic mounting onto the system board using a wire bonder or flip chip bonder can be performed with confidence.

[Question B to be solved by the invention] Dear Mr., An arrangement in which a plurality of bonding pads are formed on the periphery (there is no problem with this arrangement itself;
Even though it is preferable), it cannot be applied.

This can be explained as follows, but simply put, it is due to the excellent characteristics of the Josephson integrated circuit itself.

That is, the Josephson integrated circuit is capable of extremely high speed operation as mentioned above, and it is thought that the operating frequency will easily exceed 1 gigahertz in the future. Therefore, in order to perform the operation test, not only the response speed of the test system but also the signal transmission system itself is required to have an equivalent or higher speed.

However, as mentioned above, each bonding pad 11.
For ..., the limit is about the size of a micro blower bottle.

Furthermore, even if high-speed signal transmission performance could be achieved in the signal transmission system, computers using existing semiconductor devices used as test data analysis equipment would not be able to keep up with the operating speed, and the first Josephson integrated circuit would be at an extremely low temperature. Although it must be operated in an environmentally friendly environment, the conventional methods described above have not passed tests in such extremely low temperature environments.

In addition, even though they are integrated circuits based on the same semiconductor, the operating environment is different.
Similarly, if a semiconductor device that can operate on the giga hertz order is provided in the future compared to the conventional device that operates on the mega hertz order even if it is good at room temperature, It is no longer possible to conduct tests using micro blower bottles as in the past.

The present invention has been made in view of these conventional circumstances, and is intended to be applied to integrated circuits that far exceed conventional operating frequencies, such as Josephson integrated circuit chips and ultra-high-speed semiconductor integrated circuit chips that may be provided in the future. Even if it is a circuit chip, it can be reliably determined whether it is good or bad in a non-destructive manner, and even when applied to Josephson integrated circuit chips that operate in an extremely low temperature environment instead of a room temperature environment, it can be done under the same conditions as the actual operating conditions. That is, the present invention aims to provide an integrated circuit structure that can be tested reliably and at a sufficiently high speed in an extremely low temperature environment, or a method for selecting non-defective chips using the integrated circuit structure.

[Means for Solving tJff] In order to achieve the above-mentioned object, the present invention provides an integrated circuit to be tested to be judged whether it is good or bad, and a test circuit to perform a test operation on the integrated circuit to be tested and extract test data. The test bonding pads, which are arranged in parallel on different areas on the same board that can be separated from each other and are necessary for connecting the test circuit to an external analysis device, are placed on the board area where the test circuit is installed as described above. This paper presents a method of dividing the area where the integrated circuit is formed on the integrated circuit, which has a self-testing function provided only for the test circuit, from the area where the test circuit is formed, and creating a new independent integrated circuit chip.

In addition, when the board is provided as a test board, only one test circuit is formed for a plurality of integrated circuits to be inspected that are formed on the board so that they can be separated from each other, and that one test circuit covers all the integrated circuits. We also propose a configuration for extracting test data from the integrated circuit under test.

Furthermore, if the integrated circuit to be tested is a Josephson integrated circuit, we also propose a configuration in which the test circuit is also a Josephson integrated circuit.

In addition to these, the test circuit includes a memory that stores an instruction program necessary for test operation, a processor that operates according to this instruction program, a register file that stores test data obtained as the processor operates, and a register.・According to the present invention, a test circuit for testing an integrated circuit under test is mounted on the same board, and the test bonding pads necessary for connecting this test circuit to an external analysis device are Since it is provided only in the area of the board where the test circuit is provided, in order to mount the integrated circuit under test on the system board in the future, it is also provided in the area where the integrated circuit under test is formed. Even if a mounting bonding pad is provided, this mounting bonding pad does not need to be used.

Therefore, if the area in which the integrated circuit to be inspected, which is determined to be good as a result of the test using the test circuit, is formed is divided from the area in which the test circuit is formed, and this is made into an independent integrated circuit chip, Using flip chip bonding technology, which has already been established in semiconductor technology, it is possible to mount only a plurality of good integrated circuit chips on one system board.

The test circuit also extracts test data from the integrated circuit under test (i.e., the test circuit naturally also has the ability to supply power to the integrated circuit under test and provide appropriate signals for testing). Therefore, the test itself is also conducted non-destructively.

Of course, this is because the substrate is a wafer, and a plurality of integrated circuits to be tested are formed on this wafer, whereas the test circuit is the same even in one case, and the test circuits are all tested on the same wafer. Since test data from the test integrated circuits is extracted, it is possible to know in advance which integrated circuits to be tested are on the wafer and can be cut out as good chips and which should be discarded as defective chips.

Therefore, the integrated circuit structure or the method for selecting good chips of the present invention is also optimal for use in Josephson integrated circuits. This is because the integrated circuit under test and the test circuit can be configured as the same Josephson device-based integrated circuit, so there is no problem with operating speed, and both can operate in an extremely low temperature environment. It is from. In other words, the Josephson integrated circuit to be tested can be tested under exactly the same conditions as its actual operating conditions, and its reliability is extremely high.

Furthermore, as a configuration suitable for connecting to an external analysis device,
The test circuit has a memory that stores an instruction program necessary for test operation, a processor that operates according to this instruction program, a register file that stores test data obtained as the processor operates, and a register file. If it is equipped with an interface circuit for sending stored test data to an external analysis device, it is also possible to convert the test data collected at high speed into serial-to-parallel data and send it to the external analysis device. Therefore, even if the external analysis device is a relatively slow existing semiconductor analysis device, such as a semiconductor computer, it can be used to analyze the test data of the Josephson integrated circuit under test.
Furthermore, it can be used to determine the quality of Josephson integrated circuits to be tested that are to be cut into chips.

Note that various methods are known for cutting out or dividing the selected good chips, including methods using mechanical cutters and methods using laser beams, for conventional semiconductor products. So you can use these as you like.

In addition, when a semiconductor integrated circuit is provided that operates at a much higher speed than existing semiconductor integrated circuits, and is not limited to Josephson integrated circuits, this book is used for non-destructive testing under actual operating conditions. The invention is equally applicable and performs the same function as above.

[Example] Examples of the present invention will be described below with reference to the attached drawings.Here, we will explain how to test Josephson integrated circuits, which could not be tested using conventional test equipment for semiconductor integrated circuits. Assume that it is a circuit.

In the case of the structure of the embodiment of the present invention shown in FIG. 1, the substrate 20 has a rectangular planar shape, and the substrate 20 has a substantially square first area 21 and a second area in contact with the side thereof. At the stage before the actual division, the inner regions 21 and 22 together constitute one principal surface region of the substrate 20, and the inner regions 21 and 22 are not actually divided.

However, it is completely differentiated functionally, and the first area 21 contains the Josephson integrated circuit 31 that will be mounted on the system board of the Josephson chip, for example, when it is determined to be a good product in the future. Formed as an integrated circuit 31, a Josephson test circuit 32 is formed in the second region 22 for performing an operation test on the Josephson integrated circuit 31 to be tested and extracting test data.

The Josephson test circuit 32 is connected to the Josephson integrated circuit 31 to be tested by wiring 33 on the board 20, and supplies power to the Josephson integrated circuit 31 to be tested and applies appropriate signals for testing. It is also possible to extract test data obtained from the Josephson integrated circuit 31 under test.

The wiring 33 is preferably a so-called strip line in view of the need for high-speed signal transmission, but the test data via this is, for example, transmitted to the Joseph under test for various groups of applied logic signals. son integrated circuit 3
It may be the result of a logical operation performed by 1.

If the Josephson integrated circuit 31 to be tested mounted in the first area 21 is judged to be a good product in the future, the area on the main surface of the first area 21, for example along its periphery, will be A suitable number of mounting bonding pads 34, suitable for mounting by flip chip bonding on the system board. ... are provided at appropriate intervals, and on the other hand, in the second area 22,
Also suitable for temporarily mounting the Josephson test circuit 32 on a test board (not shown) during testing by flip-chip bonding, it is also appropriately arranged along the periphery of the second region. The required number of test bonding pads 35. ...is provided.

In other words, even if it becomes necessary to electrically and mechanically fix the board 20 on a suitable test board (not shown) during testing, the second area 22 can be used as a bonding pad for that purpose. Attached bonding pad 35.・・・
..., and the mounting bonding pad 34 attached to the first area 21 on which the Josephson integrated circuit 31 to be tested is mounted can be kept in an unused state without being damaged. There is.

Such a structure according to the invention has self-testing capabilities with respect to the built-in Josephson integrated circuit 31. In other words,
The operation test of the Josephson integrated circuit 31 to be tested is performed using the board 2.
The Josephson test circuit 32 and the Josephson integrated circuit 31 to be tested are placed under the same conditions.
The Josephson integrated circuit under test 3 operates at extremely high speed.
1 can be extracted by a Josephson test circuit 32 on the same board which can also operate at extremely high speed.

Therefore, by analyzing the test data, for example, if an incorrect calculation result is obtained from the Josephson integrated circuit 31 under test for a certain pattern of logic signals applied from the Josephson test circuit 32, Is it possible to judge that the Josephson integrated circuit 31 under test is defective, and conversely, to judge that the Josephson integrated circuit 31 under test that has obtained all correct logical operation results for all predetermined test data/bumps is good? can.

Then, regarding the board 2° on which the Josephson integrated circuit 31 to be inspected, which has been determined to be good in this way, is mounted, follow the dividing line 23 that can be set between the first area 21 and the second area 22. If the first and second regions 21 and 22 are divided using a known and existing suitable cutting means such as a mechanical cutter or a laser beam, a portion of the substrate having an area corresponding to the first region 21 (the same (using the reference numeral 21) is now a separate Josephson integrated circuit chip 21. It can also be cut out as a good chip 21.

If only the good integrated circuit chips 21 are selected in this way, then the cut out good products can be processed using a rigid mounting method such as the flip-chip bonding method, which is provided for well-known and existing semiconductor integrated circuits. Each mounting bonding pad 34 of the Josephson integrated circuit chip 21 can be used to immediately mount it on a computer system board.

However, if the device that analyzes the test data extracted by the Josephson integrated circuit 32 is, for example, a semiconductor device placed outside a cryogenic environment, typically a semiconductor computer, the operating speed of the Josephson integrated circuit 32 It is also possible that the data processing speed of the test circuit 32 cannot be kept up. In such a case, it is desirable that the Josephson test circuit 32 built into the board 20 has an internal circuit configuration as shown in FIG.

That is, the Josephson test circuit 31 includes a memory 41 that stores an instruction program necessary for testing the Josephson integrated circuit 32 under test, a processor 42 that operates according to this instruction program, and a A register file 43 that stores test data obtained from the inspection Josephson integrated circuit 32 side, and an interface circuit that sends the test data stored in this register file 43 to an external analysis device (not shown). (110 circuits) 44, the test data collected at high speed can be serial-parallel-converted in the register file 43 having a shift register configuration, for example, and then sent to an external analysis device. Therefore, even if the external analysis device is an existing semiconductor analysis device, such as a semiconductor computer, which operates slower than Josephson integrated circuits, it can be used to test the Josephson integrated circuit 31 under test. It can be used for data analysis. Of course, as also shown in FIG. 2, a suitable I10 circuit 45 may be inserted between the Josephson test circuit 32 and the Josephson integrated circuit 31 to be tested.

Further, if the Josephson integrated circuit 31 to be inspected is determined to be a good product as a result of the test, the Josephson integrated circuit 31 is Naturally, the wiring La 33 between the Josephson test circuit 32 and the Josephson integrated circuit 31 to be tested is also disconnected, and the second leaning wall 22 carrying the Josephson test circuit 31 that has finished its role can be discarded.

However, each substrate 20 shown in FIG. 1 may be one of a plurality of substrates originally formed on - wafers. In other words, each substrate 20 shown in FIG. After forming a plurality of Josephson integrated circuit structures of The quality of each circuit may be determined individually.

However, if one considers that a plurality of Josephson integrated circuits are originally constructed on one wafer, the structure shown in FIG. 3 is also reasonable.

That is, the substrate 20 is a single wafer 50, on which a plurality of rectangular regions, in this case twenty rectangular regions arranged in five columns and four rows, are formed, one of which (as shown in the figure). In this case, the area (stippling in the upper left corner) is the second area 2 with respect to Figure 1.
A circuit corresponding to the Josephson test circuit 31 shown in the first diagram is constructed here, and the remaining 19 rectangular areas correspond to the first area 21. A circuit corresponding to the Josephson integrated circuit 31 to be tested shown in FIG. 1 is constructed here.

Of course, the Josephson test circuit 32 is preferably connected to all 19 Josephson integrated circuits 31 to be tested via strip lines so that all 19 Josephson integrated circuits 31 to be tested can be tested. is taken. However, as schematically shown in the figure, for other Josephson integrated circuits 31 to be tested other than those adjacent to the Josephson test circuit 32, The wiring system may be such that the connection is made indirectly through wiring formed in the Josephson integrated circuit to be inspected.

Even in such a structure, although not shown in FIG. 3, test bonding pads necessary for testing are provided only in the Josephson test circuit 32, similar to the first embodiment shown in FIG. Although not shown in FIG. 3, each first region 21. If the bonding pads formed on... are used for later mounting and are not used during testing, the bonding pads formed on each of the Josephson integrated circuits 31,... to be tested will be A non-destructive test can be performed in a working environment, and as a result, the test board is equipped with the Josephson integrated circuit that was judged to be a good product among the multiple ones formed on the same wafer 50 (same substrate 20). First area 21. . . . can be used as good quality Josephson integrated circuit chips after being divided from the wafer 50.

As is clear, as a mere comparison, the structure shown in the third figure can reduce the utilization efficiency of the wafer 50 and the manufacturing cost compared to the structure shown in the first figure. This is because a single Josephson test circuit is shared by a plurality of Josephson integrated circuits to be tested (in reality, there can be many more than shown).

Of course, the internal configuration shown in the second figure can also be adopted for the Josephson test circuit 31 in the structure shown in the third figure, and if there are any problems with the wiring on the wafer 50, Not only can the positions of the test circuits 32 be changed, but also the number of test circuits 32 can be increased. In other words, one Josephson test circuit 32 does not test all the Josephson integrated circuits 31 to be tested, but each of the plural Josephson test circuits 31 tests several Josephson integrated circuits to be tested. The wiring may be such that the circuit 31 is tested. Even in that case, it is clear that at least the most basic structural requirements of the gist of the present invention are satisfied, and therefore such an integrated circuit structure also falls within the scope of the present invention.

Incidentally, if the purpose is simply to prevent damage to the bonding pads provided in the Josephson integrated circuit portion, for example, as shown schematically in FIG. Josephson integrated circuit under test 3
It is also conceivable to attach a pair of bonding pads i34, 34° to each signal line terminal of 1 for testing and for mounting.

However, this method greatly impedes the high placement density of bonding pads and requires an area larger than that required for the Josephson integrated circuit 31, so it is difficult to say that it is a method that can be adopted practically. Furthermore, since the test circuit has to be an external circuit, the task of real-time high-speed testing under actual operating conditions cannot be achieved. Therefore, as described above, the significance of providing the Josephson test circuit 32 and the Josephson integrated circuit 31 to be tested so as to be divisible into different regions 21 and 22 in the present invention is based on these points. There are also big ones.

Finally, although a Josephson integrated circuit was assumed in the above embodiment, there is talk of realizing semiconductor integrated circuits that can operate at much higher speeds than existing semiconductor integrated circuits in the future. The present invention can also be effectively applied to the inspection of such ultra-high-speed semiconductor integrated circuits.

[Effects] According to the present invention, compared to semiconductor integrated circuits that operate at room temperature, which can be measured using relatively simple measurement means, they are inherently difficult to measure due to their extremely high operating speed and extremely low temperature environment. Non-destructive testing of Josephson integrated circuit chips, which has been considered difficult, and even real-time testing if necessary, makes it possible to select non-defective chips.

Once it is possible to sort out good chips in this way, the rest can be achieved using flip-chip technology, which is a well-known semiconductor technology.
Since many good chips can be automatically mounted on a common system board using the bonding method, high-density packaging can be realized even in Josephson computers.

Also, depending on the configuration of the built-in Josephson test circuit, test data can be temporally processed and analyzed by an external analyzer with a slow operating speed, so if the analysis software is mature, is obtained similarly.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a Josephson integrated circuit structure with self-testing functionality as one embodiment constructed in accordance with the present invention. FIG. 2 is an explanatory diagram of one preferred circuit configuration of a Josephson test circuit provided in a Josephson integrated circuit structure. FIG. 3 is a schematic diagram of a Josephson integrated circuit structure as another embodiment of the present invention. FIG. 4 is a schematic diagram of a Josephson integrated circuit structure assuming that one pair of bonding pads is provided for testing and one for mounting. FIG. 5 is an explanatory diagram of a conventional test method using a micro blow μ bottle. It is. 35 is a test bonding pad provided in the second area; 41 is an instruction program bonding pad;
42 is a processor, 43 is a register file, 44 is an interface circuit, and 50 is a wafer.

Claims (8)

[Claims] (1) An integrated circuit to be inspected to be judged for pass/fail and a test circuit for testing the integrated circuit to be tested and extracting test data are placed side by side on the same board in different areas that can be separated from each other: and , test bonding pads necessary for connecting the test circuit to an external analysis device are provided only in the area where the test circuit is provided on the board. Integrated circuit structure. (2) The substrate is a wafer: While there are a plurality of integrated circuits to be inspected formed on different areas on the wafer so as to be able to be separated from each other, there is only one test circuit formed on the wafer. The integrated circuit structure having a self-testing function according to claim 1, wherein: the one test circuit extracts the test data from each of the plurality of integrated circuits to be tested. body. (3) The integrated circuit structure having a self-testing function according to claim 1 or 2, wherein the integrated circuit to be tested and the test circuit are both Josephson circuits that operate in a cryogenic environment. . (4) The test circuit includes a memory that stores an instruction program necessary for the test operation, a processor that operates according to the instruction program, and a register file that stores test data obtained in accordance with the operation of the processor. and an interface circuit for sending the test data stored in the register file to an external analysis device. An integrated circuit structure with. (5) An integrated circuit to be inspected to be judged for pass/fail and a test circuit for testing the integrated circuit to be tested and extracting test data are arranged side by side on the same board in different regions that can be separated from each other: and , test bonding pads necessary for connecting the test circuit to an external analysis device are provided on the board only in the area where the test circuit is provided, and: the test obtained by the test operation is performed. By analyzing data, the area in which the integrated circuit determined to be good is formed is divided from the area in which the test circuit is formed, and a new independent integrated circuit chip is created. Method for selecting good integrated circuit chips. (6) The substrate is a wafer: While there are a plurality of integrated circuits to be inspected formed on different areas on the wafer so that they can be divided from each other, there is only one test circuit formed on the wafer. 6. The method for selecting good integrated circuit chips according to claim 5, wherein: the one test circuit extracts the test data from all of the plurality of integrated circuits to be tested. (7) The method for selecting good integrated circuit chips according to claim 5 or 6, wherein the integrated circuit to be inspected and the test circuit are both Josephson circuits that operate in an extremely low temperature environment. (8) The test circuit includes a memory that stores an instruction program necessary for the test operation, a processor that operates according to the instruction program, and a register file that stores test data obtained in accordance with the operation of the processor. The integrated circuit non-defective chip according to claim 5, further comprising: an interface circuit for sending the test data stored in the register file to an external analysis device. Sorting method.