JPH02238645A - Wafer - Google Patents

Abstract

PURPOSE:To prevent a pad from being destroyed by an increase in the number of contact operations with pads by a prober by a method wherein mutually identical sides of adjacent chips are faced and pads for test use with which the prober of a tester is brought into contact between faced identical pieces are installed outside chip regions. CONSTITUTION:In a wafer 1 on which many chips 2a to 2i constituting a large- scale integrated circuit have been formed, the many chips 2a to 2i are arranged in such a way that mutually identical sides of adjacent chips are faced; pads 4 for test use with which a prober of a tester is brought into contact between faced identical pieces are installed outside chip regions. The pads 4 for test use are wired and connected to pads 3 formed at outer edge parts inside the chips 2a to 2i. Thereby, even when the number of contact operations with the pads 4 by the prober at a test operation of the chips 2a to 2i are increased, the pads 3 inside the chips 2a to 2i are not damaged; it is possible to avoid that the chips become defective when the pads are destroyed; a sorting-out operation of good products can be executed smoothly; a yield can be enhanced.

Description

[Detailed description of the invention] Field of application of "industry"] The present invention relates to a wafer on which large-scale integrated circuits are fabricated,
In particular, it relates to chip sorting technology on wafers.

[Prior Art] Conventionally, in a chip selection test for large-scale integrated circuits, a blooper of a tester is brought into contact with a pad provided at the outer edge of the chip to apply an input signal, and the output signal is observed. We are sorting out defects.

[Issues to be solved] In the conventional chip selection test described above, as the number of pins in large-scale integrated circuits increases, multiple types of test data are required, and it is difficult to contact the prober pads by performing multiple tests. By increasing the number of times, the possibility of damaging the pad increases, and if the pad is destroyed and closed, of course it becomes impossible to perform a sorting test on the chip in question, which may cause a decrease in product yield. There was a problem.

The present invention has been made in view of the above-mentioned problems, and provides a method for performing a chip selection test without bringing the tester's prober into contact with the pads provided on the outer edge of the chip. With the goal.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a wafer on which a large number of chips constituting a large-scale integrated circuit are mounted, such that the large number of chips are arranged so that the same sides as adjacent chips face each other. A test pad is provided outside the chip area and a prober of a tester is brought into contact between the same opposing pieces, and the test pad and a pad provided at the outer edge of the chip are connected by wiring. be.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view schematically showing a wafer according to an embodiment of the present invention, and in the figure, reference numeral 1 indicates wafers 2a to 21 are chips.

Each of the chips 2a to 21 is arranged such that adjacent chips face each other with the same side facing each other, and each of the four corresponding sides (A side,
B side, C side, D side) are arranged to face each other. Further, each of the chips 2a to 21 is provided with a pad 3 in its area along the A side, the B side, the C side, and the D side.

In the figure, 4 is a test pad, and the side of the chip facing each other,
For example, it is provided on the wafer between the opposing sides D and D of the chips 2a and 2b, and between the pads 3 and 3 of the chips 2a and 2b, respectively. Tests 1 are provided vertically and horizontally outside the area of the chips 2a to 21 to be fabricated on the wafer 1.
・The chip 2 is connected to the pad 4 via the inter-pad connection wiring 5.
The pads 3 provided on the outer edges of a to 21 are connected to realize pad duplication.

The chip sorting test for the wafer in this example is for chips 2a to 2.
The prober of the tester is brought into contact with the test pads 4 provided in the vertical and horizontal directions outside the area 1, an input signal is applied, and the output signals are observed to determine whether the pads are good or bad. For this reason, when the number of bins in large-scale integrated circuits increases and a large number of tests are performed, 1 pro/he 1 is used as the test pad 4.
The pads 3 in the areas of the chips 2a to 21 are less likely to be destroyed even if the pads 3 are contacted many times.

[Effects of the Invention] As explained above, the present invention provides a wafer on which a large number of chips constituting a large-scale integrated circuit are mounted, so that the large number of chips are arranged so that the same sides as adjacent chips face each other. A test pad is provided outside the chip area for contacting the prober of the tester between the same opposing pieces, and a wiring connection is made between the test pad and a pad provided at the outer edge of the chip. Even if the number of times the properper contacts the pad during chip testing increases, the pad within the chip area will not be destroyed.
This has the effect that it is possible to avoid defective chips due to pad breakage, and to expect smooth selection of non-defective products and improvement in yield.

In addition, by arranging adjacent chips so that the same side faces each other and sharing the test pads between them, back drive can be prevented from occurring against the adjacent chips of the chip under test that the tester's blooper comes into contact with. There is also the effect that element deterioration due to this can be prevented.

[Brief explanation of drawings]

FIG. 1 is a plan view schematically showing a wafer according to an embodiment of the present invention. 1: Wafer 2a-21: Chip 3: Pad inside the chip 4: Test pad 5: Connection wiring between pads A-D: Chip side agent Patent attorney Kihei Watanabe

Claims (1)

[Claims] A test in which, on a wafer with a large number of chips constituting a large-scale integrated circuit, the large number of chips are arranged so that the same side faces the adjacent chips, and a prober of a tester is brought into contact between the same opposing pieces. A wafer characterized in that a test pad is provided outside a chip area, and the test pad and a pad provided at an outer edge inside the chip are connected by wiring.