JPS6235644A - Semiconductor device - Google Patents

Abstract

PURPOSE:To facilitate the analysis of improper functioning by a method wherein a chip containing a main function as well as a testing circuit is installed in one and the same wafer in addition to chips accommodating main functions only. CONSTITUTION:Chips 1 are without a testing circuit 4 and each of chips 2 is provided with one or more signal terminal pads 5 exclusively for testing. A chip 2 is arranged adjacent to a plurality of chips 1. Connection is established, by wiring patterns 6 located on the wafer, between the circuits to be tested that are contained in a given quantity 'n' of the chips 1 and the testing circuits that are in the chips 2 that are respectively in contact with said quantity 'n' of the chips 1. This facilitates the analysis of improper functioning.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated device in which test circuits are mounted as independent chips on a wafer.

[Conventional technology]

Conventionally, this type of semiconductor integrated device, as shown in FIG.
Test circuits are provided on each chip, and all chips on the wafer are under the same conditions.

The functions of this test circuit are, firstly, to discover defects in the functions installed on the chip, and secondly, to easily check the function using test signals from an external tester such as an automatic tester. It is.

Therefore, in addition to the circuits that realize the functions originally installed on the chip and pads for extracting signals to the outside, there are also circuits that realize the above test functions and signal exchangers with external test equipment such as automatic testers. There is a mixture of pads used to remove dirt.

[Problem that the invention seeks to solve]

This type of semiconductor integrated device has two purposes: first, to discover defects in the functions installed on the chip, and second, to easily detect problems with test signals from an external tester such as an automatic tester. Since it is equipped with a test circuit that also allows for functional confirmation, the circuit becomes large-scale and a certain area of the chip layout is exclusively used for testing. Further, signal terminal pads and pins dedicated to the test circuit are also provided. Such a test circuit that has the above-mentioned first purpose is not necessary at the product stage.Therefore, realizing the test circuit on the chip that becomes the product and providing dedicated pads increases the chip size and increases the number of signal terminals. In addition, the test circuit itself is subject to the above constraints, making it difficult to incorporate all necessary and sufficient functions, which makes failure analysis difficult. Was.

[Failure to solve the problem]

The present invention relates to a semiconductor integrated device in which a plurality of chips are mounted on a single wafer, and each chip has the same test circuit for the purpose of analyzing the operation of the circuit, in which the test circuit is removed from the chip. A collection of chips) is defined as a first chip group, a dedicated signal terminal pad is provided on the test circuit, a chip with one or more chips mounted on one chip is defined as a second chip, and a plurality of second chips are defined as a second chip group. The circuit under test is arbitrarily arranged with respect to the first chip group, and exists in any n chips of the first chip group, and the circuit under test exists in a second chip adjacent to any n chips. The test circuit is connected to the test circuit using a wiring pattern on the wafer.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment of the present invention.

] is a chip that performs the main function, 3 is a circuit section mounted on the chip that implements the main function, 2 is a chip with a mixed main function and test circuit, 4 is a test circuit section, and 5 is a signal accompanying the test circuit. Terminal pads 6 indicate wiring.

This is handled by using chip 1 as the product chip, but in order to analyze defects in the product chip, chip 2 is used, which is equipped with the test function of 4.5 and mixed with the main function of 3.

〔Effect of the invention〕

As explained above, the present invention involves mounting a chip with a test circuit in addition to the main function on the same wafer, in addition to a chip with the main function, and the scale of the test function incorporated in the test circuit depends on the size of the product chip. Since there is no effect on

On the other hand, the product chip has the effect of reducing the chip size and the number of signal terminals by eliminating the test circuit for failure analysis, which is an unnecessary function from the viewpoint of the original product function.

[Brief explanation of drawings]

FIG. 1 shows a layout diagram of a chip of the present invention. ]... Product chip, 2... Chip with test function. 3...Main function section, 4...Test circuit section,
Death: Pad for test signal terminal, 6: Wiring pattern. FIG. 2 shows a chip layout diagram of a conventional example. 1...Chip with mixed main function and test function,
2...Main function section, 3...Test circuit section,
4...Signal terminal section, butt...Wiring pattern.

Claims (1)

[Claims] A first chip group that does not have a test circuit, and a second chip that has a test circuit along with a dedicated signal terminal pad on the same wafer, and a plurality of the second chips are included in the first chip group. A circuit under test that is arbitrarily arranged for the circuit and exists in any n chips of the first chip group;
1. A semiconductor device characterized in that each semiconductor device is connected to a test circuit existing in a second chip adjacent to each other by a wiring pattern on a wafer.