JP2942353B2 - Test method and test circuit for semiconductor device - Google Patents
Test method and test circuit for semiconductor deviceInfo
- Publication number
- JP2942353B2 JP2942353B2 JP2339888A JP33988890A JP2942353B2 JP 2942353 B2 JP2942353 B2 JP 2942353B2 JP 2339888 A JP2339888 A JP 2339888A JP 33988890 A JP33988890 A JP 33988890A JP 2942353 B2 JP2942353 B2 JP 2942353B2
- Authority
- JP
- Japan
- Prior art keywords
- test
- output
- pad
- pads
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 この発明は、多出力半導体IC等のテスト方法およびテ
スト回路に関する。Description: TECHNICAL FIELD The present invention relates to a test method and a test circuit for a multi-output semiconductor IC and the like.
従来の技術 従来、半導体装置をテストする場合は、第４図に示す
ように、半導体チップ１上の各種パッド（電源パッド8,
入力パッド6,接地パッド7,出力パッド３）に、プロービ
ング針２を１つのパッドに１本ずつ接触させてテストを
行っていた。2. Description of the Related Art Conventionally, when testing a semiconductor device, as shown in FIG.
The test was performed by bringing the probing needles 2 into contact with the input pad 6, the ground pad 7, and the output pad 3) one by one.
発明が解決しようとする課題 ところで、上記の従来の半導体装置のテスト方法は、
１つのパッドに１本のプロービング針を接触させて測定
を行っており、例えばLCDドライバのような非常に多出
力な半導体装置の場合は、出力パッドの数が多くなり、
また実装密度を上げるためパッドの大きさも小さくなっ
ているため、プロービングのための目合わせ精度やプロ
ービング針の位置精度，プロービング針間隔精度，プロ
ービング針のジオメトリー精度がきびしくなりテストが
困難となっている。Problems to be Solved by the Invention By the way, the above-mentioned conventional method for testing a semiconductor device is
The measurement is performed by bringing one probing needle into contact with one pad. For example, in the case of an extremely multi-output semiconductor device such as an LCD driver, the number of output pads increases.
In addition, the size of the pads has been reduced to increase the mounting density, so the alignment accuracy for probing, the positioning accuracy of the probing needle, the accuracy of the spacing between the probing needles, and the accuracy of the geometry of the probing needles have become severe, making testing difficult. .
つまり、従来のテスト方法はプロービング針を立てら
れる精度には限界があるため、非常に多出力の半導体装
置は、テストが非常に困難になるという欠点があった。In other words, the conventional test method has a limit in the accuracy with which the probing needle can be set, so that a semiconductor device having a very high output has a drawback that the test becomes very difficult.
課題を解決するための手段 （１） この発明のテスト方法は、出力パッド数個ごと
に出力パッドより面積の大きいテストパッドを配置し、
複数の出力パッドの信号をテストパッドにシリアル出力
させて出力パッドの信号を測定する方法である。Means for Solving the Problems (1) In the test method of the present invention, a test pad having a larger area than an output pad is arranged for every several output pads,
This is a method of serially outputting signals of a plurality of output pads to a test pad and measuring the signals of the output pads.
（２） この発明のテスト回路は、複数個の出力パッド
の信号を出力パッドより面積の大きいテストパッドにシ
リアル出力させるもので、例えばトランスミッションゲ
ートと出力バッファとで構成されている。(2) A test circuit according to the present invention serially outputs signals from a plurality of output pads to a test pad having a larger area than the output pads, and includes, for example, a transmission gate and an output buffer.
作用 上記の構成によると、半導体の出力パッド数が非常に
多くて出力パッドの大きさが小さくても、テストパッド
配置することにより、プロービングが容易になりテスト
が可能となる。Operation According to the above configuration, even if the number of output pads of the semiconductor is very large and the size of the output pads is small, arranging the test pads facilitates probing and enables testing.
実施例 以下、この発明について図面を参照して説明する。Hereinafter, the present invention will be described with reference to the drawings.
第１図はこの発明の一実施例の測定方法およびテスト
回路について説明するための半導体チップの平面図であ
る。半導体チップ１の周辺には出力パッド３が多数配置
されており、さらに出力パッド３が９個ごとにテストパ
ッド４が１個，テスト回路５が１組配置されている。９
個の出力パッド３の信号はテスト回路に入り、シリアル
にテストパッド４に信号が送られており、テストパッド
４の信号はプロービング針２によって外部からテストさ
れる。テストパッド４の大きさと間隔は従来の出力数の
少ない半導体装置の場合とほぼ同じであるため容易にテ
ストができる。FIG. 1 is a plan view of a semiconductor chip for explaining a measuring method and a test circuit according to one embodiment of the present invention. A large number of output pads 3 are arranged around the semiconductor chip 1, and one test pad 4 and one set of test circuits 5 are arranged for every nine output pads 3. 9
The signals of the output pads 3 enter the test circuit, and the signals are sent to the test pads 4 in serial. The signals of the test pads 4 are externally tested by the probing needle 2. Since the size and interval of the test pad 4 are almost the same as those of the conventional semiconductor device having a small number of outputs, the test can be easily performed.
第２図はこの発明の一実施例のテスト回路の回路図で
ある。９個の出力バッド１〜９はそれぞれトランスミッ
ションゲートTMに接続され、トランスミッションゲート
TMの出力はテストパッドに接続されている。C1〜C9はト
ランスミッションゲートTMのコントロール信号であり、
▲▼〜▲▼はそれぞれ反転信号である。Bufは
出力バッファである。FIG. 2 is a circuit diagram of a test circuit according to one embodiment of the present invention. Each of the nine output pads 1 to 9 is connected to a transmission gate TM,
The output of TM is connected to the test pad. C1 to C9 are control signals of the transmission gate TM,
▲ ▼ to ▲ ▼ are inversion signals, respectively. Buf is an output buffer.
第３図は第２図のテスト回路の動作をタイムチャート
で表したもので、出力パッド１〜９の信号がシリアルに
テストパッド４に出力されている状態を示している。信
号C1〜C9がタイムチャートのような信号であるとする
と、信号C1〜C9の内highレベルになった時間だけ対応す
るトランスミッションゲートTMがONして、テストパッド
４に信号が出力されている。このように出力パッド１〜
９の信号がテストパッド４にシリアルに出力される。FIG. 3 is a time chart showing the operation of the test circuit shown in FIG. 2, and shows a state in which signals from output pads 1 to 9 are serially output to test pad 4. Assuming that the signals C1 to C9 are signals as shown in a time chart, the transmission gate TM corresponding to the high level of the signals C1 to C9 is turned on, and the signal is output to the test pad 4. Thus, the output pads 1 to
9 is serially output to the test pad 4.
発明の効果 以上説明したように、この発明は出力パッド数個ごと
にテストパッドを配置したことにより、半導体ICの出力
パッド数が非常に多くなっても、プロービング針が容易
にテストパッドに接触できるため、テストが容易になる
効果がある。Effect of the Invention As described above, according to the present invention, by arranging test pads for every several output pads, even if the number of output pads of the semiconductor IC becomes very large, the probing needle can easily contact the test pads. This has the effect of facilitating the test.
第１図はこの発明のテスト方法を説明するためにテスト
時の様子を示した半導体チップの平面図である。 第２図はこの発明のテスト回路の回路図である。 第３図は第２図のタイムチャートである。 第４図は従来のテスト方法を説明するためにテスト時の
様子を示した半導体チップの平面図である。 １……半導体チップ、 ２……プロービング針、 ３……出力パッド、 ４……テストパッド、 ５……テスト回路、 ６……入力パッド、 ７……接地パッド、 ８……電源パッド、 C1〜C9……トランスミッションゲートコントロール信
号、 ▲▼〜▲▼……C1〜C9の反転信号、 TM……トランスミッションゲート、 Buf……出力バッファ。FIG. 1 is a plan view of a semiconductor chip showing a state during a test for explaining a test method of the present invention. FIG. 2 is a circuit diagram of the test circuit of the present invention. FIG. 3 is a time chart of FIG. FIG. 4 is a plan view of a semiconductor chip showing a state at the time of a test for explaining a conventional test method. 1 ... Semiconductor chip, 2 ... Probing needle, 3 ... Output pad, 4 ... Test pad, 5 ... Test circuit, 6 ... Input pad, 7 ... Ground pad, 8 ... Power pad, C1 ~ C9: Transmission gate control signal, ▲ ▼ to ▲ ▼: Inversion signal of C1 to C9, TM: Transmission gate, Buf: Output buffer.
Claims (2)
ごとに出力パッドより面積の大きいテストパッドを有
し、出力パッドの信号をテストパッドにシリアル出力す
ることにより、出力パッドの信号を測定する半導体装置
のテスト方法。In a multi-output semiconductor IC, a test pad having a larger area than an output pad is provided for every several output pads, and a signal of the output pad is serially output to the test pad to measure a signal of the output pad. Test method for semiconductor device.
と出力パッド数個ごとに設けた出力パッドより面積の大
きいテストパッドとの間に複数のトランスミッションゲ
ートと出力バッファとで構成され、出力パッドの信号を
テストパッドにシリアル出力させるテスト回路。2. A multi-output semiconductor IC comprising a plurality of transmission gates and an output buffer between several output pads and a test pad having a larger area than the output pads provided for each of the output pads. A test circuit that serially outputs a signal to the test pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2339888A JP2942353B2 (en) | 1990-11-30 | 1990-11-30 | Test method and test circuit for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2339888A JP2942353B2 (en) | 1990-11-30 | 1990-11-30 | Test method and test circuit for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04207050A JPH04207050A (en) | 1992-07-29 |
| JP2942353B2 true JP2942353B2 (en) | 1999-08-30 |
Family
ID=18331760
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2339888A Expired - Lifetime JP2942353B2 (en) | 1990-11-30 | 1990-11-30 | Test method and test circuit for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2942353B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102005038895B4 (en) * | 2005-08-17 | 2012-01-19 | Infineon Technologies Ag | Circuit with capacitive elements |
-
1990
- 1990-11-30 JP JP2339888A patent/JP2942353B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04207050A (en) | 1992-07-29 |
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