JPS6218037Y2 - - Google Patents

Description

[Detailed description of the invention] This invention conducts various electrical tests (hereinafter referred to as P/W tests) using an automatic prober connected to an IC tester on integrated circuits formed on a semiconductor substrate before scribing during the integrated circuit manufacturing process. The present invention relates to a structure of a semiconductor substrate suitable for reliably performing the following.

Conventionally, electrical tests related to this type of integrated circuit are
In this method, the probe of an automatic prober connected to an IC tester successively contacts bonding pads made of thin metal films within multiple integrated circuits fabricated on a semiconductor substrate.

In this case, if the probe attached to the probe card of the automatic prober causes poor contact with the bonding pad inside the integrated circuit due to aging, deformation, or abrasion of the tip, the integrated circuit may actually be a good product. The drawback was that the IC tester judged the IC to be defective and damaged the surface of the IC, destroying the good integrated circuit.

In addition, when using the above method to inspect for poor contact with the probe during a test of an integrated circuit on a semiconductor substrate, it is recommended to stop the test and replace the semiconductor substrate under test with another semiconductor substrate with a thin metal film coated on its entire surface. A lot of time was wasted as the probe had to be brought into contact.

An object of the present invention is to provide a method for solving the above-mentioned drawbacks by providing a metal thin film pad as a probe contact failure detection means on a semiconductor substrate on which a conventional integrated circuit is formed. Furthermore, semiconductor substrates for manufacturing integrated circuits in the future will have larger diameters, and as the chip area of integrated circuits increases, the number of bonding pads will increase, and contact failures of probes during P/W tests must be extremely reduced. .

In conventional P/W testing, the probe of an automatic prober may have poor contact with the bonding pad in the integrated circuit under test on the semiconductor substrate due to a defect in the probe itself or poor alignment of the semiconductor substrate under test. There were quite a few things that could happen.

According to the present invention, a plurality of integrated circuits are formed on the surface of a semiconductor under test, and by providing a metal thin film pad of uniform thickness that occupies the area of at least one of the integrated circuits, failures occur during a P/W test. If this occurs continuously, contact failure due to an inconvenience of the probe can be diagnosed by pressing the probe of an automatic prober against the metal thin film pad and using a contact failure detection program prepared in advance.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a conventional semiconductor substrate 2 on which a plurality of integrated circuits 1 are formed on the surface of the substrate.

FIG. 2 shows a semiconductor substrate 4 which occupies one integrated circuit area and has a metal thin film 3 having the same thickness as a bonding pad, which serves as a probe contact failure detection means according to the present invention.

3 to 6 are cross-sectional views illustrating an example of detecting probe contact failure during a P/W test using the semiconductor substrate shown in FIG. 2, and FIG. 3 is a probe card. 5 is a diagram in which an integrated circuit under test 9, which is a part of the semiconductor substrate 4 fixed to a stage 7 which is a part of an automatic prober, has been moved directly below a probe 6 attached to the probe 5. FIG.

FIG. 4 is a diagram in which the stage 7 has been raised and is in contact with the probe 6 and a number of bonding pads 8 formed within the integrated circuit under test 9 which is a part of the semiconductor substrate 4. In FIG.

FIG. 5 is a diagram showing poor contact between the probe 6 and the ponding pad 8 due to deformation of the probe 6. That is, when the contact failure shown in FIG. 5 occurs, the IC tester connected to the probe 6 determines that the integrated circuit under test 9 is a defective product even if it is a good product, and then the stage 7 moves and sequentially tests the IC tester. The integrated circuit under test will be tested.

If defective products occur continuously in this way, a contact failure detection program prepared in advance in the IC tester is activated, and a metal thin film pad 3 is placed directly under the probe 6 as a contact failure detection means, as shown in FIG. After moving the stage 7 so that If the pin is used as a detection pin and the voltage from the drive pin is detected, poor contact between the probe 6 and the metal thin film pad 3 can be detected.

As explained above, the present invention reduces contact failures caused by aging, deformation, and abrasion of the tip of the probe by configuring the semiconductor substrate shown in FIG. 2 as shown in FIG. This can be detected during the W test, and has the effect of significantly reducing the possibility of erroneously determining a good integrated circuit as defective.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing a conventional semiconductor substrate on which a plurality of integrated circuits are fabricated. FIG. 2a is a plan view showing a semiconductor substrate having a probe contact failure detection pad according to an embodiment of the present invention, and FIG. 2b is a sectional view thereof. 3 to 6 are cross-sectional views showing an embodiment constructed using the semiconductor substrate shown in FIG. 2. In each figure, 1... integrated circuit, 2... conventional semiconductor substrate, 3... metal thin film pad, 4... semiconductor substrate having probe contact failure detection pad, 5...
Probe card, 6... Probe, 7... Stage, 8...
...bonding pad, 9...integrated circuit under test.

Claims (1)

[Scope of utility model registration request] In a semiconductor substrate in which a large number of semiconductor chips having substantially the same size are arranged in a matrix, each semiconductor chip having an integrated circuit formed therein, a part of the substrate is provided with a plurality of semiconductor chips having substantially the same size as the semiconductor chips. A thin metal film having a substantially uniform thickness is provided, and the thin metal film is formed by contacting the plurality of probes of a prober for electrical testing of the integrated circuit with the thin metal film. A semiconductor substrate, characterized in that it is used to detect poor contact between the plurality of probes and bonding pads in the integrated circuit by checking the conductivity between them.