JPH03142852A - Manufacture of wafer scale semiconductor device - Google Patents

Abstract

PURPOSE:To remove power source wirings for defective blocks and unused blocks by wiring blocks having the same functions with buses, wiring various functional blocks with buses, and performing functional tests of the functional blocks. CONSTITUTION:A power source wiring 23 is provided for supplying power sources to a circuit part 21. A block bus line 8 is provided for connecting the same terminals of a plurality of blocks having the same function which are arranged on a wafer 1 through the bus. A system bus line 12 is provided for interface with blocks having the different functions. A contact area 24 is provided for connecting the block bus line 8 and the system bus line 12. The functional blocks 2A-2D, 3A-3D, 4A-4D and 5A-5D having those constitutions are arranged in a matrix pattern. Thus the interfaces among a plurality of many kinds of the blocks are provided. Then, the probes of a testing pad 22 are pushed, and the functional tests for the individual blocks are conducted. The power source wirings for the defective and unused blocks are removed based on the results of the tests.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing a semiconductor device equivalent to a wafer-scale IC, a wafer-scale semiconductor device that can manufacture a wafer-scale IC by wiring so as to easily avoid defective functional blocks in a short period of time. The aim is to provide a manufacturing method for manufacturing various types of functional blocks and I/O blocks on a wafer depending on the functional content.
/O buffer group, a process of forming a plurality of these functional blocks and I/O buffer groups and arranging them in a matrix, bus wiring between the same functional blocks, and further wiring between different functional blocks. wafer-scale IC manufacturing process, which includes the steps of bus wiring, a step of performing a functional test for each block after the above process steps, and a step of removing power supply wiring of defective and unused blocks based on the results of the functional test. Configure to manufacture.

[Industrial application field]

The present invention relates to a method for manufacturing a wafer-scale semiconductor device, and more particularly, to a method for manufacturing a wafer-scale IC.

In recent years, there has been a demand for large-scale ICs that have multiple functions. For this reason, there is a wafer-scale IC that creates a system on the wafer by forming various functional chips on one wafer and selecting and wiring only good products.

For example, the performance of computer systems has improved dramatically, and the amount of memory used per system has increased to the point where the amount of memory used per system has increased.

For this reason, there is a growing need for memory systems that have an increasingly large capacity and are compact. Wafer-scale memory was developed as a functional device that satisfies these demands and specifically fills the performance and price gap between main memory and disks. Research on wafer-scale memory has been conducted for more than 20 years, but it has not yet been put to practical use. For practical application, it is especially necessary to develop defect avoidance technology.

Even now, it is difficult to eliminate the occurrence of defects in silicon wafers and during wafer processing, even though efforts are being made to make clean rooms cleaner, process materials more purified, and process equipment less damaged. Therefore, in wafer memories that treat the entire wafer as one device, the presence of defects is unavoidable, and defect avoidance techniques are essential.

[Conventional technology]

In a wafer scale IC, a single wafer is divided into a large number of functional blocks, and wiring is provided between these blocks to form one device using the entire wafer. In such a wafer scale tC, malfunctions may occur in functional blocks during the process process, so multiple functional blocks are prepared in advance and the functional blocks are tested after the process process to identify non-defective functional blocks. The system is configured by wiring between the two.

[Problem to be solved by the invention]

However, in such conventional manufacturing methods for wafer-scale semiconductor devices, since the quality of functional blocks is irregular, it is difficult and complicated to perform wiring for each wafer accordingly. This poses a problem in that it takes a long time and increases costs.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for manufacturing a wafer-scale semiconductor device that can manufacture a wafer-scale IC by wiring such that defective functional blocks can be easily avoided in a short period of time.

[Means to solve the problem]

In order to achieve the above object, the method for manufacturing a wafer-scale semiconductor device according to the present invention divides the wafer into various types of functional blocks and I/O buffer groups according to their functional contents, and divides these functional blocks and I/O buffer groups into A process of forming multiple blocks and arranging them in a matrix, a process of bus wiring between the same functional blocks, and a process of bus wiring between different functional blocks, and a functional test for each block after the above process steps. A wafer scale IC is manufactured by the process of removing defective and unused block power supply wiring based on the results of a functional test.

[Effect]

In the present invention, bus wiring is provided between the same functional blocks, and bus wiring is also provided between each functional block.

Thereafter, a functional test is performed on each functional block, and the power supply wiring of defective blocks and unused blocks is removed according to the test results, thereby completing the wiring process of the wafer scale IC.

Therefore, even if the functional blocks are irregular in whether they are good or bad, it is sufficient to simply remove the power supply wiring of the bus at the corresponding location, so that defective functional blocks can be easily avoided and the wiring process can be shortened.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

1 to 3 are diagrams showing an embodiment of the method for manufacturing a wafer scale semiconductor device according to the present invention. FIG. 1 is a plan view of a wafer. In this figure, 1 is a wafer, 2 to 5 are functional block groups, and each functional block group 2 to 5 is A, B.
Various types of functional blocks 2A to 2D are denoted by symbols SC and D.

3A to 3D, 4A to 4D, and 5A to 5D. The multiple types of functions include, for example, the functional block group 2 corresponds to a CPU, the functional block 3 corresponds to a ROM, etc.

6 is an I/O buffer group, four I/O buffers 6A~
It has 6D. Also, 7 is the band area, 8-11
12 to 15 are block path lines connecting the same functional blocks, and system path lines 12 to 15 connecting different functional blocks.

Next, the manufacturing process of the above wafer scale IC will be explained.

First, functional block groups 2 to 5 and I/O buffer group 6 are arranged in the X direction (horizontal direction in the figure) on wafer 1, and each group has a plurality of identical functional blocks (four in this example). Therefore, each block is arranged in a matrix, and the system is divided into blocks in the Y direction (vertical direction in the figure).
It will be held in

Next, lines where the same signals between blocks having the same function overlap are bus-connected by block path lines 8 to 11, respectively. Similarly, between different functional blocks and I/O
The buffer group 6 is bus-connected by system path lines 12 to 15, and is further connected to each pad in the pad area 7.

Here, the details of one functional block are shown as shown in FIG. To explain the functional block 2A as an example, the functional block 2A includes a circuit section 21 that performs logical operations,
Test pad 22 for use in the primary test of the circuit section 21
, a power supply wiring 23 for supplying power to the circuit section 21 , and the block path line 8 for connecting the same terminals of the same functional blocks arranged on the wafer 1 via a bus.
, the system path line 12 for interfacing with different functional blocks, and the block path line 8.
and a contact area 24 for connecting the system path line 12. Functional blocks 2A to 2D, 3A to 3D, 4A to 4D, and 5A to 5 having such configurations
By arranging D in a matrix, it is possible to interface between various types and a plurality of blocks.

When the above process steps are completed, a probe is pressed against the test pad 22 to perform a functional test (corresponding to the next test) for each block, and based on the test results, the power supply of defective and unused blocks is determined. Remove wiring. Specifically, as shown in the details of the power supply wiring 23 in FIG.
It has power supply branch lines 33 and 34 that respectively supply power to the circuit section 21, and contact holes 35 and 36 that connect these. Note that 37 and 38 are contact holes that connect the power supply branch lines 33 and 34 to the circuit section 21. The power supply branches 33, 34 are formed as the top layer and are made of aluminum. For defective and unused blocks, the power supply lines 33 and 34 are connected to the laser or FIB (Fo
The aluminum wiring is removed using a cused ion beast (Ion Beast) device or the like, thereby stopping the power supply.

Therefore, the output buffers of defective and unused blocks are in a high impedance state. In this way, one good product is selected from each functional block group 2 to 5 and I/O buffer group 6, and the wafer scale IC is
A device is manufactured, and then tests are conducted to complete the device.

In this way, in this embodiment, the functional blocks 2A to 2D, 3
Even if the pass/fail status of A to 3D, 4A to 4D, and 5A to 5D is irregular, it is sufficient to simply remove the power supply wiring of the defective or unused blocks, so defective functional blocks can be easily avoided. The wiring can be completed, the wiring process for wafer scale ICs can be completed in a short period of time, and costs can be reduced.

In addition, if it is possible to distinguish used blocks as well as defective and unused blocks, for example, if one of the test pads 22 is provided with an empty block and a marking is applied thereto, it is possible to distinguish between used and unused blocks. When a block inside breaks down, it can be easily repaired by rewiring the power supply wiring to the good block. For rewiring, for example, the pattern cut points PI and Pg in FIG. 3 are backfilled with the FIB device.

〔Effect of the invention〕

According to the present invention, even if good and defective functional blocks are irregular, wiring can be performed by simply removing the power supply wiring, and the wiring process can be performed easily and in a short period of time.

[Brief explanation of the drawing]

1 to 3 are diagrams showing an embodiment of the method for manufacturing a wafer-scale semiconductor device according to the present invention, in which FIG. 1 is a plan view of the wafer-scale IC, and FIG. 2 is a detailed view of one functional block thereof. FIG. 3 is a diagram showing the power supply wiring of one of the functional blocks. 1... Wafer, 2-5... Functional block group, 2A-2D, 3A-3D, 4A-4-5D... Functional block, 6...・I/O buffer group, 6A to 6D... Bow/O buffer, 7...
Pad area, 8-11...Block pass line, 12-15
...System pass line, 21...Circuit section, 22...Test pad, 23...Power supply wiring, 24...Contact area , 31.32... Main power line, 33.34... Power branch line, 35-38... Contact hole. 1 A - A plan view of the wafer scale Ic of the embodiment. Fig. 1. A diagram showing details of one functional block of the embodiment.

Claims (1)

[Claims] A wafer is divided into various types of functional blocks and I/O buffer groups according to their functional contents, and a plurality of these functional blocks and I/O buffer groups are formed and arranged in a matrix. The process of bus wiring between the same functional blocks and the bus wiring between different functional blocks; The process of performing functional tests for each block after the above process steps. and a step of removing power supply wiring from unused blocks.