JPH0685019A - Semiconductor wafer and its testing method - Google Patents

Abstract

PURPOSE:To provide a semiconductor wafer and a testing method therefor in which even a semiconductor chip with bonding pads in a short pitch can be tested without damaging respective bonding pads formed on the semiconductor chip. CONSTITUTION:A semiconductor wafer 1 is constructed in a manner that corresponding pads 3 with a scribe area 4 in between are connected individually and electrically by means of conductive layers 5 on respective semiconductor chips 2 arranged therein and the respective layers 5 are provided with testing pads 8 that are electrically connected with the respective layers 5 are arranged in zigzag. When the wafer 1 is subject to testing, respective testing probes is brought into contact with not the pads 3 on the objective chip 2 but respective testing pad 8 formed in the area 4 in the periphery thereof.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer on which a large number of semiconductor chips are arranged and an inspection method for the semiconductor wafer.

[0002]

2. Description of the Related Art Generally, in the manufacture of semiconductor chips, so-called dicing is performed in which a large number of semiconductor chips are arrayed on a single semiconductor wafer and then the wafer is divided into individual semiconductor chips. Usually, before this dicing, a semiconductor chip in a wafer state is functionally inspected, and defective products are marked.

FIG. 4 shows the semiconductor chip 12 in a wafer state. A scribe region 14 is formed between the arranged semiconductor chips, and this region is deeply cut by a diamond blade or the like rotating at high speed to perform dicing.

On the upper part of each semiconductor chip 12, a bonding pad 13 is formed along each side of the chip. In the functional test, a large number of wafer probe pins 15 radially oriented from the probe holding plate having the opening toward the center of the opening are brought into contact with the corresponding bonding pads 13 (FIG. 2). reference). A power supply and an input signal are supplied from the test apparatus through the wafer probe pin 15, and the output signal thereof is detected.

The tip portion of the wafer probe pin 15 is preliminarily positioned corresponding to the arrangement position of the bonding pads 13, and the semiconductor wafer 10 is raised and lowered with respect to the probe holding plate, whereby the bonding pad 13 is moved. And the wafer probe pin 15 are contacted and separated. After the inspection of one semiconductor chip 12 is completed,
The target is moved to another adjacent semiconductor chip 12, the same inspection is repeated, and the inspection is sequentially performed on all the semiconductor chips on the wafer.

[0006]

In this inspection, as shown in FIG. 5 (a), the wafer probe pins 15 are pressed against the bonding pad 13 with a constant force and come into contact with each other. Since the wafer probe pin 15 has relatively poor elasticity, the bonding pad 13 on the semiconductor chip 12 may be deformed by being pressed by the tip of the wafer probe pin 15 as shown in FIG. 5B. . Such a deformation of the bonding pad 15 is
In the wire bonding process to be performed later, contact failure was caused, which was one of the causes of defective semiconductor chips.

On the other hand, in order to promote high-density integration of this semiconductor chip, it is desirable that a large number of bonding pads can be arranged within a certain range. However, the minimum pitch of the tip portions of the wafer probe pins for inspecting this semiconductor chip is about several tens of μm due to restrictions such as the thickness of each probe pin. That is, when the pitch of the bonding pads is shorter than this interval, it cannot be measured by the conventional device, which is one of the problems in shortening the pitch of the bonding pads.

The present invention has been made to solve these problems, and a semiconductor wafer and a semiconductor wafer inspection capable of performing an inspection without damaging each bonding pad formed on a semiconductor chip. The purpose is to provide a method.

Another object of the present invention is to provide a semiconductor wafer and a semiconductor wafer which can be inspected by such a conventional inspection method using a wafer probe pin as well as a semiconductor chip having bonding pads formed at a pitch shorter than the conventional one. To provide the inspection method.

[0010]

A semiconductor wafer according to the present invention is a semiconductor wafer in which a large number of semiconductor chips are arrayed and formed. Each arrayed semiconductor chip has a plurality of pads, and the adjacent semiconductor chips are adjacent to each other. Pads facing each other across the scribe region of the chip are electrically connected to each other by a conductive layer formed in the scribe region, and are electrically connected to each conductive layer for inspection. The pads are arranged in a staggered arrangement in the scribe area.

Further, in the semiconductor wafer inspection method according to the present invention, for each pad of a semiconductor chip arrayed and formed on the semiconductor wafer, each inspection probe provided corresponding to each pad array position is provided. In the method of inspecting a semiconductor wafer in which the semiconductor wafers are in contact with each other, in the semiconductor wafer, adjacent pads of a semiconductor chip, which are opposed to each other with a scribe region therebetween, are electrically connected to each other by a conductive layer formed in the scribe region. Connected to, and
The inspection pads electrically connected to each of the conductive layers are formed in a zigzag pattern in the scribe area, and the inspection pads electrically connected to the pads of the semiconductor chip to be inspected are , The inspection probes are brought into contact with each other to perform the inspection.

[0012]

The inspection pad formed in the scribe area of the semiconductor wafer is in a state of being electrically connected to the pads of the semiconductor chips located on both sides of the inspection pad through the conductive layer, and is used as a common pad during the inspection. it can. Therefore, when the inspection probe is brought into contact with the inspection pad, the inspection probe is connected to the pad of the semiconductor chip. Further, since the inspection pads are arranged in a zigzag pattern, they act so that the intervals between the adjacent inspection pads become wide.

On the other hand, in the method of inspecting a semiconductor wafer, since the semiconductor wafer is configured in this way, when performing the inspection, the semiconductor wafer is formed not in the pad on the corresponding semiconductor chip but in the scribe region around it. When each inspection probe is brought into contact with each of the inspection pads thus formed, each inspection probe is connected to each pad of the corresponding semiconductor chip.

[0014]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is an enlarged view of a part of the semiconductor wafer 1, in which a large number of semiconductor chips 2 are regularly arranged. Four bonding pads 3 are formed on the periphery of the upper portion of each semiconductor chip 2 along each side at regular intervals. The bonding pads 3 formed along the respective sides are electrically connected to the bonding pads 3 formed along the opposite sides via the conductive layer 5 with the scribe region 4 shown by hatching in the drawing interposed therebetween. ing. In addition, the inspection pads 8 arranged in a zigzag pattern are individually formed on each conductive layer 5 in the scribe region 4, and the conductive layers 5 and the inspection pads 8 are electrically connected to each other. Is. The conductive layer 5 is formed by using an aluminum wiring layer on the wafer, but in addition to this, a polysilicon layer, a semiconductor conductive layer formed by ion implantation, or the like which extends over the scribe region 4 is used. Layers can also be used, and any layer can be used as long as the opposing bonding pad and inspection pad can be electrically connected to each other.

Next, the semiconductor wafer 1 thus formed
The inspection method will be described. As shown in FIG. 2, this inspection is performed by a probe holding plate 7 having a large number of wafer probe pins 6 radially oriented toward the center of the opening.
Using. The tip portion of the wafer probe pin 6 is prepositioned corresponding to the array position of the pads to be inspected, and the semiconductor wafer 1 is raised and lowered with respect to the probe holding plate 7 so that each semiconductor chip 2 The pad and the wafer probe pin 6 are contacted and separated.

FIG. 3 is an enlarged view of one semiconductor chip to be inspected among the semiconductor chips 2 arranged on the semiconductor wafer 1. As described above, the tip of the many wafer probe pins 6 radially directed from the probe holding plate 7 is brought into contact with each corresponding pad to perform the inspection. In the present inspection method, the bonding pad 3 is used.
Instead of directly contacting the wafer probe pin 6 with the wafer probe pin 6, the wafer probe pin 6 is brought into contact with each bonding pad 3 and each inspection pad 8 electrically connected through the conductive layer 5. Therefore, the tip portion of the wafer probe pin 6 is formed in advance by being positioned corresponding to the arrangement position of each inspection pad 8. When the tip portions of the respective wafer probe pins 6 arranged in this manner are brought into contact with the corresponding inspection pads 8, the wafer probe pins 6 are attached to all the bonding pads 3 of the semiconductor chip to be inspected. Is in an electrically connected state. Therefore, the power supply and the input signal can be supplied from the test device through each wafer probe pin 6, and the output signal thereof can be detected to perform the function test as in the conventional case.

By arranging the wafer probe pins 6 in such a state, the distance between the tip portions of the wafer probe pins becomes equal to the distance between the inspection pads 8 arranged in a staggered manner (1 ₁₎ ( (See FIG. 3). Thus, for example, the distance l ₁ of the test pads 8, when set to the minimum pitch of the distal ends of the wafer probe pins 6 also, on the semiconductor chip 2, a short pitch l ₂ than the pitch l ₁ The bonding pads 3 can be arranged. This action makes it possible to set the gap between the bonding pads on the semiconductor chip 2 to be further shorter as the adjacent inspection pads are arranged apart from each other.

Therefore, by carrying out the inspection using the semiconductor wafer thus formed, the wafer probe pins are also used for the bonding pads arranged at the minimum pitch between the tips of the wafer probe pins 6. It becomes possible to inspect.

After performing a functional inspection on all the semiconductor chips 2 and marking defective products, the scribe area 3 is diced to obtain the individual semiconductor chips 2.
Split into. By this dicing, the inspection pad 8 formed in the scribe region 3 is cut and removed, the conductive layer 5 is also cut, and the electrical connection between the bonding pads is also eliminated. At this time, in the outer peripheral portion of each of the divided semiconductor chips 2, a part of the conductive layer 5 connected to the bonding pad is left together with the uncut portion of the scribe region 4. Even in the bonding process, there will be no hindrance.
It can be handled like a conventional semiconductor chip.

[0020]

As described above, in the semiconductor wafer according to the present invention, the pads facing each other across the scribe region are electrically connected to each other, and are electrically connected to the respective conductive layers individually. Since the inspection pads are formed, the pads on the semiconductor chip and the inspection pads are
It can be used as a common pad at the time of function inspection, and since the inspection pads are arranged in a zigzag pattern, the distance between the adjacent inspection pads can be widened as compared with the semiconductor chip-shaped pads. . Furthermore, since the inspection pad and the conductive layer formed in the scribe area are cut and removed in the subsequent dicing step, there is no hindrance in the subsequent die bonding step or wire bonding step. It can be handled in the same manner as the semiconductor chip of.

Further, in the method of inspecting a semiconductor wafer, each inspection probe is brought into contact with each inspection pad formed in the scribe region around the semiconductor chip, not with the pad on the corresponding semiconductor chip. It is possible to carry out a functional test without damaging each bonding pad formed on the semiconductor chip.

Further, since the inspection pads to be in contact with the inspection probes are arranged in a staggered pattern, the inspection pads can be arranged at a wider interval than the intervals of the pads on the semiconductor chip, which makes it possible to minimize the inspection probes. Compared to the pitch
A semiconductor chip in which pads are arranged at a short pitch can be reliably inspected by a method using an inspection probe.

[Brief description of drawings]

FIG. 1 is a schematic plan view showing an enlarged part of a semiconductor wafer according to the present invention.

FIG. 2 is a schematic perspective view showing an inspection state.

FIG. 3 is a schematic plan view showing a method of inspecting a semiconductor chip.

FIG. 4 is a schematic plan view showing a part of a semiconductor wafer in an enlarged manner to show a conventional semiconductor wafer and its inspection method.

5 (a) and 5 (b) are schematic side views showing a bonding pad in contact with a wafer probe pin.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor wafer, 2 ... Semiconductor chip, 3 ... Bonding pad, 4 ... Scribe area, 5 ... Conductive layer, 6 ... Wafer probe pin, 8 ... Inspection pad.

Claims (2)

[Claims] 1. In a semiconductor wafer in which a large number of semiconductor chips are formed in an array, each of the arrayed semiconductor chips has a plurality of pads, and the adjacent semiconductor chips face each other across a scribe region. The pads are electrically connected to each other by the conductive layer formed in the scribe area, and the inspection pads electrically connected to the conductive layers are arranged in a zigzag pattern in the scribe area. A semiconductor wafer formed by 2. A method of inspecting a semiconductor wafer, which comprises inspecting each pad of a semiconductor chip arrayed and formed on a semiconductor wafer by contacting each test probe provided corresponding to the array position of each pad. In this semiconductor wafer, in the adjacent semiconductor chips, the pads facing each other across the scribe region are electrically connected individually by the conductive layer formed in the scribe region, and The inspection pads electrically connected to the layers are formed in a staggered arrangement in the scribe region, and the inspection pads electrically connected to the pads of the semiconductor chip to be inspected. On the other hand, a method of inspecting a semiconductor wafer is characterized in that the inspection probes are brought into contact with each other to perform inspection.