JP2996219B2 - Test method and test jig for semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test method and a test jig for a semiconductor device, and more particularly, to a test method and a test method for a semiconductor device using a dual type probe guard capable of simultaneously performing a test on two chips. About jigs.

[0002]

2. Description of the Related Art Generally, in testing a chip formed on a wafer, a probe card having a plurality of probe needles capable of contacting a chip pad is used. The chip is tested by making contact.

FIG. 2 shows an example of a probe card 1
FIG. 3 is a top view showing a configuration of a single type probe card capable of performing a test on one chip.

As shown in FIG. 2, a single-type probe card has a plurality of probe needles (wirings) 100 that can respectively contact the pads of a chip.

In recent years, in the evaluation of characteristics of semiconductor devices,
As chip size shrinks, time is required to be shortened. For this reason, instead of a single type probe card, a dual type probe card capable of simultaneously testing two chips is used. .

FIG. 3 is a diagram for explaining an example of a method for testing a semiconductor device using a conventional dual-type probe card. FIG. 3A shows an example of a configuration of a conventional dual-type probe card. FIG. 2B is a top view showing a configuration of a wafer for explaining a test method using the probe card shown in FIG.

FIG. 3 shows a conventional probe card.
As shown in (a), two single type probe cards 110a and 110b are arranged adjacently so that one diagonal line in each probe card becomes one straight line.

FIG. 3 shows a method for testing a semiconductor device using the probe card configured as described above.
This will be described with reference to FIG.

Here, as shown in FIG. 3, it is assumed that semiconductor devices (chips) to be tested in this conventional example are arranged in a matrix of m columns × n rows.

In the test of the semiconductor device shown in FIG. 3B, first, the probe card 110a is placed on the chip W (-1,0) on the wafer, and the probe card 110b is placed on the chip W (0,1). The probe cards are arranged so as to be respectively located at the positions of the chips W (-1,0),
Perform a test on W (0,1).

Next, the probe card 110a is
On (0,0), the probe card 110b
The probe card is moved so as to be positioned on (1, 1) respectively, whereby the chips W (0, 0), W
A test for (1, 1) is performed.

Next, the probe card 110a is
On (1,0), the probe card 110b is
The probe card is moved so as to be positioned on (2, 1), respectively, so that the chips W (1,0), W
A test for (2,1) is performed.

Thereafter, the probe card 110a is placed on the chip W (m, 0), and the probe card 110b is placed on the chip W (m, 0).
(M + 1,1), thereby moving the probe card one chip at a time in the positive direction of the row until a test is performed on chips W (m, 0) and W (m + 1,1), Perform tests on each.

After performing tests on the chips W (m, 0) and W (m + 1,1), the probe card is moved by two chips in the positive direction of the row, and the probe card 110a is moved to the chip W (m, 2). Above, the probe cards 110b are respectively positioned on the chips W (m + 1, 3), so that tests on the chips W (m, 2) and W (m + 1, 3) are performed.

Next, the probe card 110a is
The probe card is moved on (m-1, 2) so that the probe card 110b is located on the chip W (m, 3), whereby the chip W (m-1, 2,),
A test is performed on W (m, 3).

Thereafter, the probe card 110a is located on the chip W (-1,2) and the probe card 110b is located on the chip W (0,3), whereby the chips W (-1,2), W Until the test for (0, 3) is performed, the probe card is moved one chip at a time in the negative direction of the row, and the test is performed for each.

After conducting a test on the chips W (-1,2) and W (0,3), the probe card is moved by two chips in the positive direction of the row, and the probe card 110a is moved to the chip W (-1,, 3). 4) The probe card 110b is positioned above the chip W (0,5), thereby performing a test on the chips W (-1,4), W (0,5).

Thereafter, the probe card is moved again in the positive direction of the row, and a test is performed on each chip.

As described above, the probe card is placed one chip at a time in the row direction and two chips in the column direction.
The chips are moved by the number of chips, and the test is sequentially performed on all the chips in the wafer.

[0020]

However, in the conventional device shown in FIG.
Since the length of the wiring at the connection portion between the probe card 10a and the probe card 110b is longer than the other portions and the interval between the wirings is narrower, the resistance value of the wiring is different from that of the single type probe card. Will be.

Therefore, there is a problem that it cannot be correlated with the characteristic evaluation of the semiconductor device using the single type probe card.

Another problem is that the characteristics of the chip measured before assembling the semiconductor device and the characteristics of the chip measured after assembling differ greatly from each other, so that the characteristics cannot be accurately evaluated.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art. Even when a dual-type probe card having two jigs is used, the characteristics of the semiconductor device can be improved. An object of the present invention is to provide a test method and a test jig for a semiconductor device, which can perform an evaluation accurately and can correlate with a case where a single type probe card is used.

[0024]

According to the present invention, there is provided a semiconductor device comprising: a plurality of semiconductor devices arranged in a matrix; and two jigs arranged on the semiconductor device. A semiconductor device test method for testing a semiconductor device, wherein a first jig, one of the jigs, is disposed on a certain semiconductor device, and a second jig, a second jig, is provided. The jig is disposed on a semiconductor device which is located at a position where the first jig is arranged and jumps away from the semiconductor device on which the first jig is arranged.

Further, the first and second jigs are sequentially moved in a row direction and a column direction of the matrix, and the first jig and the second jig are respectively transferred to the plurality of semiconductor devices. By arranging at least one of them sequentially, a test is performed on all the semiconductor devices.

Further, the movement of the first and second jigs in the row direction and the column direction is performed by the same amount.

The movement of the first and second jigs is as follows.
The method is characterized in that the process is performed for each semiconductor device in the keima jumping direction, and for each semiconductor device in the vertical direction.

Further, as the first and second jigs, are formed on a wafer, each of the dual type of probe card having a plurality of probe needles can be contacted to the pads of the chip to be the semiconductor device Single part
It is characterized by using minutes .

Further, the semiconductor device has first and second jigs for testing a semiconductor device, and two jigs are arranged on the semiconductor device for a plurality of semiconductor devices arranged in a matrix. A test jig for a semiconductor device for testing a semiconductor device, wherein the first jig and the second jig are arranged so as to be positioned at a distance from each other on the semiconductor device. It is characterized by the following.

Further, the first and second jig is formed on a wafer, each of the dual type of probe card having a plurality of probe needles can be contacted to the pads of the chip to be the semiconductor device It is characterized by being a single part .

(Operation) In the present invention configured as described above, a test of a semiconductor device is performed by arranging two jigs on the semiconductor device for a plurality of semiconductor devices arranged in a matrix. Is performed, one of the jigs is separated from the semiconductor device on which the other jig is arranged by one semiconductor device and the position of the Keima jump which is one of the left and right diagonally forward positions The two jigs are sequentially moved in the row direction and the column direction of the matrix in a state of being arranged on the semiconductor device, and at least one of the two jigs is sequentially arranged on each of the plurality of semiconductor devices. Test is performed on all the semiconductor devices.

Here, since the two jigs are arranged so as to be separated from each other at the position of the Keima jump, there are portions on the jigs where the lengths of the wires are different and where the intervals between the wires are narrow. It does not exist.

Further, since the movement of the jig in the row direction and the movement in the column direction can be performed by the same amount, respectively, the movement control does not become complicated.

[0034]

Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 1A and 1B are diagrams for explaining an embodiment of a method for testing a semiconductor device according to the present invention, wherein FIG. 1A shows an example of a configuration of a test jig, and FIG. FIG. 3 is a top view showing a configuration of a wafer for explaining a test method using the test jig shown in FIG.

As shown in FIG. 1A, the test jig according to the present embodiment has two single type probe cards 1.
Arrangements 0a and 10b are located at positions where the probe card 10b is moved by two chips in the positive direction of the row and one chip in the positive direction of the column with respect to the probe card 10a. It is the configuration that was done.

FIG. 1 shows a method of testing a semiconductor device using the probe card configured as described above.
This will be described with reference to FIG.

Here, as shown in FIG. 1, in the semiconductor device (chip) to be tested in this embodiment,
It is assumed that they are arranged in a matrix of m columns × n rows.

When testing the semiconductor device shown in FIG. 1B, first, the probe card 10a is placed on the chip W (-2,0) on the wafer, and the probe card 10b is placed on the chip W (0,1). The probe cards are arranged so as to be positioned at the respective positions, so that the chips W (−2, 0), W
A test for (0, 1) is performed.

Next, the probe card 10a is
On (-1, 0), the probe card 10b is
The probe cards are moved so as to be positioned on (1, 1) respectively, whereby the chips W (-1, 0), W
A test for (1, 1) is performed.

Next, the probe card 10a is
On (0,0), the probe card 10b
The probe cards are moved so as to be positioned on (2, 1) respectively, whereby the chips W (0,0), W
A test for (2,1) is performed.

Thereafter, the probe card 10a is
On (m, 0), the probe card 10 b
+2, 1), respectively, so that the chip W
Until the test for (m, 0) and W (m + 2, 1) is performed, the probe card is moved by one chip in the positive direction of the row, and the test is performed for each.

After performing the test on the chips W (m, 0) and W (m + 2,1), the probe card is moved by two chips in the positive direction of the row, and the probe card 10a is moved to the chip W (m, 2). On top, the probe card 10b is
(M + 2, 3), thereby testing chips W (m, 2) and W (m + 2,3).

Next, the probe card 10a is
On (m-1, 2), the probe card 10b is
The probe cards are moved so as to be positioned on (m + 1, 3), respectively, whereby the chip W (m−1,3) is moved.
2), a test is performed on W (m + 1, 3).

Thereafter, the probe card 10a is
On (-2, 2), the probe card 10b is
(0,3), respectively, so that chip W
Until the test for (−2, 2), W (0, 3) is performed, the probe card is moved by one chip in the negative direction of the row, and the test is performed for each.

After performing the test on the chips W (−2, 2) and W (0, 3), the probe card is moved by two chips in the positive direction of the row, and the probe card 10 a 4) The probe card 110b is positioned above the chip W (0,5), thereby performing a test on the chips W (-2,4), W (0,5).

Thereafter, the probe card is moved in the positive direction again, and a test is performed on each chip.

As described above, the probe card is mounted one chip at a time in the row direction and two chips in the column direction.
The row is moved by the number of chips, and the test is sequentially performed on all the chips in the wafer.

In the present embodiment, since there are no portions on the probe card where the lengths of the wires are different or portions where the intervals between the wires are narrow, it is possible to perform the same characteristic evaluation as that of the single type probe card. it can. The time required for the characteristic evaluation is longer than that of the conventional device shown in FIG. 3, for example, when chips are arranged in a matrix of m columns × n rows by the test time for n / 2 chips. It just becomes.

[0050]

As described above, in the present invention,
When a semiconductor device is tested by arranging two jigs on a plurality of semiconductor devices arranged in a matrix, one of the jigs is used.
The two jigs are sequentially moved in the row direction and the column direction of the matrix in a state where one jig is arranged on the semiconductor device at a jump position with respect to the semiconductor device on which the other jig is arranged. Since at least one of the two jigs is sequentially arranged on each of the plurality of semiconductor devices, the test is performed on all the semiconductor devices. There is no portion where the interval between them is narrow, and therefore, the characteristic evaluation equivalent to the characteristic evaluation of the semiconductor device by one jig can be performed in a shorter time than when one jig is used. In addition, it is possible to correlate with the case where one jig is used.

Since the movement of the two jigs in the row direction and the movement in the column direction can be performed by the same amount, it is possible to evaluate the characteristics of all the semiconductor devices without using complicated movement control. it can.

[Brief description of the drawings]

FIGS. 1A and 1B are diagrams illustrating an embodiment of a semiconductor device test method according to the present invention, in which FIG. 1A illustrates an example of a configuration of a test jig, and FIG. FIG. 4 is a top view showing a configuration of a wafer for describing a test method using a test jig.

FIG. 2 is a top view showing a configuration of a single-type probe card capable of performing a test on one chip as an example of the probe card.

3A and 3B are diagrams for explaining an example of a method of testing a semiconductor device using a conventional dual-type probe card, and FIG. 3A is a diagram illustrating a configuration example of a conventional dual-type probe card; FIG. 2B is a top view showing the configuration of the wafer for explaining the test method using the probe card shown in FIG.

[Explanation of symbols]

 10a, 10b probe card

Claims (7)

(57) [Claims] 1. A method of testing a semiconductor device, comprising: arranging two jigs on a plurality of semiconductor devices arranged in a matrix to test the semiconductor device. When the first jig, which is one of the jigs, is arranged on a certain semiconductor device, the second jig, which is the remaining jig, is replaced with the first jig. A method for testing a semiconductor device, wherein the semiconductor device is disposed on a semiconductor device which is located at a position where the semiconductor device jumps from the semiconductor device. 2. The method for testing a semiconductor device according to claim 1, wherein the first and second jigs are sequentially moved in a row direction and a column direction of the matrix, and the first and second jigs are sequentially moved to each of the plurality of semiconductor devices. A test method for a semiconductor device, comprising: arranging at least one of a first jig and a second jig in order to test all the semiconductor devices. 3. The semiconductor device test method according to claim 2, wherein the first and second jigs are moved in the row direction and in the column direction by the same amount. How to test the equipment. 4. The method for testing a semiconductor device according to claim 3, wherein the movement of the first and second jigs is performed one semiconductor device at a time in the Keima jumping direction and in a direction perpendicular to the semiconductor device. A test method for a semiconductor device, wherein the test is performed for each of two semiconductor devices. 5. A method of testing a semiconductor device according to any one of claims 1 to 4, as the first and second jigs, are formed on a wafer,
Dual tie having a plurality of probe needles each capable of contacting a pad of a chip serving as the semiconductor device
A method for testing a semiconductor device, wherein each single part of a probe card of a semiconductor device is used. 6. A semiconductor device comprising: first and second jigs for testing a semiconductor device, wherein two jigs are arranged on the semiconductor device with respect to a plurality of semiconductor devices arranged in a matrix, respectively. A test jig for a semiconductor device for testing a semiconductor device, wherein the first jig and the second jig are arranged so as to be located at a jump position from each other on the semiconductor device. A test jig for a semiconductor device, comprising: 7. The test jig for a semiconductor device according to claim 6, wherein the first and second jigs are formed on a wafer, and each of the first and second jigs is in contact with a pad of a chip serving as the semiconductor device. A test jig for a semiconductor device, which is a single part of a dual type probe card having a plurality of probe needles.