JP3843624B2 - Semiconductor integrated circuit device and method for assembling semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device and method for assembling semiconductor integrated circuit device Download PDF

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JP3843624B2
JP3843624B2 JP33718498A JP33718498A JP3843624B2 JP 3843624 B2 JP3843624 B2 JP 3843624B2 JP 33718498 A JP33718498 A JP 33718498A JP 33718498 A JP33718498 A JP 33718498A JP 3843624 B2 JP3843624 B2 JP 3843624B2
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integrated circuit
semiconductor integrated
circuit device
electrode region
electrode
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JP2000164620A (en
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誠司 得能
洋 水野
英雄 石井
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06153—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry with a staggered arrangement, e.g. depopulated array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体集積回路装置の高密度化、高集積化の実現に関し、特に、高集積化された半導体集積回路装置の電気特性検査とパッケージへのボンディングを確実に実現し、かつ半導体集積回路装置の面積をできる限り小さくするためのパッド配置と、前記パッドを用いた半導体集積回路装置の電気的特性検査及び組立を行なう方法を提供するものである。
【０００２】
【従来の技術】
近年の半導体集積回路装置の微細化技術の向上に伴って、半導体集積回路装置の内部と、外部との電気信号のやりとりを行なうための、信号の方向制御や、保護回路が搭載されているパッドセルの面積も大幅に削減され、このパッドセルのピッチも小さなものになってきている。
【０００３】
半導体製造技術における微細化技術は、急激なスピードで向上しているが、電極パッドにピンを当て電気特性を評価する検査技術や、電極パッドを介して半導体集積回路とパッケージとの接続を実現するボンディング技術においては、半導体製造技術におけるほどの微細化を実現することが困難になって来ている。
【０００４】
実際に、電気特性検査においては、検査装置における、検査用ピンの太さや、動きのずれの精度より決定される領域を電極パッドが確保する必要があるし、パッケージへのボンディングにおいても、リード線の幅などによって定義される領域を電極パッドが確保する必要がある。
【０００５】
これらの課題を回避する方法の１つとして、特開平５−２０６３８３号公報では、電極パッドとは別に、電気特性検査用のパッドを設け、これを半導体ウエハー上で半導体集積回路の領域外のダイシングライン上に配置することで、電気特性検査用パッドの検査を実行するために必要となる面積を確保し、ＩＣの検査、測定の容易化を図っている。
【０００６】
【発明が解決しようとする課題】
しかしながら、特開平５−２０６３８３号公報では、電気特性の検査に関しては、確実に行なうことを可能としているが、従来技術で述べているように、ボンディングのためにも電極パッドに一定の幅を持たせる必要があり、この問題を解決することができない。
【０００７】
また、現在では半導体ウエハーの加工技術の向上にともない、ダイシングラインも微細化が進み、ダイシングラインの幅よりも電気特性検査用パッドの幅の方が大きくなることがあり、特開平５−２０６３８３号公報の手法を用いても、ＩＣの検査の容易化と半導体集積回路の面積の最適化を両立することが困難になっている。
【０００８】
また、検査、及びボンディングを行なうために必要最低限の大きさを持った電極パッドを用いて、電気的特性検査を行ない、この後同一の電極パッドを用いてボンディングを行なおうとした時に、ボンディングに失敗することがある。これは、特性検査をする時に当てた検査ツールのプローブピンが電極パッドにプローブ痕を残すことが大きな原因となっている。
【０００９】
電極パッドの微細化が進むにつれて、電極パッドの大きさに対するプローブ痕の占める割合が大きくなり、ボンディングの際にこのプローブ痕が、圧着や、合金形成の妨げとなるからである。
【００１０】
【課題を解決するための手段】
上記の課題を解決し、確実な電気的特性の検査とボンディングを実現するために、電極パッドの面積を拡大して検査後のプローブ痕の面積割合を削減し、ボンディングを可能とするか、電極パッドを性能検査用の部分と、ボンディング用の部分にわけて作成しボンディング用のパッドの部分にはプローブ痕が残らないようにする方法が考えられる。
【００１１】
本特許では、確実な検査とボンディングを実現し、さらに面積の最適化を図るために、電極パッドは、プローブする場所とボンディングする場所を変更することとし、さらに、半導体集積回路装置の面積の最適化を図るために、検査のルール、ボンディングのルール、パッドピッチといった情報に基づいて電極パッド配置を決定する。
【００１２】
【発明の実施の形態】
以下、本発明の実施の形態について、図を用いて説明する。
【００１３】
（第１の実施の形態）
第１の実施の形態では、請求項１に係る発明について図を用いて説明する。
【００１４】
図１は本発明に基づいて設計された、電極用パッド及び、この電極パッドの配置の一例である。１０１は、パッドセル本体であり、保護回路、制御論理が搭載されている。
【００１５】
領域１０９は検査用の電極領域であり、領域１１０はボンディング用の電極領域である。ここで、領域１１０は、ボンディング装置の精度やボンディングワイヤーの物理的な要因から、ボンディングを確実に行なえるようにするために最小の大きさが規定されており、その幅は１０５となる。また、領域１０９は、検査装置の精度や、検査用のピン物理的特性から、検査が確実に行なえるように最小の大きさが規定されており、その幅は１０６となる。
【００１６】
電極パッド１０２は前記領域１０９と領域１１０を隣接あるいは一部を重ね合わせて配置することにより形成されている。本発明では、電極パッド１０２の様に凸型になることが一つの特徴である。
【００１７】
１０３はボンディング用パッド領域１１０の中心位置であり、１０４は性能検査用パッド領域１０９の中心位置となっている。
【００１８】
ここで、間隔１０７は、ボンディング用パッド領域１１０の中心１０３と、検査用パッド領域１０９の中心１０４の距離の最小幅を示している。この距離は、特性検査の際にプローブ用ピンを置いた後のパッド上にピンのプローブ痕が残っていても、この間隔だけを維持しておけば確実にボンディングを行なえることを保証するための距離で、今回の発明にとって最も重要な距離となる。このように、間隔１０７を定義することにより、領域１０９と領域１１０をそれぞれの中心１０３と１０４が間隔１０７以上の距離を維持したまま重ね合わせ配置したとしても検査とボンディングを確実に実現できることが保証できるので、電極パッドの削減の効果も期待できる。
【００１９】
図２は、本発明に基づいて設計された電極用パッド及び、この電極用パッドの配置の一例である。図２は、図１においてボンディング用の電極領域の幅１０５と検査用の電極領域の幅１０６同一の値の時の状態である。このような状態では、ボンディング用電極領域の中心２０３と検査用電極領域の中心２０４には区別がなくなるためボンディング及び、検査を行なう際に、どちらを使うかの選択が可能となり、効率の良い検査、ボンディングが可能となる。
【００２０】
（第２の実施の形態）
第２の実施の形態では、請求項２に係る発明について図を用いて説明する。
【００２１】
図３は、本発明で実現されるテスト方法の一例を示している。
ここで、３０１は検証のプローブピンであり、これをテスト用電極領域の中心１０４に接触させ電気的特性検査を実行する。この時検査用プローブピンのピン間隔の精度、検査装置のプローブピン移動に関する精度、検査用プローブピンの電極パッドに対する進入角等の要因により、ピン３０１の電極パッド１０２への接触場所は中心位置１０４からはずれるが、検査用電極領域１０９が幅１０６を確保しているので確実に検査を行なうことが可能となっている。
【００２２】
図４は、本発明で実現される半導体回路装置の組立方法の一例を示している。ここで、４０１はパッケージの端子であり、４０２はパッケージと半導体集積回路装置とを接続するリード線である。４０３は、図３の様に検査用のプローブピンが接触したところに生じるプローブ痕であり、パッドの表面が大きく傷ついている。
【００２３】
このように、検査とボンディングを同じところで実行した場合には、４０３のようなプローブ痕がある上にリード線等を接続するような形になるので、接続がうまくいかなくなる。今回の発明では、ボンディングは、ボンディング用電極領域の中心１０３を用いて実行されるので、接続不良が起こるようなことにはならない。また、ボンディング装置の精度や、リード線幅のような物理的条件から規定される、ボンディング用電極領域の幅１０５を電極１０２が確保しているので、接続不良や、隣接する電極用パッドとのショート等が起こることもなく確実な組立を実現できている。今回の図面では、ワイヤーボンディングタイプの説明をしているが、この考え方は、チップサイズパッケージやエリアパッドのような接続方法に対しても十分有効なものとなる。
【００２４】
【発明の効果】
以上説明した様に、本発明では、微細化が進む半導体集積回路装置において、電極パッドを検査用の領域と、ボンディング用の領域に分けて考え、これらの領域の幅と間隔の最小値を、検査装置、ボンディング装置の精度や、プローブ用ピンの加工精度、等の情報に基づいて決定しておき、この最小値を確保するようにこの電極パッドの設計を実現することで、半導体集積回路装置の検査と組立を確実に行なえるとともに、面積の最適化も実現できる。
【図面の簡単な説明】
【図１】本発明の第１の実施の形態における電極用パッドの配置例を示す図
【図２】本発明の第１の実施の形態における電極用パッドの配置例を示す図
【図３】本発明の第２の実施の形態における半導体集積回路装置の検査方法の一例を示す図
【図４】本発明の第２の実施の形態における半導体集積回路装置の組立方法の一例を示す図
【符号の説明】
１０１ パッドセル
１０２ 電極パッド
１０３ ボンディング用電極領域の中心位置
１０４ 検査用電極領域の中心位置
１０５ ボンディング用電極領域の最小幅
１０６ 検査用電極領域の最小幅
１０７ ボンディング用電極領域の中心位置と検査用電極領域の中心位置の最小間隔
１０８ パッドセル幅
１０９ 検査用電極領域
１１０ ボンディング用電極領域[0001]
BACKGROUND OF THE INVENTION
The present invention relates to realization of high density and high integration of a semiconductor integrated circuit device, and in particular, to surely realize electrical property inspection and bonding to a package of a highly integrated semiconductor integrated circuit device, and a semiconductor integrated circuit The present invention provides a pad arrangement for minimizing the area of the device, and a method for inspecting and assembling electrical characteristics of a semiconductor integrated circuit device using the pad.
[0002]
[Prior art]
With the recent improvement in miniaturization technology of semiconductor integrated circuit devices, signal direction control for exchanging electrical signals between the inside and outside of the semiconductor integrated circuit device and a pad cell equipped with a protection circuit As a result, the pad cell pitch is also reduced.
[0003]
The miniaturization technology in the semiconductor manufacturing technology is improving at a rapid speed, but the inspection technology to evaluate the electrical characteristics by applying pins to the electrode pad and the connection between the semiconductor integrated circuit and the package through the electrode pad are realized. In the bonding technology, it has become difficult to realize the miniaturization as in the semiconductor manufacturing technology.
[0004]
Actually, in the electrical characteristic inspection, the electrode pad needs to secure an area determined by the thickness of the inspection pin and the accuracy of movement deviation in the inspection apparatus, and the lead wire is also used for bonding to the package. The electrode pad must secure a region defined by the width of the electrode.
[0005]
As one method for avoiding these problems, in Japanese Patent Laid-Open No. 5-206383, a pad for electrical property inspection is provided separately from the electrode pad, and this is dicing outside the region of the semiconductor integrated circuit on the semiconductor wafer. By arranging on the line, an area necessary for executing the inspection of the electrical property inspection pad is secured, and the inspection and measurement of the IC are facilitated.
[0006]
[Problems to be solved by the invention]
However, in Japanese Patent Application Laid-Open No. 5-206383, it is possible to surely perform the inspection of electrical characteristics. However, as described in the prior art, the electrode pad has a certain width for bonding. This problem cannot be solved.
[0007]
At present, with the improvement of semiconductor wafer processing technology, dicing lines have also been miniaturized, and the width of the electrical property inspection pad may be larger than the width of the dicing line. Even if the technique disclosed in the publication is used, it is difficult to achieve both easy inspection of the IC and optimization of the area of the semiconductor integrated circuit.
[0008]
In addition, when an electrical property inspection is performed using an electrode pad having a minimum size necessary for inspection and bonding, bonding is performed when an attempt is made to perform bonding using the same electrode pad. May fail. This is largely due to the probe pin of the inspection tool applied during the characteristic inspection leaving a probe mark on the electrode pad.
[0009]
This is because as the electrode pad is further miniaturized, the ratio of the probe trace to the size of the electrode pad increases, and this probe trace hinders pressure bonding and alloy formation during bonding.
[0010]
[Means for Solving the Problems]
In order to solve the above problems and realize reliable electrical property inspection and bonding, the electrode pad area is increased to reduce the area ratio of the probe trace after the inspection, and bonding is possible. It is conceivable to divide the pad into a performance inspection part and a bonding part so that probe marks do not remain in the bonding pad part.
[0011]
In this patent, in order to achieve reliable inspection and bonding, and further optimize the area, the electrode pad is changed in the place to be probed and the place to be bonded, and the area of the semiconductor integrated circuit device is optimized. In order to achieve this, electrode pad arrangement is determined based on information such as inspection rules, bonding rules, and pad pitch.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0013]
(First embodiment)
In the first embodiment, the invention according to claim 1 will be described with reference to the drawings.
[0014]
FIG. 1 is an example of an electrode pad and an arrangement of the electrode pad designed according to the present invention. Reference numeral 101 denotes a pad cell body on which a protection circuit and control logic are mounted.
[0015]
A region 109 is an electrode region for inspection, and a region 110 is an electrode region for bonding. Here, the area 110 is defined to have a minimum size in order to ensure that bonding can be reliably performed based on the accuracy of the bonding apparatus and physical factors of the bonding wire, and the width is 105. The area 109 is defined to have a minimum size of 106 so that the inspection can be performed reliably from the accuracy of the inspection apparatus and the physical characteristics of the inspection pin.
[0016]
The electrode pad 102 is formed by arranging the region 109 and the region 110 adjacent to each other or partially overlapping each other. One feature of the present invention is that it is convex like the electrode pad 102.
[0017]
Reference numeral 103 denotes a center position of the bonding pad area 110, and reference numeral 104 denotes a center position of the performance inspection pad area 109.
[0018]
Here, the interval 107 indicates the minimum width of the distance between the center 103 of the bonding pad region 110 and the center 104 of the inspection pad region 109. This distance is used to ensure that even if the probe traces on the pin remain on the pad after the probe pin is placed during the characteristic inspection, bonding can be reliably performed if only this distance is maintained. This distance is the most important distance for the present invention. Thus, by defining the interval 107, it is ensured that inspection and bonding can be realized reliably even if the regions 109 and 110 are overlapped with their centers 103 and 104 maintained at a distance of 107 or more. Therefore, the effect of reducing electrode pads can be expected.
[0019]
FIG. 2 is an example of an electrode pad designed according to the present invention and an arrangement of the electrode pad. FIG. 2 shows a state where the width 105 of the bonding electrode region and the width 106 of the inspection electrode region have the same value in FIG. In such a state, there is no distinction between the center 203 of the bonding electrode region and the center 204 of the inspection electrode region, so that it is possible to select which one to use when performing bonding and inspection, and efficient inspection. Bonding becomes possible.
[0020]
(Second Embodiment)
In the second embodiment, the invention according to claim 2 will be described with reference to the drawings.
[0021]
FIG. 3 shows an example of a test method realized by the present invention.
Here, reference numeral 301 denotes a verification probe pin, which is brought into contact with the center 104 of the test electrode region to execute an electrical characteristic inspection. At this time, the contact position of the pin 301 with respect to the electrode pad 102 is the center position 104 due to factors such as the accuracy of the pin interval of the inspection probe pin, the accuracy of the probe pin movement of the inspection device, and the angle of entry of the inspection probe pin with respect to the electrode pad. However, since the inspection electrode region 109 has the width 106, the inspection can be surely performed.
[0022]
FIG. 4 shows an example of an assembling method of a semiconductor circuit device realized by the present invention. Here, 401 is a terminal of the package, and 402 is a lead wire for connecting the package and the semiconductor integrated circuit device. Reference numeral 403 denotes probe marks generated when the probe pins for inspection contact as shown in FIG. 3, and the surface of the pad is greatly damaged.
[0023]
As described above, when the inspection and bonding are performed at the same place, the probe trace such as 403 is formed and the lead wire or the like is connected, so that the connection is not successful. In the present invention, bonding is performed using the center 103 of the electrode region for bonding, so that connection failure does not occur. In addition, since the electrode 102 has a bonding electrode region width 105 defined by the accuracy of the bonding apparatus and physical conditions such as the lead wire width, the connection between the bonding electrode and the adjacent electrode pad can be prevented. Secure assembly is possible without short circuit. In this drawing, the wire bonding type is described, but this concept is sufficiently effective for connection methods such as chip size packages and area pads.
[0024]
【The invention's effect】
As described above, according to the present invention, in the semiconductor integrated circuit device that is being miniaturized, the electrode pad is considered to be divided into a region for inspection and a region for bonding, and the minimum value of the width and interval of these regions is determined. A semiconductor integrated circuit device that is determined on the basis of information such as the accuracy of the inspection device and the bonding device and the processing accuracy of the probe pin, and realizes the design of this electrode pad so as to ensure this minimum value. Can be reliably inspected and assembled, and the area can be optimized.
[Brief description of the drawings]
FIG. 1 is a diagram showing an arrangement example of electrode pads in the first embodiment of the present invention. FIG. 2 is a diagram showing an arrangement example of electrode pads in the first embodiment of the present invention. The figure which shows an example of the inspection method of the semiconductor integrated circuit device in the 2nd Embodiment of this invention FIG. 4 The figure which shows an example of the assembly method of the semiconductor integrated circuit device in the 2nd Embodiment of this invention Explanation of]
101 Pad Cell 102 Electrode Pad 103 Bonding Electrode Area Center Position 104 Inspection Electrode Area Center Position 105 Bonding Electrode Area Minimum Width 106 Inspection Electrode Area Minimum Width 107 Bonding Electrode Area Center Position and Inspection Electrode Area Minimum interval 108 at the center position of the pad pad width 109 Inspection electrode region 110 Bonding electrode region

Claims (7)

各外部端子に対して、ボンディング用の第１の矩形状の電極領域と、
テスト用の第２の矩形状の電極領域とを接して配置することにより形成される電極パッドを複数備える半導体集積回路装置であって、
前記複数の電極パッドは、当該半導体集積回路装置の外側方向へ前記第１の矩形状の電極領域、前記第２の矩形状の電極領域の順番に並んで形成されている第１の電極パッドと、当該半導体集積回路装置の外側方向へ前記第２の矩形状の電極領域、前記第１の矩形状の電極領域の順番に並んで形成されている第２の電極パッドから構成され、前記第１の電極パッドと前記第２の電極パッドとが交互に配置されていることを特徴とする半導体集積回路装置。For each external terminal, a first rectangular electrode region for bonding;
A semiconductor integrated circuit device comprising a plurality of electrode pads formed by placing in contact with a second rectangular electrode region for testing,
The plurality of electrode pads include a first electrode pad formed in the order of the first rectangular electrode region and the second rectangular electrode region in the outer direction of the semiconductor integrated circuit device. The second rectangular electrode region and the second rectangular electrode region formed in this order in the order of the first rectangular electrode region toward the outside of the semiconductor integrated circuit device. The electrode pads and the second electrode pads are alternately arranged. 前記第１の矩形状の電極領域の面積は、前記第２の矩形状の電極領域の面積よりも大きいことを特徴とする請求項１記載の半導体集積回路装置。2. The semiconductor integrated circuit device according to claim 1, wherein an area of the first rectangular electrode region is larger than an area of the second rectangular electrode region. 前記第１の電極パッドと当該半導体集積回路装置の最も近い辺との距離は、前記第２の電極パッドと当該半導体集積回路装置の最も近い辺との距離よりも短いことを特徴とする請求項２記載の半導体集積回路装置。  The distance between the first electrode pad and the nearest side of the semiconductor integrated circuit device is shorter than the distance between the second electrode pad and the nearest side of the semiconductor integrated circuit device. 3. The semiconductor integrated circuit device according to 2. 前記第１の電極パッドの前記第２の矩形状の電極領域と、前記第２の電極パッドの前記第２の電極パッドとが、当該半導体集積回路装置に対して並行に隣り合って配置されていることを特徴とする請求項３記載の半導体集積回路装置。The second rectangular electrode region of the first electrode pad and the second electrode pad of the second electrode pad are arranged adjacent to each other in parallel to the semiconductor integrated circuit device. 4. The semiconductor integrated circuit device according to claim 3, wherein: 前記第１の矩形状の電極領域と前記第２の矩形状の電極領域とは、一部重なり合って配置されていることを特徴とする請求項４記載の半導体集積回路装置。5. The semiconductor integrated circuit device according to claim 4, wherein the first rectangular electrode region and the second rectangular electrode region are partially overlapped with each other. 前記第２の矩形状の電極領域にてテストを行うために当てるプローブピンが残すプローブ痕が、前記第１の矩形状の電極領域にておこなうボンディングに影響を及ぼさない程度に、前記第１の矩形状の電極領域の中心部と前記第２の矩形状の電極領域の中心部の距離が確保されていることを特徴とする請求項５記載の半導体集積回路装置。To the extent that the probe marks left by the probe pins applied to perform the test in the second rectangular electrode region do not affect the bonding performed in the first rectangular electrode region. the semiconductor integrated circuit device according to claim 5, wherein the distance between the center portion and the center portion of the rectangular electrode region said second rectangular electrode region is ensured. 請求項１乃至６記載の半導体集積回路装置に対して、
前記第２の電極パッドに対してテストプローブピンを接触させて当該半導体集積回路装置の電気特性検査を行ない、
前記第１の電極パッドに対して外部信号線のボンディングを行うことを特徴とする半導体集積回路装置の検査組立方法。The semiconductor integrated circuit device according to claim 1,
Test electrical characteristics of the semiconductor integrated circuit device by bringing a test probe pin into contact with the second electrode pad,
A method for inspecting and assembling a semiconductor integrated circuit device, wherein an external signal line is bonded to the first electrode pad.
JP33718498A 1998-11-27 1998-11-27 Semiconductor integrated circuit device and method for assembling semiconductor integrated circuit device Expired - Fee Related JP3843624B2 (en)

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