JP4744259B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention includes a semiconductor element having a structure referred to as a pad-on-element (POE) in which electrode pads are formed on input / output (I / O) cells, and bumps are formed on the electrode pads. The present invention relates to a semiconductor device electrically connected to the wiring electrode portion and a manufacturing method thereof.

  FIG. 11 is a cross-sectional view of a conventional semiconductor device 51 in which a semiconductor element 52 is mounted on a semiconductor substrate 57. As shown in FIG. 12, a plurality of electrode pads 54 made of a material such as Al are formed on a plurality of input / output cells on the outer periphery of the circuit formation region 53 on the semiconductor element 52. Each electrode pad 54 is formed with a metal bump 55 made of a material such as Au (no leveling is required).

  A power supply 56 for supplying power for driving the circuit core portion is provided in the range of the circuit formation region 53 on the semiconductor element 52. One of the plurality of electrode pads 54 is electrically connected to each power source 56.

  In addition, a plurality of wiring electrode portions 58 are provided on the upper layer surface of the semiconductor substrate 57, and the wiring electrode portion 58 is interposed between the semiconductor element 52 and the semiconductor substrate 57 by flip-chip mounting. 58 and the bump 55 are electrically connected. The plurality of wiring electrode portions 58 on the upper layer surface of the semiconductor substrate 57 and the plurality of back surface land portions 60 on the back surface side are connected by an inner layer via 61.

FIG. 13 is a cross-sectional view of another conventional semiconductor device 51. A conductive adhesive 64 is transferred and applied to each bump 55 of the semiconductor element 52, and each bump 55 is connected to the bump 55 via the conductive adhesive 64. Each wiring electrode part 58 is electrically connected. A liquid epoxy resin material 59 is injected into the gap between the semiconductor element 52 and the semiconductor substrate 57 and cured.
Japanese Patent Laid-Open No. 11-340267

  However, in the conventional semiconductor device 51, with the progress of the technology for improving the function of the semiconductor element 52, it is technically essential to increase the number of pins of the semiconductor element 52. In order to increase the number of pins, it is necessary to increase the number of terminals of the electrode pad 54 on the outer peripheral portion of the upper surface of the semiconductor element 52. However, the outer side dimension L (size) of the semiconductor element 52 is correspondingly increased. As a result, the problem of exceeding the user-defined semiconductor element dimensions (size) occurred.

  On the other hand, when the distance (pitch) between the electrode pads 54 of the semiconductor element 52 is reduced, there is a problem that defects such as an electrical contact failure and a leak failure occur between the adjacent electrode pads 54. It was.

  Further, when the outer side dimension L of the semiconductor element 52 is increased in order to cope with the increase in the number of pins as described above, the power supply of the circuit core portion existing inside the circuit formation region 53 of the semiconductor element 52 is increased. The wiring length between the electrode pad 54 and the electrode pad 54 electrically connected to the power source 56 becomes long. For this reason, an IR drop phenomenon occurs in which the output voltage of the power supply 56 drops, and there arises a problem that prescribed semiconductor element characteristics cannot be obtained. The IR drop is a phenomenon in which a voltage drop called IR occurs when a current I is passed through a wiring having a wiring resistance R.

  The present invention makes it possible to cope with the increase in the number of pins of a semiconductor element without reducing the distance (pitch) between electrode pads on the outer peripheral portion of the upper surface of the semiconductor element and increasing the outer dimension (size) of the semiconductor element. It is another object of the present invention to provide a semiconductor device and a method for manufacturing the same that can significantly reduce the IR drop phenomenon in which the output voltage of the power supply of the circuit core section drops.

In order to achieve the above object, according to the semiconductor device of the present invention, an outer peripheral electrode pad is formed on each of a plurality of input / output cells in an outer peripheral portion of a circuit formation region of a semiconductor element, and In the semiconductor device in which the bump is formed, an internal electrode pad is formed on the input / output cell provided in the range of the circuit formation region of the semiconductor element, and a plurality of internal bumps are formed on the internal electrode pad, By flip chip mounting, an insulating resin material is interposed between the semiconductor element and the semiconductor substrate to electrically connect each outer peripheral portion and internal bump of the semiconductor element to each wiring electrode portion of the semiconductor substrate. The semiconductor element has a quadrangular shape, the outer peripheral portion and the internal electrode pads are formed in a rectangular shape, and the semiconductor element is divided into four triangular partitioned areas by diagonal lines. The outer peripheral portion and the inner electrode pads included, to the outer edge sides of the semiconductor elements, characterized in that the short side is arranged so as to be parallel.
Further, the semiconductor device of the present invention is a semiconductor in which outer peripheral electrode pads are respectively formed on a plurality of input / output cells in the outer peripheral portion of a circuit formation region of a semiconductor element, and outer peripheral bumps are formed on each outer peripheral electrode pad. An internal electrode pad is formed on an input / output cell provided within a circuit formation region of the semiconductor element, and a plurality of internal bumps are formed on the internal electrode pad. By interposing an insulating resin material between the semiconductor element and the semiconductor substrate, each outer peripheral part and internal bump of the semiconductor element and each wiring electrode part of the semiconductor substrate are electrically connected, and the internal electrode of the semiconductor element The pad is formed with an inspection area for contacting an inspection probe needle, and internal bumps are formed on both sides of the inspection area.

  According to this, since the internal electrode pads are formed within the range of the circuit formation region separately from the outer peripheral electrode pads, and the plurality of internal bumps are formed on the internal electrode pads, the total number of electrode pads of the semiconductor element is Therefore, the number of semiconductor elements can be increased without reducing the distance (pitch) between the outer peripheral electrode pads or increasing the outer dimension (size) of the semiconductor element. it can.

In addition, the flip-chip mounting electrically connects the internal bumps of the semiconductor element and the wiring electrode portion of the semiconductor substrate. However, during flip-chip mounting, the semiconductor substrate is likely to warp and swell, and such There is a possibility that the internal bumps are detached from the wiring electrode portion due to warpage or undulation. In the case where there is one internal bump formed on the internal electrode pad, if the internal bump is detached from the wiring electrode portion, the electrical connection between the internal bump and the wiring electrode portion is interrupted. In contrast, in the present invention, there are a plurality of internal bumps formed on the internal electrode pad, and the plurality of internal bumps are connected to one wiring electrode portion. Even if warping or undulation occurs in the semiconductor substrate, it is very unlikely that all of the plurality of internal bumps will be detached from the wiring electrode part at one time. Even so, the connection between the remaining internal bumps and the wiring electrode portion is ensured. Thereby, the connection is maintained and the reliability of the connection is improved.

Furthermore, the heat generated from the circuit formation region of the semiconductor element is transferred to the internal bumps from the internal electrode pads and efficiently dissipated to the user substrate and the housing via the semiconductor substrate. Thereby, the power consumption of a semiconductor element or a semiconductor device can be reduced.
In the probe test, the probe needle is brought into contact with the outer peripheral electrode pad and the internal electrode pad, respectively, to test the electrical characteristics of the semiconductor element. At this time, in general, the probe needle moves on the outer electrode pad and the inner electrode pad while sliding from the outer side to the inner side of the semiconductor element and slides on each electrode pad. The direction of the long side of the electrode pad is the same. Thereby, since the contact distance of a probe needle and each electrode pad can be ensured long, the reliability of a probe test improves.

Also, may be electrically connected to the wiring electrodes of each outer peripheral portion and inner bumps and the semiconductor substrate of the semiconductor element via a conductive adhesive.
In addition, an inspection region in which an inspection probe needle is brought into contact with the internal electrode pad of the semiconductor element may be formed .

It is preferable that internal bumps are formed on both sides of the inspection area .
The number of the internal electrode pads corresponds to the number of power source provided in the circuit of at least a semiconductor element, it is preferable that the internal electrode pads respectively at the each power supply is electrically connected.

  According to this, by connecting the internal electrode pad to the power source electrically, the wiring length between the power source and the internal electrode pad can be reduced as compared with the conventional case where the outer peripheral electrode pad is electrically connected to the power source. Can be shortened. For this reason, the IR drop phenomenon in which the output voltage of the power source drops can be greatly reduced.

Furthermore, the semiconductor device manufacturing method of the present invention is the above-described semiconductor device manufacturing method, in which an electrical inspection is performed by bringing a probe needle into contact with the outer peripheral portion and the internal electrode pad of the semiconductor element formed on the wafer. Performing a process, cutting the wafer into a plurality of semiconductor elements, forming an outer peripheral bump on the outer peripheral electrode pad of the semiconductor element and forming an inner bump on the inner electrode pad, and an upper surface of the semiconductor substrate A step of affixing a sheet-shaped resin material to the semiconductor substrate, aligning the semiconductor element on the semiconductor substrate, flip-chip mounting with the thermocompression bonding method through the resin material, each outer peripheral portion and internal bumps, each wiring electrode portion, And a step of electrically connecting the two.

Furthermore, a method of manufacturing a semiconductor device of the present invention is a method of manufacturing the semi-conductor device, electrical inspection by contacting each probe on the outer peripheral portion and the inner electrode pads of the semiconductor devices formed on the wafer A step of cutting the wafer and dividing it into a plurality of semiconductor elements, a step of forming outer peripheral bumps on the outer peripheral electrode pads of the semiconductor elements and forming inner bumps on the internal electrode pads, The semiconductor element is aligned, flip-chip mounted, and electrically connected to each outer peripheral portion and internal bump and each wiring electrode portion via a conductive adhesive, and in the gap between the semiconductor element and the semiconductor substrate. And a step of injecting, applying, and curing a liquid resin material .

  As described above, according to the present invention, it is possible to increase the number of semiconductor elements without reducing the distance (pitch) between the outer peripheral electrode pads or increasing the outer dimension (size) of the semiconductor element.

  Also, when flip-chip mounting, even if warping or undulation occurs in the semiconductor substrate, it is very unlikely that all of the plurality of internal bumps will be detached from the wiring electrode portion at one time. Even if the wiring electrode part is detached from the wiring electrode part, the connection between the remaining internal bumps and the wiring electrode part is ensured. Thereby, the connection is maintained and the reliability of the connection is improved.

  Furthermore, the heat generated from the circuit formation region of the semiconductor element is transferred to the internal bumps from the internal electrode pads and efficiently dissipated to the user substrate and the housing via the semiconductor substrate. Thereby, the power consumption of a semiconductor element or a semiconductor device can be reduced.

  Further, since the wiring length between the power supply of the semiconductor element and the internal electrode pad is shortened as compared with the conventional one, the IR drop phenomenon in which the output voltage of the power supply drops can be greatly reduced.

  Furthermore, since the direction of movement of the probe needle and the direction of the outer periphery and the long side of the internal electrode pad are the same, a long contact distance between the probe needle and each electrode pad can be ensured, and the probe test is reliable. improves.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
As shown in FIG. 1, reference numeral 1 denotes a semiconductor device in which a semiconductor element 3 is mounted on a semiconductor substrate 2. FIG. 2 is a plan view of a rectangular semiconductor element 3 with the circuit forming surface as the upper surface. A rectangular outer peripheral electrode pad 5 is formed on each of a plurality of input / output (I / O) cells in the outer peripheral portion of the circuit forming region 4 of the semiconductor element 3. Each outer peripheral electrode pad 5 is provided with an inspection region 9 where a probe needle 7 for inspection is brought into contact to make a probe mark 8 and a bump forming region 11 where an outer peripheral bump 10 made of a material such as Au is formed. ing.

  A rectangular internal electrode pad 14 is formed on each input / output (I / O) cell provided in the circuit forming region 4. Each internal electrode pad 14 is provided with an inspection region 15 where the probe needle 7 for inspection is brought into contact with the probe mark 8 and a bump formation region 17 where an internal bump 16 made of a material such as Au is formed. . Note that the bump formation regions 17 are on both sides of the inspection region 15, whereby two internal bumps 16 are formed on each internal electrode pad 14.

  In addition, a plurality of power sources 18 that supply power for driving the circuit core unit are provided in the circuit within the circuit forming region 4. The number of internal electrode pads 14 is the same as the number of power supplies 18, and the internal electrode pads 14 are located immediately above the power supplies 18, and the internal electrode pads 14 are electrically connected to each power supply 18. .

  As shown in FIG. 3, when the semiconductor element 3 is divided into four triangular partitioned areas 19a to 19d by a diagonal line A, the outer peripheral portion and the internal electrode pads 5 and 14 included in the partitioned areas 19a to 19d are It arrange | positions so that the short side may become parallel with respect to the outer edge sides 20a-20d of the semiconductor element 3 contained in the same division area 19a-19d.

  As shown in FIG. 1, the semiconductor substrate 2 is a multilayer circuit board, and a plurality of wiring electrode portions 23 are formed on the upper layer surface of the semiconductor substrate 2. These wiring electrode portions 23 and a plurality of back surface land portions 24 formed on the back surface side of the semiconductor substrate 2 are connected by an inner layer via 25.

  An insulating sheet-shaped epoxy resin material 26 is interposed between the semiconductor element 3 and the semiconductor substrate 2, and each outer peripheral portion of the semiconductor element 3 and the internal bumps 10 and 16 are connected to each of the semiconductor substrate 2. The wiring electrode part 23 is electrically connected.

Next, a method for manufacturing the semiconductor device 1 will be described.
(1) Inspection Step First, as shown in FIGS. 4A and 4B, the outer peripheral portions of the plurality of semiconductor elements 3 formed on the wafer 28 and the inspection regions 9 and 15 of the internal electrode pads 5 and 14 are respectively provided. The probe needle 7 is brought into contact with each other, and a probe mark 8 is formed in each of the inspection regions 9 and 15 to perform an electrical inspection.
(2) Cutting Step Next, the wafer 28 is cut and divided into a plurality of semiconductor elements 3.
(3) Bump Formation Step Next, as shown in FIG. 4C, the outer bump 10 is formed on the outer electrode pad 5 of the semiconductor element 3 and the inner bump 16 is formed on the inner electrode pad 14.
(4) Resin Material Affixing Step Next, as shown in FIG. 4D, a sheet-shaped epoxy resin material 26 is affixed to the upper surface of the semiconductor substrate 2.
(5) Mounting Step Thereafter, as shown in FIG. 4E, the semiconductor element 3 is inverted, the semiconductor element 3 is aligned on the semiconductor substrate 2, and a high temperature and high load is applied through the epoxy resin material 26. Flip chip mounting is performed by a thermocompression bonding method (for example, about 230 ° C./10 seconds: 50 to 60 gf / B), and each outer peripheral portion and internal bumps 10 and 16 are electrically connected to each wiring electrode portion 23.

The semiconductor device 1 is manufactured by the steps (1) to (5).
Hereinafter, the operation of the above configuration will be described.
As shown in FIG. 2A, the internal electrode pads 14 are formed within the circuit forming region 4 separately from the outer peripheral electrode pads 5, and the internal bumps 16 are formed on each internal electrode pad 14. The number of all the electrode pads of the semiconductor element 3 increases by the number of the internal electrode pads 14, and accordingly, the distance (pitch) between the outer peripheral electrode pads 14 is reduced or the outer side dimension L (size) of the semiconductor element 3 is reduced. The semiconductor element 3 can be multi-pinned without enlarging the thickness of the semiconductor element 3, and the cost of the semiconductor element 3 can be reduced.

  Further, as shown in FIG. 1B, the internal bump 16 of the semiconductor element 3 and the wiring electrode portion 23 of the semiconductor substrate 2 are electrically connected by flip chip mounting. The semiconductor substrate 2 is likely to be warped or undulated, and the internal bump 16 may be detached from the wiring electrode portion 23 due to such warpage or undulation. In the case where the number of internal bumps 16 formed on the internal electrode pad 14 is one, if the internal bump 16 is detached from the wiring electrode portion 23, the electrical connection between the internal bump 16 and the wiring electrode portion 23 is interrupted. Therefore, there is a problem that the connection reliability is low. On the other hand, in the first embodiment, there are two internal bumps 16 formed on the internal electrode pad 14, and these two internal bumps 16 are represented by 1 Since the semiconductor substrate 2 is connected to the wiring electrode portions 23, even if the semiconductor substrate 2 is warped or undulated, the possibility that both of the two internal bumps 16 are detached from the wiring electrode portion 23 at a time is very low. In most cases, even if any one of the internal bumps 16 is detached from the wiring electrode portion 23, the connection between the remaining other internal bump 16 and the wiring electrode portion 23 is ensured. Therefore, the connection is maintained and the reliability of the connection is improved.

  Furthermore, heat generated from the circuit formation region 4 of the semiconductor element 3 is transmitted from the internal electrode pad 14 to the internal bump 16 and is efficiently dissipated to the user substrate and the housing via the semiconductor substrate 2. Thereby, the power consumption of the semiconductor element 3 and the semiconductor device 1 can be reduced. As an example, the thermal resistance data value indicating the temperature rise per watt can be reduced by about 35% compared to the conventional case.

  Further, as shown in FIG. 2A, since the internal electrode pad 14 is electrically connected to the power source 18, the outer peripheral electrode pad 54 is electrically connected to the power source 56 as in the prior art (see FIG. 12). Compared with the case of connection, the wiring length between the power supply 18 and the internal electrode pad 14 is shortened. As a result, the IR drop phenomenon in which the output voltage of the power supply 18 drops can be greatly reduced, the semiconductor element 3 can be further increased in speed, and the device performance can be improved with respect to a fine process.

  Further, in the (1) inspection process when the semiconductor device 1 is manufactured, the probe needle 7 moves in the predetermined direction B from the outer side to the inner side of the semiconductor element 3 as shown in FIG. It slides in contact with the inspection area 9 of the partial electrode pad 5 and the inspection area 15 of the internal electrode pad 14. As a result, the moving direction of the probe needle 7 (that is, the predetermined direction B) is the same as the direction of the long sides of the outer peripheral portions and the internal electrode pads 5, 14. A long contact distance with each electrode pad 5 and 14 can be secured, and the reliability of the probe test is improved.

Further, since the number of layers constituting the semiconductor element 3 can be reduced, it is possible to reduce the mask cost and the manufacturing process when the semiconductor element 3 is manufactured, and the semiconductor element 3 and the cost reduction related to the manufacturing process can be realized. The productivity of 3 can be improved.
(Embodiment 2)
As shown in FIG. 5, each outer peripheral portion and internal bumps 10 and 16 of the semiconductor element 3 and each wiring electrode portion 23 of the semiconductor substrate 2 are electrically connected through a conductive adhesive 35.

Next, a method for manufacturing the semiconductor device 1 will be described.
Similar to the first embodiment described above, the (1) inspection step, (2) cutting step, and (3) bump formation step shown in FIG. 6 (c) are performed. .
(4) Mounting Step Next, as shown in FIG. 6D, a conductive adhesive 35 is applied to each outer peripheral portion of the semiconductor element 3 and the internal bumps 10 and 16, the semiconductor element 3 is inverted, and the semiconductor substrate The semiconductor element 3 is aligned on 2 and flip-chip mounted by a thermocompression bonding method that applies high temperature and high load, and each outer peripheral portion and internal bumps 10 and 16 and each wiring electrode portion 23 are connected via a conductive adhesive 35. Are electrically connected.
(5) Resin injection step Thereafter, as shown in FIG. 6 (e), an insulating liquid epoxy resin material 26 is injected and applied to the gap between the semiconductor element 3 and the semiconductor substrate 2, and the temperature is about 120 ° C. The epoxy resin material 26 is cured at a high temperature.

The semiconductor device 1 is manufactured by the steps (1) to (5).
In each of the embodiments described above, as shown in FIGS. 1B and 5B, two internal bumps 16 are formed on one internal electrode pad 14, but three or more For example, as shown in FIGS. 7A and 7B, four or eight internal bumps 16 may be formed.

  In each of the above embodiments, the internal electrode pad 14 is formed in a rectangular shape, but is not limited to a rectangular shape. For example, as shown in FIGS. 8A to 8D, it may be formed in a square shape. Good. Furthermore, it may be formed into a shape other than a quadrangle, for example, an I shape as shown in FIGS. 9A to 9C, or a saddle shape as shown in FIG.

In each of the above-described embodiments, as shown in FIG. 2B, when the outer peripheral bump 10 is formed on the outer electrode pad 5, the outer peripheral bump 10 is formed next to the probe mark 8. As shown in FIG. 10, the outer peripheral bump 10 may be formed so as to overlap the position of the probe mark 8.
In each of the above embodiments, as shown in FIG. 2A, the internal electrode pad 14 is disposed directly above the power source 18, but may be disposed in the vicinity of the power source 18. Although the number of internal electrode pads 14 is the same as the number of power supplies 18, the number of internal electrode pads 14 may be larger than the number of power supplies 18. In this case, another internal electrode pad 14 is connected to a specific internal electrode pad 14 connected to the power supply 18 via an internal wiring. According to this, even if warpage or undulation occurs in the semiconductor substrate 2, there is a possibility that the internal bump 16 of a specific internal electrode pad 14 and the internal bump 16 of another internal electrode pad 14 may be detached from the wiring electrode portion 23 at a time. In most cases, even if the internal bumps 16 of the specific or different internal electrode pads 14 are separated from the wiring electrode part 23, the internal bumps 16 and the wiring electrode parts of the remaining internal electrode pads 14 23 is secured. Thereby, the connection is maintained and the reliability of the connection is improved. It is also possible to select and use the specific internal electrode pad 14 and another internal electrode pad 14 for one power source 18.

  INDUSTRIAL APPLICABILITY The present invention is useful for a semiconductor device of a type in which a plurality of metal bumps are formed on an electrode pad of a semiconductor element, and these bumps are connected to a plurality of wiring electrode portions formed on a semiconductor substrate by flip chip mounting. .

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure of the semiconductor device in Embodiment 1 of this invention, (a) is a longitudinal cross-sectional view, (b) is an enlarged view of the location of the internal electrode pad in (a). 2A and 2B are diagrams of a semiconductor element of the semiconductor device, in which FIG. 1A is a plan view and FIG. 2B is a partially enlarged view of FIG. FIG. 4 is a diagram of a semiconductor element of the semiconductor device, in which (a) shows four partitioned regions of the semiconductor element, and (b) shows one of the four partitioned regions. It is a figure which shows the manufacturing method of a semiconductor device equally. It is a figure of the semiconductor device in Embodiment 2 of this invention, (a) is a longitudinal cross-sectional view, (b) is an enlarged view of the location of the internal electrode pad in (a). It is a figure which shows the manufacturing method of a semiconductor device equally. It is a figure of the internal electrode pad of the semiconductor device in other embodiments of the present invention. It is a figure of the internal electrode pad of the semiconductor device in other embodiments of the present invention. It is a figure of the internal electrode pad of the semiconductor device in other embodiments of the present invention. It is a figure of the outer peripheral part electrode pad of the semiconductor device in other embodiment of this invention. It is sectional drawing of the conventional semiconductor device. 2 is a plan view of a semiconductor element of the semiconductor device. FIG. It is sectional drawing of another conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor substrate 3 Semiconductor element 4 Circuit formation area 5 Outer peripheral electrode pad 7 Probe needle 10 Outer peripheral bump 14 Internal electrode pad 15 Inspection area 16 Internal bump 18 Power supply 19a-19d Partition area 20a-20d Outer edge 23 Wiring electrode Part 26 Epoxy resin material 28 Wafer 35 Conductive adhesive A Diagonal wire

Claims (9)

A semiconductor device in which an outer peripheral electrode pad is formed on each of a plurality of input / output cells in an outer peripheral portion of a circuit formation region of a semiconductor element, and an outer peripheral bump is formed on each outer peripheral electrode pad,
An internal electrode pad is formed on the input / output cell provided within the circuit formation region of the semiconductor element,
A plurality of internal bumps are formed on the internal electrode pad,
By flip chip mounting, an insulating resin material is interposed between the semiconductor element and the semiconductor substrate to electrically connect each outer peripheral portion and internal bump of the semiconductor element to each wiring electrode portion of the semiconductor substrate. ,
The semiconductor element has a rectangular shape,
The outer peripheral part and the internal electrode pad are formed in a rectangular shape,
The semiconductor element is divided into four triangular partition areas by diagonal lines,
The outer peripheral portion and the internal electrode pad included in each of the partition regions are arranged so that the short side is parallel to the outer edge of the semiconductor element . A semiconductor device in which an outer peripheral electrode pad is formed on each of a plurality of input / output cells in an outer peripheral portion of a circuit formation region of a semiconductor element, and an outer peripheral bump is formed on each outer peripheral electrode pad,
An internal electrode pad is formed on the input / output cell provided within the circuit formation region of the semiconductor element,
A plurality of internal bumps are formed on the internal electrode pad,
By flip chip mounting, an insulating resin material is interposed between the semiconductor element and the semiconductor substrate to electrically connect each outer peripheral portion and internal bump of the semiconductor element to each wiring electrode portion of the semiconductor substrate. ,
An inspection area is formed on the internal electrode pad of the semiconductor element to contact the probe needle for inspection,
A semiconductor device, wherein internal bumps are formed on both sides of an inspection region . 2. The semiconductor device according to claim 1, wherein each outer peripheral part and internal bump of the semiconductor element and each wiring electrode part of the semiconductor substrate are electrically connected via a conductive adhesive . 3. The semiconductor device according to claim 2 , wherein each outer peripheral portion and internal bump of the semiconductor element and each wiring electrode portion of the semiconductor substrate are electrically connected via a conductive adhesive . 4. The semiconductor device according to claim 1 , wherein an inspection region for contacting an inspection probe needle is formed on an internal electrode pad of the semiconductor element . 6. The semiconductor device according to claim 5, wherein internal bumps are formed on both sides of the inspection area . The number of internal electrode pads corresponds to at least the number of power supplies provided in the circuit of the semiconductor element,
The semiconductor device according to claim 1, wherein an internal electrode pad is electrically connected to each power source . A method of manufacturing a semiconductor device according to claim 1 or 2,
A step of performing electrical inspection by bringing a probe needle into contact with the outer peripheral portion of the semiconductor element formed on the wafer and the internal electrode pad, respectively;
Cutting the wafer and dividing it into a plurality of semiconductor elements;
Forming an outer bump on the outer electrode pad of the semiconductor element and forming an inner bump on the inner electrode pad;
Attaching a sheet-shaped resin material to the upper surface of the semiconductor substrate;
A step of aligning a semiconductor element on a semiconductor substrate, flip-chip mounting through the above-mentioned resin material by a thermocompression bonding method, and electrically connecting each outer peripheral part and inner bump to each wiring electrode part A method of manufacturing a semiconductor device. A method for manufacturing a semiconductor device according to claim 3 or 4, wherein:
A step of performing electrical inspection by bringing a probe needle into contact with the outer peripheral portion of the semiconductor element formed on the wafer and the internal electrode pad, respectively;
Cutting the wafer and dividing it into a plurality of semiconductor elements;
Forming an outer bump on the outer electrode pad of the semiconductor element and forming an inner bump on the inner electrode pad;
A step of aligning a semiconductor element on a semiconductor substrate, flip-chip mounting, and electrically connecting each outer peripheral portion and internal bump and each wiring electrode portion via a conductive adhesive;
A method of manufacturing a semiconductor device comprising: a step of injecting and applying a liquid resin material into a gap between a semiconductor element and a semiconductor substrate and curing.

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