JP2009130074A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2009130074A
JP2009130074A JP2007302498A JP2007302498A JP2009130074A JP 2009130074 A JP2009130074 A JP 2009130074A JP 2007302498 A JP2007302498 A JP 2007302498A JP 2007302498 A JP2007302498 A JP 2007302498A JP 2009130074 A JP2009130074 A JP 2009130074A
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bump
bumps
semiconductor device
electrode
semiconductor chip
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Hidekazu Hosomi
英一 細美
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Toshiba Corp
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Toshiba Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a bump, which suppresses a voltage drop attributable to an electric resistance of a power supply system of a semiconductor element to a low level. <P>SOLUTION: The semiconductor device comprises: a wiring substrate 2 having a plurality of electrode pads; and a semiconductor chip 3 carried thereon wherein a bump forming face is directed downward. In a circumferential part of a surface of the semiconductor chip 3, a plurality of circular signal bumps 4 are arranged, and at its central part, a plurality of power supply bumps 5 and ground bumps 6 all having a long shape are arranged. On a face carrying the semiconductor chip of the wiring substrate 2, a circular electrode pad 7 for connecting the signal bump is formed in the circumferential part, and in its central part, an electrode pad 8 for connecting the power supply bump and an electrode pad 9 for connecting the ground bump all having a long shape are formed. Each bump of the semiconductor chip 3 is joined to the electrode pad corresponding to the wiring substrate 2. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、半導体装置に係り、特に、消費電力が高い高性能デバイスに対して有用な突起状電極を有する半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a protruding electrode useful for a high-performance device with high power consumption.

従来から、半導体チップを配線基板に搭載し接続する実装技術の一つとして、フリップチップ接続がある。フリップチップ接続は、半導体チップの主面に多数の電極をマトリックス状に配置し、この電極を介して外部との信号の送受信や電源の供給を行う接続技術であり、マイクロプロセッサ等の高性能デバイスや、多くの信号ピンを必要とするシステムＬＳＩに用いられている。   Conventionally, flip chip connection is one of mounting techniques for mounting and connecting a semiconductor chip to a wiring board. Flip chip connection is a connection technology in which a large number of electrodes are arranged in a matrix on the main surface of a semiconductor chip, and signals are sent to and received from the outside and power is supplied through these electrodes. It is also used in system LSIs that require many signal pins.

フリップチップ接続により実装される半導体チップの主面（表面）の主面には、バンプと呼ばれる突起状電極が多数配置されている。通常、主面の周辺部には、信号用のバンプ（信号バンプ）が狭い間隔（ピッチ）ｐで配設されており、中央部には、電源供給用の電源バンプと接地用のグランドバンプが、それぞれ信号バンプの配設ピッチｐよりも広いピッチで配設されている。   A large number of protruding electrodes called bumps are arranged on the main surface (surface) of the semiconductor chip mounted by flip chip connection. Normally, signal bumps (signal bumps) are arranged at a narrow interval (pitch) p on the periphery of the main surface, and a power supply bump for power supply and a ground bump for grounding are provided in the center. These are arranged at a pitch wider than the arrangement pitch p of the signal bumps.

従来から、マイクロプロセッサ等の高性能デバイスにおいては、半導体チップ内の電源供給系の電気抵抗に起因する電圧降下(＝抵抗×電流)が問題になっている。そして、半導体チップの機能素子Ａと電源バンプおよびグランドバンプとの距離を短縮し、前記した電気抵抗に起因する電圧降下をさらに小さくすることが求められている。   Conventionally, in a high-performance device such as a microprocessor, a voltage drop (= resistance × current) due to an electric resistance of a power supply system in a semiconductor chip has been a problem. Then, it is required to reduce the distance between the functional element A of the semiconductor chip, the power supply bump, and the ground bump, and further reduce the voltage drop caused by the electrical resistance.

このような要求に合わせて、半導体チップ主面の電源供給領域および／または接地領域でも、信号バンプと同じ狭い配設ピッチｐで電源バンプおよびグランドバンプを配置することが考えられている。   In order to meet such requirements, it is considered that the power supply bumps and the ground bumps are arranged at the same narrow arrangement pitch p as the signal bumps in the power supply region and / or the ground region on the main surface of the semiconductor chip.

しかしながら、このようなバンプ配置を有する半導体チップを搭載した半導体装置においては、以下に示す問題があった。すなわち、電源供給領域および／または接地領域においてバンプ間の間隔が狭くなるため、電源バンプ等の間の短絡が生じやすくなり、それに起因する不良が増大するおそれがあった。また、これらのバンプの狭ピッチ化に対応し、配線基板側の電極パッドおよび配線の設計が複雑化するため、製造歩留りの低下が生じやすかった。さらに、配線基板と半導体チップとの間に絶縁性樹脂の封止層を形成する工程で、絶縁性樹脂の注入および充填作業が難しくなるため、充填不良が発生しやすいか、あるいはスループットが低下するという問題があった。   However, the semiconductor device on which the semiconductor chip having such a bump arrangement is mounted has the following problems. That is, since the gap between the bumps becomes narrow in the power supply region and / or the ground region, a short circuit between the power bumps or the like is likely to occur, and there is a possibility that defects due to the short circuit increase. In addition, since the design of the electrode pads and the wiring on the wiring board side becomes complicated in response to the narrow pitch of these bumps, the manufacturing yield is likely to decrease. Further, in the process of forming the insulating resin sealing layer between the wiring substrate and the semiconductor chip, it becomes difficult to inject and fill the insulating resin, so that a filling failure is likely to occur or the throughput is reduced. There was a problem.

なお、この種の関連技術として、半導体装置の一例が開示されている（例えば、特許文献１参照。）。
特開２００１−２８４４０２号公報 An example of a semiconductor device is disclosed as this type of related technology (see, for example, Patent Document 1).
JP 2001-284402 A

本発明はこれらの問題を解決するためになされたもので、突起状電極（バンプ）を有する半導体装置において、半導体素子の電源供給系の電気抵抗に起因する電圧降下を低く抑えることを目的としている。   The present invention has been made to solve these problems, and an object of the present invention is to suppress a voltage drop caused by an electric resistance of a power supply system of a semiconductor element in a semiconductor device having a protruding electrode (bump). .

本発明の一態様に係る半導体装置は、一方の主面に複数の電極パッドを有する配線基板と、一方の主面に複数の突起状電極を有し、この突起状電極形成面を下向きにして前記配線基板の前記電極パッド形成面上に搭載された半導体素子を備え、前記半導体素子の前記突起状電極と前記配線基板の対応する電極パッドとを接合して成る半導体装置であり、前記半導体素子の電源供給領域および／または接地領域に形成された前記突起状電極は長尺形状を有し、かつこれら長尺形状の突起状電極はそれぞれの長辺方向を平行に揃えて配列されていることを特徴とする。   A semiconductor device according to one embodiment of the present invention includes a wiring substrate having a plurality of electrode pads on one main surface, and a plurality of protruding electrodes on one main surface, with the protruding electrode formation surface facing downward. A semiconductor device comprising a semiconductor element mounted on the electrode pad forming surface of the wiring board, wherein the protruding electrode of the semiconductor element and a corresponding electrode pad of the wiring board are joined together, The protruding electrodes formed in the power supply area and / or the ground area have a long shape, and the long protruding electrodes are arranged with their long sides aligned in parallel. It is characterized by.

本発明の一態様に係る半導体装置によれば、電源供給系の電気抵抗に起因する電圧降下を低く抑えることができる。   According to the semiconductor device of one embodiment of the present invention, a voltage drop due to the electric resistance of the power supply system can be suppressed to a low level.

以下、本発明を実施するための形態について説明する。なお、以下の記載では実施形態を図面に基づいて説明するが、それらの図面は図解のために提供されるものであり、本発明はそれらの図面に限定されるものではない。   Hereinafter, modes for carrying out the present invention will be described. In addition, although embodiment is described based on drawing in the following description, those drawings are provided for illustration and this invention is not limited to those drawings.

図１は、本発明の第１の実施形態に係る半導体装置の構成を示す断面図であり、図２は、第１の実施形態における半導体チップのバンプ（突起状電極）の配置を示す平面図である。また、図３は、図２の破線で囲まれた部分を拡大して示す図である。   FIG. 1 is a cross-sectional view showing the configuration of the semiconductor device according to the first embodiment of the present invention, and FIG. 2 is a plan view showing the arrangement of bumps (projection electrodes) of the semiconductor chip in the first embodiment. It is. FIG. 3 is an enlarged view of a portion surrounded by a broken line in FIG.

図１に示す第１の実施形態の半導体装置１は、一方の主面に複数の電極パッドを有するパッケージ用の配線基板２と、半導体チップ３を備えている。半導体チップ３は一方の主面である表面（素子形成面）に複数のバンプ（突起状電極）を有し、このバンプ形成面を下向きにして（フェースダウンで）配線基板２の電極パッド形成面上に搭載されている。   A semiconductor device 1 according to the first embodiment shown in FIG. 1 includes a wiring substrate 2 for a package having a plurality of electrode pads on one main surface, and a semiconductor chip 3. The semiconductor chip 3 has a plurality of bumps (projection electrodes) on one main surface (element formation surface), and the bump formation surface faces downward (face-down), and the electrode pad formation surface of the wiring board 2. Mounted on top.

図２に示すように、半導体チップ３の表面の周辺部には、円形状の複数の信号バンプ４が、所定の間隔（配設ピッチｐ）で配設されている。そして、このような信号バンプ４に取り囲まれた半導体チップ４の中央部には、複数の電源バンプ５とそれと同数のグランドバンプ６が、交互に並べて配設されている。電源バンプ５とグランドバンプ６は、いずれも長尺形状を有し、それぞれの長辺が半導体チップ３の少なくとも一辺に平行になるように配列されている。長尺形状の電源バンプ５とグランドバンプ６の配置間隔（配設ピッチ）は、信号バンプ４の配設ピッチｐと等しくすることが好ましい。また、電源バンプ５とグランドバンプ６、および信号バンプ４の構成材料としては、スズ（Ｓｎ）をベースにした半田材料（Ｓｎ−Ｐｂ合金、Ｓｎ−Ａｇ合金、Ｓｎ−Ｃｕ合金等）や、金（Ａｕ）、銅（Ｃｕ）等の単体金属を用いることができる。   As shown in FIG. 2, a plurality of circular signal bumps 4 are arranged at a predetermined interval (arrangement pitch p) on the periphery of the surface of the semiconductor chip 3. A plurality of power bumps 5 and the same number of ground bumps 6 are alternately arranged in the center of the semiconductor chip 4 surrounded by the signal bumps 4. Both the power supply bumps 5 and the ground bumps 6 have a long shape, and are arranged so that each long side is parallel to at least one side of the semiconductor chip 3. The arrangement interval (arrangement pitch) between the elongated power supply bumps 5 and the ground bumps 6 is preferably equal to the arrangement pitch p of the signal bumps 4. The power bumps 5, the ground bumps 6 and the signal bumps 4 may be made of a solder material (Sn—Pb alloy, Sn—Ag alloy, Sn—Cu alloy, etc.) based on tin (Sn), gold, A single metal such as (Au) or copper (Cu) can be used.

電源バンプ５およびグランドバンプ６の平面形状は、辺あるいは径がそれに直交する方向の辺あるいは径に比べて長尺に構成された形状（長尺形状）であればよい。長方形、平行四辺形、長楕円形等とすることができる。   The planar shape of the power supply bumps 5 and the ground bumps 6 may be any shape (long shape) that is configured to be longer than the sides or diameters in the direction perpendicular to the sides or diameters. It can be rectangular, parallelogram, oblong, etc.

長尺形状の電源バンプ５およびグランドバンプ６の長辺あるいは長径の長さは、半導体チップ３の電源供給領域および／または接地領域の対応する長さ全体の１／３以上であれば、電源供給系の電気抵抗に起因する電圧降下抑制の効果を上げることができる。形成の容易さ等の点からは、電源供給領域および／または接地領域の長さと等しくすることが好ましい。   If the length of the long side or the long diameter of the long power supply bump 5 and the ground bump 6 is 1/3 or more of the entire corresponding length of the power supply area and / or the ground area of the semiconductor chip 3, the power supply The effect of suppressing the voltage drop caused by the electrical resistance of the system can be increased. From the viewpoint of ease of formation, etc., it is preferable to make the length equal to the length of the power supply region and / or the ground region.

配線基板２の半導体チップ搭載面においては、周辺部に信号バンプ接続用の円形状の電極パッド７が形成されている。また、中央部には、いずれも長尺形状を有する電源バンプ接続用の電極パッド８およびグランドバンプ接続用の電極パッド９が、交互に並べて配置されている。電源バンプ接続用の電極パッド８およびグランドバンプ接続用の電極パッド９の平面形状は、長尺形状であれば特に限定されず、長方形、平行四辺形、長楕円形などとすることができる。これらの電極パッド８，９は、対応する電源バンプ５およびグランドバンプ６と同一の形状および長さとし、かつこれらのバンプに対応する位置に配置することが好ましい。   On the semiconductor chip mounting surface of the wiring substrate 2, circular electrode pads 7 for connecting signal bumps are formed in the periphery. In the center, electrode pads 8 for connecting power bumps and electrode pads 9 for connecting ground bumps, both of which are long, are alternately arranged. The planar shape of the electrode pad 8 for connecting the power bump and the electrode pad 9 for connecting the ground bump is not particularly limited as long as it is a long shape, and may be a rectangle, a parallelogram, an ellipse, or the like. These electrode pads 8 and 9 preferably have the same shape and length as the corresponding power bumps 5 and ground bumps 6 and are arranged at positions corresponding to these bumps.

そして、半導体チップ３の各バンプが配線基板２の対応する電極パッドに接合されている。すなわち、半導体チップ３の円形状の信号バンプ４が配線基板２の信号バンプ接続用の電極パッド７に接合されており、半導体チップ３のいずれも長尺形状の電源バンプ５とグランドバンプ６が、配線基板２のいずれも長尺形状の電源バンプ接続用電極パッド８とグランドバンプ接続用電極パッド９にそれぞれ接合されている。   Each bump of the semiconductor chip 3 is bonded to a corresponding electrode pad of the wiring board 2. That is, the circular signal bumps 4 of the semiconductor chip 3 are bonded to the signal bump connection electrode pads 7 of the wiring board 2, and the long power bumps 5 and the ground bumps 6 of each of the semiconductor chips 3 are Each of the wiring boards 2 is bonded to a long-shaped power bump connecting electrode pad 8 and a ground bump connecting electrode pad 9, respectively.

また、配線基板２と半導体チップ３との間には、絶縁性樹脂が注入・充填され、絶縁性樹脂から成る封止層１０が形成されている。さらに、配線基板２の半導体チップ搭載面と反対側の下面には、はんだボールのような外部接続用の電極（図示を省略する。）が配設されている。   An insulating resin is injected and filled between the wiring substrate 2 and the semiconductor chip 3 to form a sealing layer 10 made of the insulating resin. Further, an external connection electrode (not shown) such as a solder ball is disposed on the lower surface of the wiring board 2 opposite to the semiconductor chip mounting surface.

このように構成される第１の実施形態の半導体装置においては、図３に拡大して示すように、半導体チップ３の機能素子Ａと長尺形状の電源バンプ５およびグランドバンプ６との距離の最大値がｐ／２となり、従来のバンプ配置に比べて大幅に短縮することができる。また、狭ピッチのバンプ配置に比べても、機能素子Ａと電源供給用のバンプとの距離を短縮することができる。   In the semiconductor device of the first embodiment configured as described above, the distance between the functional element A of the semiconductor chip 3 and the elongated power bump 5 and ground bump 6 is enlarged as shown in FIG. The maximum value is p / 2, which can be significantly shortened compared to the conventional bump arrangement. Further, the distance between the functional element A and the bump for supplying power can be shortened as compared with the bump arrangement with a narrow pitch.

ここで、従来の半導体装置におけるバンプ配置を図４に示し、狭ピッチのバンプ配置を図５および図６に示す。図４に示すバンプ配置においては、電源バンプ５２およびグランドバンプ５３の配設ピッチは信号バンプ５４の配設ピッチｐの２倍になっており、半導体チップ５１内の機能素子Ａと電源バンプ５２およびグランドバンプ５３との距離の最大値はｐとなっている。また、図５および図６に示す狭ピッチのバンプ配置では、半導体チップ５１内の機能素子Ａと電源バンプ５２およびグランドバンプ５３との距離の最大値は、√２ｐ／２（＜ｐ）となる。   Here, the bump arrangement in the conventional semiconductor device is shown in FIG. 4, and the narrow pitch bump arrangement is shown in FIG. 5 and FIG. In the bump arrangement shown in FIG. 4, the arrangement pitch of the power bumps 52 and the ground bumps 53 is twice the arrangement pitch p of the signal bumps 54, and the functional element A in the semiconductor chip 51 and the power bumps 52, The maximum distance from the ground bump 53 is p. 5 and FIG. 6, the maximum distance between the functional element A in the semiconductor chip 51, the power supply bump 52, and the ground bump 53 is √2p / 2 (<p). .

第１の実施形態の半導体装置においては、このような従来のバンプ配置に比べて、機能素子Ａと電源供給用のバンプとの距離を短縮することができるので、電源系の電圧降下を低減し、電気的特性に優れた半導体装置を得ることができる。   In the semiconductor device of the first embodiment, the distance between the functional element A and the power supply bump can be shortened as compared with such a conventional bump arrangement, so that the voltage drop of the power supply system is reduced. A semiconductor device having excellent electrical characteristics can be obtained.

また、第１の実施形態の半導体装置においては、電源バンプ５およびグランドバンプ６間の短絡が発生しにくく、製造歩留りが向上する。さらに、半導体チップ３の電源バンプ５とグランドバンプ６がそれぞれ長尺形状を有しており、これらのバンプと半導体基板２側の電極パッド８，９との接合面積が従来に比べて増大しているため、半導体チップ３から発生する熱を、これらの長尺形状のバンプ（電源バンプ５とグランドバンプ６）および半導体基板２側の長尺形状の電極パッド８，９を介して効率的に放散させることができる。こうして、熱膨張により発生する熱応力を効果的に分散することができるので、温度サイクルに対する寿命も向上する。またさらに、絶縁性樹脂の注入および充填作業が容易であり、充填不良が発生しにくいという利点がある。   Further, in the semiconductor device of the first embodiment, a short circuit between the power supply bump 5 and the ground bump 6 hardly occurs, and the manufacturing yield is improved. Furthermore, the power supply bumps 5 and the ground bumps 6 of the semiconductor chip 3 each have a long shape, and the bonding area between these bumps and the electrode pads 8 and 9 on the semiconductor substrate 2 side is increased as compared with the prior art. Therefore, the heat generated from the semiconductor chip 3 is efficiently dissipated through these long bumps (the power bumps 5 and the ground bumps 6) and the long electrode pads 8 and 9 on the semiconductor substrate 2 side. Can be made. Thus, the thermal stress generated by the thermal expansion can be effectively dispersed, so that the life against the temperature cycle is also improved. Furthermore, there is an advantage that the injecting and filling operation of the insulating resin is easy and the filling failure hardly occurs.

次に、本発明の別の実施形態について説明する。図７は、本発明の第２の実施形態に係る半導体装置の構成を示す断面図である。   Next, another embodiment of the present invention will be described. FIG. 7 is a cross-sectional view showing a configuration of a semiconductor device according to the second embodiment of the present invention.

第２の実施形態において、半導体チップ３の素子形成面には、円形状の複数の信号バンプ４と、いずれも長尺形状の複数の電源バンプ５およびグランドバンプ６が、それぞれ第１の実施形態と同様に配設されている。   In the second embodiment, a plurality of circular signal bumps 4 and a plurality of long power bumps 5 and ground bumps 6 are formed on the element forming surface of the semiconductor chip 3, respectively. It is arrange | positioned similarly to.

配線基板２の半導体チップ搭載面において、周辺部には信号バンプ接続用の円形状の複数の電極パッド７が形成されている。また中央部にも、円形状の複数の電源バンプ接続用の電極パッド８とグランドバンプ接続用の電極パッド９がそれぞれ形成されている。これら電源バンプ接続用の電極パッド８およびグランドバンプ接続用の電極パッド９は、それぞれが列をなすように形成され、かつ電源バンプ接続用電極パッド８の列とグランドバンプ接続用電極パッド９の列が、半導体チップ３側の長尺形状の電源バンプ５およびグランドバンプ６に対応するように交互に配列されている。   A plurality of circular electrode pads 7 for connecting signal bumps are formed on the periphery of the semiconductor chip mounting surface of the wiring board 2. A plurality of circular electrode pads 8 for connecting power bumps and electrode pads 9 for connecting ground bumps are also formed at the center. The electrode pads 8 for power bump connection and the electrode pads 9 for ground bump connection are formed so as to form a row, and the row of the power bump connection electrode pads 8 and the row of the ground bump connection electrode pads 9 are formed. Are alternately arranged so as to correspond to the elongated power supply bumps 5 and ground bumps 6 on the semiconductor chip 3 side.

そして、半導体チップ３の円形状の信号バンプ４が、配線基板２の信号バンプ接続用の円形状の電極パッド７に接合されている。また、半導体チップ３の長尺形状の電源バンプ５が、配線基板２の対応する位置に形成された電源バンプ接続用の電極パッド８の列に接合され、半導体チップ３の長尺形状のグランドバンプ６が、配線基板２の対応する位置に形成されたグランドバンプ接続用の電極パッド９の列に接合されている。   Then, the circular signal bumps 4 of the semiconductor chip 3 are bonded to the circular electrode pads 7 for connecting the signal bumps of the wiring board 2. Further, the long power bumps 5 of the semiconductor chip 3 are joined to the rows of electrode pads 8 for connecting the power bumps formed at the corresponding positions on the wiring board 2, and the long ground bumps of the semiconductor chip 3 are joined. 6 are joined to a row of electrode pads 9 for ground bump connection formed at corresponding positions on the wiring board 2.

また、配線基板２と半導体チップ３との間には、絶縁性樹脂から成る封止層１０が形成されている。さらに、配線基板２の半導体チップ搭載面と反対側の下面には、はんだボールのような外部接続用の電極（図示を省略する。）が配設されている。   A sealing layer 10 made of an insulating resin is formed between the wiring board 2 and the semiconductor chip 3. Further, an external connection electrode (not shown) such as a solder ball is disposed on the lower surface of the wiring board 2 opposite to the semiconductor chip mounting surface.

このように構成される第２の実施形態の半導体装置においては、第１の実施形態の半導体装置と同様に、半導体チップ３の機能素子Ａと長尺形状の電源バンプ５およびグランドバンプ６との距離の最大値がｐ／２となり、従来からのバンプ配置に比べて、機能素子Ａと電源供給用のバンプとの距離を短縮することができる。したがって、高性能デバイスにおける電源系の電圧降下を低減し、電気的特性に優れた半導体装置を得ることができる。   In the semiconductor device of the second embodiment configured as described above, as in the semiconductor device of the first embodiment, the functional element A of the semiconductor chip 3 and the elongated power supply bump 5 and ground bump 6 are provided. The maximum value of the distance is p / 2, and the distance between the functional element A and the power supply bump can be shortened as compared with the conventional bump arrangement. Therefore, the voltage drop of the power supply system in the high-performance device can be reduced, and a semiconductor device having excellent electrical characteristics can be obtained.

また、配線基板２側の電源バンプ接続用の電極パッド８およびグランドバンプ接続用の電極パッド９の一部が欠損したとしても、同じ列に属する他の電極パッド８，９がそれを補って接続点となるため、半導体チップ３のバンプとの間に十分な電気接続が得られる。さらに、第１の実施形態に比べて、配線基板２の電極パッド８，９間の配線形成が可能であり、配線の自由度が大きいという利点がある。   Even if part of the electrode pads 8 for power supply bump connection and the electrode pads 9 for ground bump connection on the wiring board 2 side is lost, the other electrode pads 8 and 9 belonging to the same column make up for the connection. Therefore, sufficient electrical connection can be obtained between the bumps of the semiconductor chip 3. Furthermore, compared to the first embodiment, it is possible to form a wiring between the electrode pads 8 and 9 of the wiring board 2 and there is an advantage that the degree of freedom of wiring is large.

以上の実施形態で説明された構成、形状、大きさおよび配置関係については、概略的に示したものにすぎず、また各構成の組成（材質）等については例示にすぎない。したがって、本発明は以上の実施形態に限定されるものではなく、特許請求の範囲に示される技術的思想の範囲を逸脱しない限り、さまざまな形態に変更することができる。   The configuration, shape, size, and arrangement relationship described in the above embodiments are merely schematically shown, and the composition (material) and the like of each configuration are merely examples. Therefore, the present invention is not limited to the above embodiment, and can be modified in various forms without departing from the scope of the technical idea shown in the claims.

本発明の第１の実施形態に係る半導体装置の構成を示す断面図である。1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention. 第１の実施形態における半導体チップのバンプの配置を示す平面図である。It is a top view which shows arrangement | positioning of the bump of the semiconductor chip in 1st Embodiment. 図２の破線で囲まれた部分を拡大して示す図である。It is a figure which expands and shows the part enclosed with the broken line of FIG. 従来からの半導体装置における半導体チップのバンプ配置の一例を示す平面図である。It is a top view which shows an example of bump arrangement | positioning of the semiconductor chip in the conventional semiconductor device. 狭ピッチのバンプ配置を示す平面図である。It is a top view which shows bump arrangement | positioning of a narrow pitch. 図５の破線で囲まれた部分を拡大して示す図である。It is a figure which expands and shows the part enclosed with the broken line of FIG. 本発明の第２の実施形態に係る半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device which concerns on the 2nd Embodiment of this invention.

符号の説明Explanation of symbols

１…半導体装置、２…配線基板、３…半導体チップ、４…信号バンプ、５…電源バンプ、６…グランドバンプ、７…信号バンプ接続用の電極パッド、８…電源バンプ接続用の電極パッド、９…グランドバンプ接続用の電極パッド、１０…絶縁性樹脂から成る封止層。   DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... Wiring board, 3 ... Semiconductor chip, 4 ... Signal bump, 5 ... Power supply bump, 6 ... Ground bump, 7 ... Electrode pad for signal bump connection, 8 ... Electrode pad for power supply bump connection, 9 ... Electrode pads for connecting ground bumps, 10 ... Sealing layer made of insulating resin.

Claims (5)

一方の主面に複数の電極パッドを有する配線基板と、一方の主面に複数の突起状電極を有し、この突起状電極形成面を下向きにして前記配線基板の前記電極パッド形成面上に搭載された半導体素子を備え、前記半導体素子の前記突起状電極と前記配線基板の対応する電極パッドとを接合して成る半導体装置であり、
前記半導体素子の電源供給領域および／または接地領域に形成された前記突起状電極は長尺形状を有し、かつこれら長尺形状の突起状電極はそれぞれの長辺方向を平行に揃えて配列されていることを特徴とする半導体装置。 A wiring board having a plurality of electrode pads on one main surface and a plurality of protruding electrodes on one main surface, with the protruding electrode forming surface facing down on the electrode pad forming surface of the wiring board A semiconductor device comprising a mounted semiconductor element, wherein the protruding electrode of the semiconductor element and a corresponding electrode pad of the wiring board are joined;
The protruding electrodes formed in the power supply region and / or the ground region of the semiconductor element have an elongated shape, and the elongated protruding electrodes are arranged with their long sides aligned in parallel. A semiconductor device characterized by that. 前記長尺形状の突起状電極の長辺の長さは、前記電源供給領域および／または接地領域の長さの１／３以上であることを特徴とする請求項１記載の半導体装置。   2. The semiconductor device according to claim 1, wherein a length of a long side of the long protruding electrode is 以上 or more of a length of the power supply region and / or a ground region. 前記半導体素子の長尺形状の突起状電極に対応する前記配線基板の電極パッドは、長尺形状を有しており、これらの長尺形状の電極パッドが、それぞれの長辺方向を平行に揃えかつ前記半導体素子の長尺形状の突起状電極と同じ向きに配列されていることを特徴とする請求項１または２記載の半導体装置。   The electrode pads of the wiring board corresponding to the long protruding electrodes of the semiconductor element have a long shape, and these long electrode pads align the long side directions in parallel. 3. The semiconductor device according to claim 1, wherein the semiconductor device is arranged in the same direction as the elongated projecting electrode of the semiconductor element. 前記半導体素子の長尺形状の突起状電極に対応する前記配線基板の電極パッドは、円形を有しており、これらの円形の電極パッドの複数個が対応する前記長尺形状の突起状電極と接合されていることを特徴とする請求項１または２記載の半導体装置。   The electrode pad of the wiring board corresponding to the long protruding electrode of the semiconductor element has a circular shape, and the long protruding electrode corresponding to a plurality of these circular electrode pads The semiconductor device according to claim 1, wherein the semiconductor device is bonded. 前記半導体素子と前記配線基板との間に絶縁性樹脂の封止層を有することを特徴とする請求項１乃至４のいずれか１項記載の半導体装置。   The semiconductor device according to claim 1, further comprising an insulating resin sealing layer between the semiconductor element and the wiring board.
JP2007302498A 2007-11-22 2007-11-22 Semiconductor device Withdrawn JP2009130074A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012209497A (en) * 2011-03-30 2012-10-25 Elpida Memory Inc Semiconductor device
JPWO2019016978A1 (en) * 2017-07-19 2020-06-18 日本電産リード株式会社 Imaging device, bump inspection device, and imaging method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012209497A (en) * 2011-03-30 2012-10-25 Elpida Memory Inc Semiconductor device
JPWO2019016978A1 (en) * 2017-07-19 2020-06-18 日本電産リード株式会社 Imaging device, bump inspection device, and imaging method
US11585652B2 (en) 2017-07-19 2023-02-21 Nidec Read Corporation Imaging device, bump inspection device, and imaging method

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