JP2005217264A - Semiconductor device, and its manufacturing method and manufacturing equipment - Google Patents

Semiconductor device, and its manufacturing method and manufacturing equipment Download PDF

Info

Publication number
JP2005217264A
JP2005217264A JP2004023276A JP2004023276A JP2005217264A JP 2005217264 A JP2005217264 A JP 2005217264A JP 2004023276 A JP2004023276 A JP 2004023276A JP 2004023276 A JP2004023276 A JP 2004023276A JP 2005217264 A JP2005217264 A JP 2005217264A
Authority
JP
Japan
Prior art keywords
bump
semiconductor
semiconductor element
semiconductor device
area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2004023276A
Other languages
Japanese (ja)
Inventor
Kazuhiro Ishikawa
和弘 石川
Yasuyuki Sakashita
靖之 阪下
Tadaaki Mimura
忠昭 三村
Noriyuki Nagai
紀行 永井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2004023276A priority Critical patent/JP2005217264A/en
Publication of JP2005217264A publication Critical patent/JP2005217264A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1182—Applying permanent coating, e.g. in-situ coating
    • H01L2224/11822—Applying permanent coating, e.g. in-situ coating by dipping, e.g. in a solder bath
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01077—Iridium [Ir]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Abstract

<P>PROBLEM TO BE SOLVED: To provide a connection structure which improves connection characteristics between a semiconductor element and gap perimeter of a semiconductor carrier substrate and realizes high heat dissipation. <P>SOLUTION: In the semiconductor element 1, a plurality of electrode pads 2a are arranged in the periphery 1a of the circuit formation surface of the semiconductor element, and at least one electrode pad 2b is arranged to interior of an area 1b which is region inside the electrode pads 2a of periphery. On the semiconductor carrier substrate 4, the semiconductor element is mounted. Bumps 3 whose diameters are different from each other are formed on the electrode pad 2a of the periphery and the electrode pad 2b of interior of the area, solder or conductive adhesive material 6 is imprinted to the bumps, and flip chip bonding is performed to the semiconductor carrier substrate. From the above configuration, a gap generated according to curvature profiles of the semiconductor element and the semiconductor carrier substrate can be corrected by controlling dimension of the bumps 3, so that OPEN fraction defective in an assembly inspection process is reduced greatly, and assembly yield can be improved. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

この発明は、従来の半導体素子の外周部にペリフェラル配置した複数個あるＡｌ等の電極パッド部と、回路形成内部に一つ以上のＡｌ等の電極パッド部を形成させたパッドオンエレメント（ＰＯＥ）と称するＰＯＥ素子（半導体素子）を用いてフリップチップ（ＦＣ）実装した構造を有する半導体装置に関するものである。特に、フリップチップするＰＯＥ素子を支持する半導体キャリア基板の凹型の大きな反りにより、半導体素子の中央部（エリア内部）に形成したスタットバンプボンディング（ＳＢＢ）部の接続性及びその接合信頼性を大きく低下するのを防止できるエリアパッド化した小型半導体装置とその製造方法に関するものである。本発明の半導体キャリア基板の大きな反り（２０〜３０μｍ）にも対応できるエリアパッド化した小型半導体装置は、従来のＦＣ実装構造の半導体装置では対応できなかった半導体素子の特性向上の為の電源補強（ＩＲドロップ電圧低下防止）等が十分できるものである。また、エリアパッド内部に複数の電気的接続端子である電極パッドを有していることから、半導体装置の多ピン化や高機能化、また高い放熱性を実現することができることを目的とした半導体装置およびその製造方法、およびバンプ寸法（径と高さ）を半導体素子の内外の領域で可変する製造装置に関するものである。   The present invention relates to a pad-on-element (POE) in which a plurality of electrode pads made of Al or the like are arranged peripherally on the outer periphery of a conventional semiconductor element, and one or more electrode pads made of Al or the like are formed inside a circuit formation. The present invention relates to a semiconductor device having a structure in which flip chip (FC) mounting is performed using a POE element (semiconductor element). In particular, due to the large concave warp of the semiconductor carrier substrate that supports the POE element to be flip-chiped, the connectivity of the stat bump bonding (SBB) part formed in the central part (inside the area) of the semiconductor element and its bonding reliability are greatly reduced. The present invention relates to a small semiconductor device having an area pad that can be prevented and a manufacturing method thereof. The small semiconductor device formed as an area pad that can cope with a large warp (20 to 30 μm) of the semiconductor carrier substrate of the present invention is a power supply reinforcement for improving the characteristics of a semiconductor element that cannot be handled by a semiconductor device having a conventional FC mounting structure. (IR drop voltage drop prevention) and the like can be sufficiently achieved. In addition, since the area pad has electrode pads that are a plurality of electrical connection terminals, the semiconductor device has the purpose of achieving higher pin count, higher functionality, and higher heat dissipation of the semiconductor device. The present invention relates to an apparatus, a manufacturing method thereof, and a manufacturing apparatus capable of changing bump dimensions (diameter and height) in regions inside and outside a semiconductor element.

以下、図面を参照して従来のフリップチップ（ＦＣ）実装したエリアパッド化半導体装置について説明する。図１３および図１４は、従来のＦＣ方式で実装した、エリアパッド化した小型半導体装置の断面図である。   A conventional flip-chip (FC) mounted area pad semiconductor device will be described below with reference to the drawings. FIG. 13 and FIG. 14 are cross-sectional views of a small semiconductor device formed as an area pad mounted by the conventional FC method.

図１３および図１４に示すように、従来のエリアパッド化した小型半導体装置では、半導体素子１を支持する半導体キャリア基板４の大きな反り（例えば凹型）の影響により、前記半導体素子１とそれを支持する前記半導体キャリア基板４の中央部であるエリア内部１ｂで、大きな隙間（ギャップ）が発生した。この現象により、前記半導体素子１のエリア内部１ｂとその中央部１ｃのＡｌ電極パッド２ｂ，２ｃ上に形成したＡｕ等のバンプ３ｂ，３ｃ（半田或いは導電性接着材６を介している）と前記半導体キャリア基板４上の複数の配線電極部５とが十分接続されずＯＰＥＮ不良となり、エリアパッド化した小型半導体装置の組立歩留（％）が大きく低下する構造であった。また、組立後においてＡｕバンプ３と半導体キャリア４の配線電極部５とが、半田或いは導電性接着材６を介して、絶縁材であるエポキシ系樹脂７を充填被覆させて電気的に接続されていても、熱疲労試験等の信頼性試験において負荷される熱ストレスの影響により、半田或いは導電性接着材６の部分でクラックが発生し、Ａｕバンプ３（半田或いは導電性接着材６を介している）と半導体キャリア基板４上の配線電極部５とが接続されたＳＢＢ接続部の接続抵抗値が高くなり、ＯＰＥＮ不良に至るといった技術的課題があった。更に、従来技術では、エリア内部に電源強化用の端子が増加し、他ピン化だけでなく、高機能化されたことで、従来よりも高い放熱性も必要であった。しかし、エリア内部１ｂでは、接続不良が多発しており、ＯＰＥＮ不良だけでなく、半導体素子１の熱的破壊を生じるといった致命的な技術的課題も発生していた。   As shown in FIGS. 13 and 14, in a conventional small semiconductor device having an area pad, the semiconductor element 1 and the semiconductor element 1 are supported by the influence of a large warp (for example, a concave shape) of the semiconductor carrier substrate 4 that supports the semiconductor element 1. A large gap (gap) occurred in the area inside 1b, which is the central portion of the semiconductor carrier substrate 4. Due to this phenomenon, bumps 3b and 3c made of Au or the like formed on the Al electrode pads 2b and 2c in the area 1b and the central portion 1c of the semiconductor element 1 (via solder or conductive adhesive 6) and the above-mentioned The plurality of wiring electrode portions 5 on the semiconductor carrier substrate 4 are not sufficiently connected, resulting in an OPEN failure, and the assembly yield (%) of the small semiconductor device formed as an area pad is greatly reduced. Further, after assembly, the Au bump 3 and the wiring electrode portion 5 of the semiconductor carrier 4 are electrically connected by being filled with an epoxy resin 7 which is an insulating material via solder or a conductive adhesive 6. However, cracks occur in the solder or the conductive adhesive 6 due to the influence of thermal stress applied in a reliability test such as a thermal fatigue test, and the Au bump 3 (via the solder or the conductive adhesive 6). There is a technical problem that the connection resistance value of the SBB connection portion to which the wiring electrode portion 5 on the semiconductor carrier substrate 4 is connected is increased, leading to an OPEN failure. Furthermore, in the prior art, the number of terminals for strengthening the power supply is increased in the area, and not only the other pins but also the higher functions are required, so that higher heat dissipation than before is required. However, connection failures frequently occur in the area 1b, and not only the OPEN failure but also a fatal technical problem such as thermal destruction of the semiconductor element 1 has occurred.

尚、エリアパッド化した小型半導体装置のＦＣ接続特性に大きく起因する半導体キャリア基板４の面全体の反り量は重要なファクターであるが、前記半導体キャリア基板４の反り量を現行の２０〜３０μｍより小さくすることは現実的には不可能であり、半導体キャリア基板４の反り形状に対応できる新たな接続手段が必要不可欠であった。   Note that the warpage amount of the entire surface of the semiconductor carrier substrate 4 due to the FC connection characteristics of the small-sized semiconductor device formed as an area pad is an important factor, but the warpage amount of the semiconductor carrier substrate 4 is less than the current 20 to 30 μm. In practice, it is impossible to reduce the size, and a new connection means that can cope with the warped shape of the semiconductor carrier substrate 4 is indispensable.

以上の背景技術により、実験的にＡｕバンプ３の高さを可変する試みをした。その結果、前記ギャップが大きい部分では、Ａｕバンプ３の寸法（高さと径）を大きくすることでＳＢＢ接続性の向上化が図れる傾向が確認できた。しかし、半導体素子１上の領域で、部分的にＡｕバンプ３の高さを可変することは、生産性に大きな課題があった。   An attempt was made to experimentally vary the height of the Au bump 3 using the background art described above. As a result, it was confirmed that the SBB connectivity can be improved by increasing the size (height and diameter) of the Au bump 3 in the portion where the gap is large. However, partially changing the height of the Au bump 3 in the region on the semiconductor element 1 has a big problem in productivity.

つまり、図１５（改善前のバンプ形成工程）に示すように、改善前の工程では、Ａｕバンプ３の高さが最も低いＡｕバンプ３ａを形成し、その後、Ａｕバンプ３を平坦（以下レベリングと称す）する。次に、２番目に高いバンプ３ｂを形成し、またレベリングを行う。そして、更に最も高いＡｕバンプ３ｃを形成し、またレベリングを行うといた、多大なバンプ形成工程を有しており、生産工程数と生産タクトに多大な時間を要するといった製造的観点の大きな技術課題があった（例えば、特許文献１，２）。
特開平１0−２９４３３０号公報 特開昭６３−６５４３１号公報 That is, as shown in FIG. 15 (bump formation process before improvement), in the process before improvement, the Au bump 3a having the lowest height of the Au bump 3 is formed, and then the Au bump 3 is flattened (hereinafter referred to as leveling). Call it). Next, the second highest bump 3b is formed and leveling is performed. Further, there is a great technical problem in terms of manufacturing, such as forming the highest Au bump 3c and performing leveling, and having a great number of bump forming steps, which requires a lot of time for the number of production steps and production tact. (For example, Patent Documents 1 and 2).
JP-A-10-294330 Japanese Unexamined Patent Publication No. 63-65431

上記のように従来の半導体装置の構造では、回路形成部を上面にした半導体素子の外周部では、電極パッド部に形成したＡｕバンプと半田或いは導電性接着材がエポキシ系の樹脂を充填被覆させ、半導体キャリア基板の配線電極部と接続されているが、半導体素子の電源補強に対応しているエリア内部では、半導体キャリア基板の反り形状（特に凹型）の影響により、半導体素子と半導体キャリア基板間のギャップが大きくなる為、形成したＡｕバンプ（半田或いは導電性接着材が転写済み）と半導体キャリア基板の配線電極部とが十分接続されずにＯＰＥＮ不良となり組立歩留（％）が大きく低下するという技術的課題があった。また、回路形成部を上面にした半導体素子の外周部とエリア内部に形成したＡｕバンプ（半田或いは導電性接着材が転写済み）と半導体キャリア基板の配線電極部とがエポキシ系樹脂を介して、一旦、電気的に接続された場合においても熱疲労試験等の信頼性試験において負荷される熱ストレスの影響により、半田或いは導電性接着材の部分のクラック発生により、Ａｕバンプと半導体キャリアの配線電極部との接続抵抗値が著しく高くなり、ＯＰＥＮ不良に至るといった技術課題が発生していた。   As described above, in the structure of the conventional semiconductor device, the Au bump formed on the electrode pad portion and the solder or the conductive adhesive is covered with the epoxy resin on the outer peripheral portion of the semiconductor element with the circuit forming portion on the upper surface. In the area that is connected to the wiring electrode part of the semiconductor carrier substrate, but corresponds to the power supply reinforcement of the semiconductor element, due to the warp shape (particularly concave) of the semiconductor carrier substrate, between the semiconductor element and the semiconductor carrier substrate Since the gap of the gap becomes larger, the formed Au bump (solder or conductive adhesive has been transferred) and the wiring electrode portion of the semiconductor carrier substrate are not sufficiently connected, resulting in an OPEN failure and a significant decrease in assembly yield (%). There was a technical problem. In addition, the outer peripheral part of the semiconductor element with the circuit forming part on the top surface, the Au bump formed in the area (solder or conductive adhesive has been transferred) and the wiring electrode part of the semiconductor carrier substrate via the epoxy resin, Once electrically connected, Au bump and semiconductor carrier wiring electrodes due to the occurrence of cracks in the solder or conductive adhesive due to the effects of thermal stress applied in reliability tests such as thermal fatigue tests As a result, a technical problem has arisen in that the connection resistance value with the portion becomes extremely high, leading to an OPEN failure.

今後、半導体素子設計において必要性が高まっている電源強化対策（半導体素子の回路形成部を構成するメモリ−機能やプロセッサー部等の電源強化）を実現させるには、半導体素子のエリア内部に電極パッド部を形成し、半田或いは導電性接着材を転写塗布させたＡｕバンプが、エポキシ系の樹脂材を介して半導体キャリアの配線電極部と高い接続信頼性を確保する接続構造を実現させることが必要である。そのためには、半導体キャリア基板の反りに対応できる新たな接続手段が必要不可欠であった。   In the future, in order to realize power supply strengthening measures (memory function that constitutes the circuit formation part of the semiconductor element, power supply of the processor part, etc.), which is becoming increasingly necessary in the design of semiconductor elements, an electrode pad is provided inside the area of the semiconductor element. It is necessary to realize a connection structure that secures high connection reliability with the wiring electrode part of the semiconductor carrier through the epoxy resin material by the Au bump formed by transferring the solder and the conductive adhesive. It is. For this purpose, a new connection means that can cope with the warp of the semiconductor carrier substrate is indispensable.

したがって、この発明の目的は、前記従来のエリアパッド化した半導体装置を解決するもので、フリップチップ実装するＰＯＥと称する半導体素子とそれを支持する半導体キャリア基板の反り形状に応じて大きな隙間（ギャップ）が発生し、半導体装置の接続信頼性が低下することを防止することである。更に、エリア内部に電源補強の端子が増加したことによる他ピン・高機能化されたことで、従来よりも高い放熱性が必要であったが、前記ギャップ部分でのＯＰＥＮ不良の影響による致命的な半導体素子の熱的破壊が発生することを防止することである。従って、前記ギャップ部周辺の接続特性を向上させ、且つ高放熱化を実現させる接続構造を有したエリアパッド化した半導体装置およびその製造方法および製造装置を提供することである。   Accordingly, an object of the present invention is to solve the above-described conventional area pad semiconductor device, and a large gap (gap) according to the warped shape of the semiconductor element called POE to be flip-chip mounted and the semiconductor carrier substrate supporting it. ) Occurs and the connection reliability of the semiconductor device is prevented from being lowered. Furthermore, due to the increased functionality of other pins due to the increase in power supply terminals inside the area, higher heat dissipation was required than before, but it was fatal due to the effect of OPEN failure at the gap. It is to prevent the thermal breakdown of a semiconductor element. Accordingly, it is an object of the present invention to provide an area pad semiconductor device having a connection structure that improves the connection characteristics around the gap portion and realizes high heat dissipation, and a method and apparatus for manufacturing the same.

前記課題を解決するためにこの発明の請求項１記載の半導体装置は、半導体素子の回路形成面の外周部に複数個の電極パッド部を配列し、かつ、前記外周部の前記電極パッド部より内側の領域であるエリア内部に、一つ以上の電極パッド部を設けた半導体素子と、前記半導体素子を搭載する半導体キャリア基板とを備えた半導体装置であって、前記外周部の電極パッド部と前記エリア内部の電極パッド部に、互いに寸法が異なるバンプを形成し、前記バンプに半田あるいは導電性接着材を転写させ、前記半導体キャリア基板とフリップチップ接続した。   In order to solve the above-mentioned problem, a semiconductor device according to claim 1 of the present invention has a plurality of electrode pad portions arranged on an outer peripheral portion of a circuit formation surface of a semiconductor element, and moreover than the electrode pad portion of the outer peripheral portion. A semiconductor device comprising: a semiconductor element provided with one or more electrode pad portions inside an area which is an inner region; and a semiconductor carrier substrate on which the semiconductor element is mounted, wherein the electrode pad portion on the outer peripheral portion; Bumps having different dimensions were formed on the electrode pad portion inside the area, solder or a conductive adhesive was transferred to the bumps, and flip-chip connected to the semiconductor carrier substrate.

請求項２記載の半導体装置は、請求項１記載の半導体装置において、前記バンプは、ボールボンディング法によるスタッドバンプ法で形成した。   According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the bump is formed by a stud bump method using a ball bonding method.

請求項３記載の半導体装置は、請求項１記載の半導体装置において、前記バンプの寸法は、前記半導体キャリア基板の反り形状に応じて、外周部よりエリア内部のバンプを大きく、または、エリア内部より外周部のバンプを大きくした。   According to a third aspect of the present invention, in the semiconductor device according to the first aspect, the bump has a larger size in the area than the outer peripheral portion or in the area of the bump, depending on the warp shape of the semiconductor carrier substrate. The bumps on the outer periphery were enlarged.

請求項４記載の半導体装置は、請求項３記載の半導体装置において、前記バンプは、隣接する電極パッド間と、バンプ上に転写塗布される半田あるいは導電性接着材とがショートしない範囲でバンプの寸法を大きくすることができる許容範囲を設けている。   According to a fourth aspect of the present invention, there is provided the semiconductor device according to the third aspect of the present invention, wherein the bumps are formed so that the bumps are not short-circuited between adjacent electrode pads and the solder or conductive adhesive that is transferred onto the bumps. An allowable range in which the size can be increased is provided.

請求項５記載の半導体装置は、請求項３記載の半導体装置において、前記寸法が大きいバンプは、表面積を大きくするために窪みを形成したバンプ台座部を有し、かつ、前記バンプ台座部の周辺部より高くした凸部を中央部に有する形状である。   The semiconductor device according to claim 5 is the semiconductor device according to claim 3, wherein the bump having the large dimension has a bump pedestal portion in which a depression is formed in order to increase a surface area, and the periphery of the bump pedestal portion. It is the shape which has the convex part made higher than the part in the center part.

請求項６記載の半導体装置の半導体装置の製造方法は、半導体素子の回路形成面の外周部に形成した電極パッド部と、前記外周部の電極パッド部より内側の領域であるエリア内部に形成した電極パッド部に、互いに寸法が異なるバンプを形成する工程と、凹型または凸型を有したレベリングツールを用いて、前記外周部と前記エリア内部のバンプを同時に一括平坦化するレベリング工程と、高さが異なるレベリング済みのバンプに半田或いは導電性接着材を転写し、半導体キャリア基板にフリップチップ接続するフリップチップ実装工程と、樹脂を前記半導体素子と前記半導体キャリア基板の間に充填硬化させる封止工程とを含む。   The method of manufacturing a semiconductor device of the semiconductor device according to claim 6, wherein the electrode pad portion formed on the outer peripheral portion of the circuit formation surface of the semiconductor element and the inside of the area that is a region inside the electrode pad portion of the outer peripheral portion are formed. A step of forming bumps having different dimensions on the electrode pad portion, a leveling step of simultaneously flattening the outer peripheral portion and the bumps inside the area using a concave or convex leveling tool, and a height Flip chip mounting process for transferring solder or conductive adhesive to leveled bumps having different levels and flip chip connection to a semiconductor carrier substrate, and sealing process for filling and curing resin between the semiconductor element and the semiconductor carrier substrate Including.

請求項７記載の半導体装置の半導体装置の製造装置は、請求項６記載の半導体装置の製造方法に用いる凹型または凸型を有したレベリングツールを備えた半導体装置の製造装置であって、前記レベリングツールは、半導体素子の寸法より大きく、かつ、高い剛性および熱伝導率と耐熱性を有した金属材質からなる。   A semiconductor device manufacturing apparatus of a semiconductor device according to claim 7 is a semiconductor device manufacturing apparatus provided with a leveling tool having a concave shape or a convex shape, which is used in the method of manufacturing a semiconductor device according to claim 6, wherein the leveling is performed. The tool is made of a metal material that is larger than the size of the semiconductor element and has high rigidity, thermal conductivity, and heat resistance.

請求項８記載の半導体装置の半導体装置の製造装置は、請求項６記載の半導体装置の製造方法に用いる凹型または凸型を有したレベリングツールを備えた半導体装置の製造装置であって、半導体素子の回路形成面の外周部とエリア内部の電極パッド部に形成したバンプを、半導体素子を回転させることなく、前記レベリングツールで、一括で同時に平坦化することができる。   A semiconductor device manufacturing apparatus of a semiconductor device according to claim 8 is a semiconductor device manufacturing apparatus having a concave or convex leveling tool used in the method of manufacturing a semiconductor device according to claim 6, wherein the semiconductor element The bumps formed on the outer peripheral portion of the circuit forming surface and the electrode pad portion inside the area can be simultaneously flattened simultaneously by the leveling tool without rotating the semiconductor element.

この発明の請求項１記載の半導体装置によれば、外周部の電極パッド部とエリア内部の電極パッド部に、互いに寸法が異なるバンプを形成し、バンプに半田あるいは導電性接着材を転写させ、半導体キャリア基板とフリップチップ接続したので、フリップチップ実装するＰＯＥと称する半導体素子とそれを支持する半導体キャリア基板の反り形状に応じて発生する大きな隙間である、ギャップをバンプの寸法（径や高さ）をコントロール補正することで、組立検査工程でのＯＰＥＮ不良率を大きく低減させ、組立歩留の向上を図ることができる。また、このようにギャップの補正を講じることで、バンプ接続部は電気的に安定した構造を維持し、従来発生していたＯＰＥＮ不良の発生を防止することができることで、熱疲労等による熱ストレスも十分緩和でき、高い接続信頼性を確保することもできる。   According to the semiconductor device of the first aspect of the present invention, bumps having different dimensions are formed on the electrode pad portion in the outer peripheral portion and the electrode pad portion in the area, and the solder or the conductive adhesive is transferred to the bump. Since the semiconductor carrier substrate is flip-chip connected, the gap is a dimension of the bump (diameter or height), which is a large gap generated according to the warp shape of the semiconductor element called POE to be flip-chip mounted and the semiconductor carrier substrate that supports it. ) Is controlled and corrected, the OPEN failure rate in the assembly inspection process can be greatly reduced, and the assembly yield can be improved. In addition, by correcting the gap in this way, the bump connection portion can maintain an electrically stable structure and can prevent the occurrence of the OPEN failure that has occurred in the past. Can be sufficiently relaxed, and high connection reliability can be secured.

請求項２では、バンプは、ボールボンディング法によるスタッドバンプ法で形成したので、スタットバンプボンディング（ＳＢＢ）部の接続信頼性を確保維持できる。   According to the second aspect of the present invention, since the bump is formed by the stud bump method by the ball bonding method, the connection reliability of the stat bump bonding (SBB) portion can be secured and maintained.

請求項３では、バンプの寸法は、半導体キャリア基板の反り形状に応じて、外周部よりエリア内部のバンプを大きく、または、エリア内部より外周部のバンプを大きくしたので、半導体キャリア基板の反り形状が凹型の場合は、半導体素子のエリア内部の電極パッドに形成するバンプ寸法（特にバンプ径やバンプ高さ）を大きく形成させることでギャップを補正することが可能となる。また、半導体キャリア基板の反り形状が凸型の場合は、凹型の場合と逆に、半導体素子の外周部の電極パッドに形成するバンプ寸法を、エリア内部よりも大きく形成させることで、半導体素子の外周部の大きなギャップを補正することが同様にできる。これにより高温高荷重を負荷することなくバンプ部の接続性の安定化が図れる。   According to the third aspect of the present invention, the bump size is such that the bump in the area is larger than the outer peripheral portion or the bump in the outer peripheral portion is larger than the inner portion according to the warped shape of the semiconductor carrier substrate. In the case of a concave type, it is possible to correct the gap by forming a large bump size (especially bump diameter and bump height) formed on the electrode pad inside the area of the semiconductor element. In addition, when the warp shape of the semiconductor carrier substrate is a convex shape, contrary to the concave shape, the bump size formed on the electrode pad on the outer peripheral portion of the semiconductor element is formed larger than the inside of the area. It is possible to correct a large gap in the outer peripheral portion in the same manner. As a result, the connectivity of the bump portion can be stabilized without applying a high temperature and high load.

請求項４では、バンプは、隣接する電極パッド間と、バンプ上に転写塗布される半田あるいは導電性接着材とがショートしない範囲でバンプの寸法を大きくすることができる許容範囲を設けているので、レベリング後のバンプに転写塗布する半田あるいは導電性接着材と隣接するバンプや電極パッドとショートを起こさないようにできる。   According to a fourth aspect of the present invention, the bump has an allowable range in which the size of the bump can be increased without causing a short circuit between the adjacent electrode pads and the solder or conductive adhesive transferred onto the bump. It is possible to prevent a short circuit from occurring between the bump or electrode pad adjacent to the solder or conductive adhesive that is transferred and applied to the bump after leveling.

請求項５では、寸法が大きいバンプは、表面積を大きくするために窪みを形成したバンプ台座部を有し、かつ、バンプ台座部の周辺部より高くした凸部を中央部に有する形状であるので、レベリング後のバンプに転写塗布する半田或いは導電性接着材を十分に転写確保することができ、安定した接続歩留（％）と高いバンプの接続信頼性を確保維持できる。さらに、発熱する半導体素子からの熱を従来の外周部だけからでなく、エリア内部のバンプ接続部からも熱放散する経路が増加したことにより、熱抵抗値を従来の２０〜３０％程度も低下させることができ、致命的であった半導体素子の熱的破壊をも防止できる。   In claim 5, the bump having a large dimension has a bump pedestal portion in which a depression is formed in order to increase the surface area, and a convex portion higher than the peripheral portion of the bump pedestal portion is formed in the central portion. Thus, it is possible to sufficiently ensure transfer of solder or conductive adhesive to be applied to the bumps after leveling, and to secure and maintain a stable connection yield (%) and high connection reliability of the bumps. Furthermore, the heat resistance value is reduced by about 20 to 30% of the conventional value due to an increase in the number of paths that dissipate heat from the heat generating semiconductor element not only from the conventional outer peripheral part but also from the bump connection part inside the area. It is possible to prevent thermal destruction of the fatal semiconductor element.

この発明の請求項６記載の半導体装置の製造方法によれば、半導体素子の回路形成面の外周部に形成した電極パッド部と、外周部の電極パッド部より内側の領域であるエリア内部に形成した電極パッド部に、互いに寸法が異なるバンプを形成する工程と、凹型または凸型を有したレベリングツールを用いて、外周部とエリア内部のバンプを同時に一括平坦化するレベリング工程とを含むので、半導体素子の外周部とエリア内部のバンプ形状は異なっており、バンプ高さが高い方に凹みを設けたレベリングツールを用いて、半導体素子の外周部とエリア内部に形成したそれぞれのバンプを同時に一括でレベリングすることで、レベリング工程に費やす時間を大きく低減し、生産性が著しく向上できる。また、ギャップが大きい部で、バンプ高さを可変した部分があれば、レベリングツールの凹部を調整することで、自由自在にバンプ高さを調整することが可能となる。   According to the method of manufacturing a semiconductor device according to claim 6 of the present invention, the electrode pad portion formed on the outer peripheral portion of the circuit formation surface of the semiconductor element and the inner portion of the outer peripheral portion which is a region inside the electrode pad portion are formed. Since the electrode pad portion includes a step of forming bumps having different dimensions from each other and a leveling step of simultaneously flattening the outer peripheral portion and the bumps in the area at the same time using a concave or convex leveling tool, The bump shape on the outer periphery of the semiconductor element is different from that on the inside of the area. Using a leveling tool with a recess on the higher bump height, the bumps formed on the outer periphery of the semiconductor element and the area are simultaneously By leveling, the time spent in the leveling process can be greatly reduced, and productivity can be significantly improved. Further, if there is a portion with a large gap and a bump height that is variable, the bump height can be freely adjusted by adjusting the recess of the leveling tool.

従って、従来の半導体装置（半導体素子の外周部のみに電極パッドを有していた半導体装置）では対応できなかった半導体素子の特性向上の為の電源補強（ＩＲドロップ電圧低下防止）等が十分できるだけでなく、エリアパッド内部に複数の電気的接続端子である電極パッドを有していることから、半導体装置の多ピン化や高機能化の実現だけでなく、高放熱化にも十分に対応できる。   Therefore, power supply reinforcement (preventing IR drop voltage drop) for improving the characteristics of semiconductor elements, which could not be handled by conventional semiconductor devices (semiconductor devices having electrode pads only on the outer periphery of the semiconductor elements), etc., is as much as possible. In addition, since the electrode pads that are a plurality of electrical connection terminals are provided inside the area pad, not only can the semiconductor device have a higher pin count and higher functionality, but it can also cope with higher heat dissipation. .

この発明の請求項７記載の半導体装置の製造装置によれば、請求項６記載の半導体装置の製造方法に用いる凹型または凸型を有したレベリングツールを備えた半導体装置の製造装置であって、レベリングツールは、半導体素子の寸法より大きく、かつ、高い剛性および熱伝導率と耐熱性を有した金属材質からなるので、半導体素子の回路形成面の外周部とエリア内部のバンプを同時に一括平坦化することができる。   According to a semiconductor device manufacturing apparatus of a seventh aspect of the present invention, there is provided a semiconductor device manufacturing apparatus provided with a leveling tool having a concave shape or a convex shape used in the method of manufacturing a semiconductor device according to the sixth aspect, The leveling tool is made of a metal material that is larger than the dimensions of the semiconductor element and has high rigidity, thermal conductivity, and heat resistance, so the outer peripheral part of the circuit formation surface of the semiconductor element and the bumps in the area can be flattened simultaneously. can do.

この発明の請求項８記載の半導体装置の製造装置によれば、請求項６記載の半導体装置の製造方法に用いる凹型または凸型を有したレベリングツールを備えた半導体装置の製造装置であって、半導体素子の回路形成面の外周部とエリア内部の電極パッド部に形成したバンプを、半導体素子を回転させることなく、レベリングツールで、一括で同時に平坦化することができるので、レベリング工程に費やす時間を大きく低減し、生産性が著しく向上できる。   According to a semiconductor device manufacturing apparatus as set forth in claim 8 of the present invention, there is provided a semiconductor device manufacturing apparatus provided with a leveling tool having a concave shape or a convex shape used in the method of manufacturing a semiconductor device according to claim 6, The bumps formed on the outer periphery of the circuit formation surface of the semiconductor element and the electrode pad inside the area can be simultaneously planarized with a leveling tool without rotating the semiconductor element, so the time spent on the leveling process Can be greatly reduced, and productivity can be remarkably improved.

以下、本発明の半導体装置及びその製造方法に関する実施形態について図面を参照しながら説明する。   Hereinafter, embodiments of a semiconductor device and a manufacturing method thereof according to the present invention will be described with reference to the drawings.

この発明の第１の実施の形態を図１および図２に基づいて説明する。図１は、本発明の第１の実施形態の半導体装置を示す断面図、図２はその概略平面図である。   A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention, and FIG. 2 is a schematic plan view thereof.

図１および図２に示すように、半導体素子１の回路形成面の外周部１ａに複数個の電極パッド部２ａを配列し、かつ、外周部１ａの電極パッド部２ａより内側の領域であるエリア内部１ｂに、一つ以上の電極パッド部２ｂを設けた半導体素子１と、半導体素子１を搭載する半導体キャリア基板４とを備えている。   As shown in FIG. 1 and FIG. 2, an area which is a region inside the plurality of electrode pad portions 2 a arranged on the outer peripheral portion 1 a of the circuit forming surface of the semiconductor element 1 and inside the electrode pad portion 2 a of the outer peripheral portion 1 a. The inside 1b includes a semiconductor element 1 provided with one or more electrode pad portions 2b, and a semiconductor carrier substrate 4 on which the semiconductor element 1 is mounted.

この場合、回路形成面を上面した半導体素子１上の外周部１ａとエリア内部１ｂの領域にあるＡｌ等の電極パッド部２（２ａ，２ｂ）に、それぞれ、Ａｕバンプ３の寸法（径と高さ）や形状を変えたＡｕバンプ３（３ａ，３ｂ）が、それぞれ半導体キャリア基板４上の複数の配線電極部５に半田或いは導電性接着材６を介して、液状の絶縁性を有したエポキシ系樹脂７が充填被覆されて電気的に接続されたフリップチップ実装構造を有している。尚、半導体キャリア基板４は、その裏面に外部端子８を有し、複数の配線電極部５と外部端子８とは半導体キャリア基板４内に形成されたビア９により内部接続されている。   In this case, the dimensions (diameter and height) of the Au bump 3 are respectively applied to the electrode pad portion 2 (2a, 2b) made of Al or the like in the region of the outer peripheral portion 1a and the area inside 1b on the semiconductor element 1 with the circuit formation surface facing up. In other words, the Au bumps 3 (3a, 3b) having different shapes are respectively bonded to a plurality of wiring electrode portions 5 on the semiconductor carrier substrate 4 via solder or conductive adhesives 6 and have liquid insulating properties. It has a flip chip mounting structure in which the resin 7 is filled and coated and electrically connected. The semiconductor carrier substrate 4 has an external terminal 8 on its back surface, and the plurality of wiring electrode portions 5 and the external terminal 8 are internally connected by vias 9 formed in the semiconductor carrier substrate 4.

この図１および図２に示す第１の実施形態の場合、前記半導体キャリア基板４の反りが凹型の場合であることから、半導体素子１上のエリア内部１ｂの電極パッド部２ｂに形成するバンプ３ｂを、外周部１ａの電極パッド部２ａ上に形成するバンプ３ａの径（φ）と高さ（ｈ）より、約１〜１．５の範囲で大きくしている。尚、Ａｕバンプ３の寸法を大きくする最大規格の範囲としては、レベリング後のＡｕバンプ３に転写塗布する半田或いは導電性接着材６と隣接するＡｕバンプ３や電極パッド２とショートを起さない範囲でＡｕバンプ３の形状を管理しているものである。また、前記記載の半導体素子１と半導体キャリア基板４との大きな隙間（ギャップ）部分を補正させるために、Ａｕバンプ３の寸法を大きくするだけでなく、半田或いは導電性接着材６を十分に転写塗布できるようにＡｕバンプ３の台座部分の表面積を大きくするため、バンプ台座部３−１に窪みをつけ、且つバンプ台座部３−１の周辺部より中央部の凸部を高くした形状を有したことを特徴とする構造を有している。   In the case of the first embodiment shown in FIGS. 1 and 2, since the warp of the semiconductor carrier substrate 4 is a concave type, the bump 3 b formed on the electrode pad portion 2 b in the area inside 1 b on the semiconductor element 1. Is made larger in the range of about 1 to 1.5 than the diameter (φ) and height (h) of the bump 3a formed on the electrode pad portion 2a of the outer peripheral portion 1a. Note that the maximum standard range for increasing the size of the Au bump 3 is that no short circuit occurs between the Au bump 3 and the electrode pad 2 adjacent to the solder or conductive adhesive 6 to be transferred and applied to the Au bump 3 after leveling. The shape of the Au bump 3 is managed within the range. Further, in order to correct a large gap (gap) portion between the semiconductor element 1 and the semiconductor carrier substrate 4 described above, not only the size of the Au bump 3 is increased, but also the solder or the conductive adhesive 6 is sufficiently transferred. In order to increase the surface area of the pedestal portion of the Au bump 3 so that it can be applied, the bump pedestal portion 3-1 has a recess and the central convex portion is higher than the peripheral portion of the bump pedestal portion 3-1. It has a structure characterized by the above.

この発明の第２の実施の形態を図３および図４に基づいて説明する。図３は、本発明の第２の実施形態の半導体装置を示す断面図、図４はその概略平面図である。本実施形態は、半導体キャリア基板４の反り形状が凸型を示す場合である。第１の実施形態と同一部分には同一符号を付す。   A second embodiment of the present invention will be described with reference to FIGS. FIG. 3 is a sectional view showing a semiconductor device according to the second embodiment of the present invention, and FIG. 4 is a schematic plan view thereof. In the present embodiment, the warp shape of the semiconductor carrier substrate 4 is a convex shape. The same parts as those in the first embodiment are denoted by the same reference numerals.

図３および図４に示すように、回路形成面を上面した半導体素子１上の外周部１ａとエリア内部１ｂの領域にあるＡｌ等の電極パッド部２ａ，２ｂに、それぞれ、Ａｕバンプ３の寸法（径と高さ）や形状を変えたＡｕ等のバンプ３（３ａ，３ｂ）が、それぞれ半導体キャリア基板４上の複数の配線電極部５に半田或いは導電性接着材６を介して、液状の絶縁性を有したエポキシ系樹脂７が充填被覆されて電気的に接続されたフリップチップ実装構造を有している。尚、半導体キャリア基板４は、その裏面に外部端子８を有し、複数の配線電極部５と外部端子８とは半導体キャリア基板４内に形成されたビア９により内部接続されている。   As shown in FIG. 3 and FIG. 4, the dimensions of the Au bumps 3 are respectively formed on the electrode pad portions 2 a and 2 b made of Al or the like in the outer peripheral portion 1 a on the semiconductor element 1 with the circuit forming surface on the upper surface and the area inside 1 b. The bumps 3 (3a, 3b) such as Au (diameter and height) and the shape are changed to a plurality of wiring electrode portions 5 on the semiconductor carrier substrate 4 via solder or conductive adhesive 6 respectively. It has a flip chip mounting structure in which an epoxy resin 7 having insulating properties is filled and coated and electrically connected. The semiconductor carrier substrate 4 has an external terminal 8 on its back surface, and the plurality of wiring electrode portions 5 and the external terminal 8 are internally connected by vias 9 formed in the semiconductor carrier substrate 4.

この図３および図４に示す第２の実施形態の場合は、前記半導体キャリア基板４の反りが凸型をしている為、第１の実施形態とは逆に、半導体素子１上のエリア内部１ｂの電極パッド部２ｂに形成するバンプ３ｂより、外周部１ａの電極パッド部２ａ上に形成するバンプ３ａの寸法である径（φ）と高さ（ｈ）を、約１〜１．５の範囲で大きくしているものである。尚、Ａｕバンプ３の形状を大きくする最大規格の範囲しては、第１の実施形態と同じ管理規準で実施管理しているものである。また、前記記載の第１の実施形態と同様に、半導体素子１と半導体キャリア基板４との大きな隙間（ギャップ）部分を補正させるために、Ａｕバンプ３の寸法を大きくするだけでなく、半田或いは導電性接着材６を十分に転写塗布できるようにバンプ台座部３−１の表面積を大きくするため、バンプ台座部３−１に窪みをつけ、且つバンプ台座部３−１の周辺部より中央部の凸部を高くした形状を有する構造にしている。   In the case of the second embodiment shown in FIGS. 3 and 4, since the warp of the semiconductor carrier substrate 4 is convex, the area inside the semiconductor element 1 is contrary to the first embodiment. The diameter (φ) and the height (h), which are the dimensions of the bump 3a formed on the electrode pad portion 2a of the outer peripheral portion 1a, are about 1 to 1.5 from the bump 3b formed on the electrode pad portion 2b of 1b. It is something that is larger in range. The range of the maximum standard for enlarging the shape of the Au bump 3 is managed and managed according to the same management standard as in the first embodiment. Further, as in the first embodiment described above, in order to correct a large gap (gap) portion between the semiconductor element 1 and the semiconductor carrier substrate 4, not only the size of the Au bump 3 is increased, but also solder or In order to increase the surface area of the bump pedestal 3-1 so that the conductive adhesive 6 can be sufficiently transferred and applied, a depression is formed in the bump pedestal 3-1 and the central portion of the bump pedestal 3-1. It has the structure which raised the convex part of this.

次に、第１および第２の実施形態において、半導体素子１とそれを支持する半導体キャリア基板４とがフリップチップ実装した際、半導体キャリア基板４の反り形状に応じて発生する大きな隙間のギャップを補正するために、半導体素子１の外周部１ａとエリア内部１ｂ領域に異なる寸法と形状を有したＡｕバンプ３を形成する半導体装置の製造方法について説明する。   Next, in the first and second embodiments, when the semiconductor element 1 and the semiconductor carrier substrate 4 that supports the semiconductor element 1 are flip-chip mounted, a gap with a large gap generated according to the warp shape of the semiconductor carrier substrate 4 is formed. A description will be given of a method for manufacturing a semiconductor device in which Au bumps 3 having different dimensions and shapes are formed in the outer peripheral portion 1a and the inner area 1b of the semiconductor element 1 for correction.

まず、半導体キャリア基板４の反り形状が凹型の場合における半導体素子１上へのＡｕバンプ３形成に伴う本発明の第１の実施形態の半導体装置の製造方法を図５に基づいて説明する。   First, the manufacturing method of the semiconductor device according to the first embodiment of the present invention accompanying the formation of the Au bump 3 on the semiconductor element 1 when the warp shape of the semiconductor carrier substrate 4 is concave will be described with reference to FIG.

図１および図５に示すように、半導体素子１の回路形成面の外周部に形成した電極パッド部２ａと、外周部の電極パッド部２ａより内側の領域であるエリア内部に形成した電極パッド部２ｂに、互いに寸法が異なるバンプ３ａ，３ｂを形成する工程と、凹型または凸型を有したレベリングツール１０を用いて、外周部とエリア内部のバンプ３ａ，３ｂを同時に一括平坦化するレベリング工程とを行う。半導体素子の外周部とエリア内部のバンプ高さを変える手法としては、同一のキャピラリで、外周部とエリア内部を異なるサイズのバンプを形成させ、半導体素子寸法より大きなレベリングツールを用いて、半導体素子の外周部とエリア内部のバンプを同時に一括レベリングする。   As shown in FIGS. 1 and 5, the electrode pad portion 2a formed on the outer peripheral portion of the circuit forming surface of the semiconductor element 1 and the electrode pad portion formed in the area that is an area inside the electrode pad portion 2a on the outer peripheral portion. A step of forming bumps 3a and 3b having different dimensions on 2b, and a leveling step of simultaneously flattening the bumps 3a and 3b in the outer periphery and the area at the same time by using a leveling tool 10 having a concave or convex shape. I do. As a method of changing the bump height in the outer periphery and area inside the semiconductor element, bumps of different sizes are formed on the outer periphery and area in the same capillary, and the semiconductor element is used by using a leveling tool larger than the semiconductor element dimension. Simultaneously level the outer perimeter and bumps in the area at the same time.

この場合、半導体素子１上の外周部１ａの電極パッド２ａにＡｕバンプ３ａを形成する。また、エリア内部１ｂ領域の電極パッド２ｂ上にＡｕバンプ３ｂ（前記３ａより寸法が大きい）を形成する。尚、前記Ａｕバンプ３ａより寸法が大きいＡｕバンプ３ｂ部の台座形状は表面積を大きくするため、バンプ台座部３−１に窪みをつけ、且つバンプ台座部３−１の周辺部より中央部の凸部を高くした形状を有している。そして、前記Ａｕバンプ３（３ａ，３ｂ）を形成した向きに、半導体素子１のサイズより大きく、且つ、強い剛性と高い熱伝導性と耐熱性のある金属材から成ることを特徴としたレベリングツール１０−１で、形成済みのＡｕバンプ３（３ａ，３ｂ）のレベリングを実施する。この際、半導体素子１の外周部１ａとエリア内部１ｂの領域に形成しているＡｕバンプ３（３ａ，３ｂ）は、それぞれの領域において、バンプ３の高さが異なるため、前記レベリングツール１０−１の形状を凹型に設けたことで、異なるバンプ３の高さの状態で、半導体素子１上の外周部１ａとエリア内１ｂ領域のＡｕバンプ３を同時に一括でレベリングすることができる生産性の優れたレベリング機構を有したバンプ形成方法の工程を有しているものである。   In this case, Au bumps 3 a are formed on the electrode pads 2 a on the outer peripheral portion 1 a on the semiconductor element 1. Also, Au bumps 3b (having dimensions larger than 3a) are formed on the electrode pads 2b in the area inside 1b. Note that the pedestal shape of the Au bump 3b portion, which is larger than the Au bump 3a, increases the surface area, so that the bump pedestal portion 3-1 is recessed and the central portion of the bump pedestal portion 3-1 is convex. It has a shape with a raised part. And a leveling tool characterized in that the Au bump 3 (3a, 3b) is formed of a metal material that is larger than the size of the semiconductor element 1 and has a high rigidity, high thermal conductivity, and heat resistance. In 10-1, leveling of the formed Au bump 3 (3a, 3b) is performed. At this time, the Au bumps 3 (3a, 3b) formed in the regions of the outer peripheral portion 1a and the area inside 1b of the semiconductor element 1 have different heights of the bumps 3 in the respective regions. Therefore, the leveling tool 10- Since the shape of 1 is provided in a concave shape, the outer bump 1a on the semiconductor element 1 and the Au bump 3 in the area 1b can be simultaneously leveled at the same time with different bump 3 heights. It has the process of the bump formation method which has the outstanding leveling mechanism.

本実施形態では、特に、半導体キャリア基板の反り形状は凹型が多く、この場合、半導体素子と半導体キャリア基板のギャップは、半導体素子の電源補強用電極パッドを有するエリア内部が大きくなる。そのため、半導体素子のエリア内部の電極パッドに形成するＡｕバンプ寸法（特にバンプ径やバンプ高さ）を大きく形成させることでギャップを補正することが可能となり、高温高荷重を負荷することなくＳＢＢ部の接続性の安定化が図れるといった手段を講じている。   In this embodiment, in particular, the warp shape of the semiconductor carrier substrate is often concave, and in this case, the gap between the semiconductor element and the semiconductor carrier substrate is large inside the area having the power supply reinforcing electrode pad of the semiconductor element. Therefore, it is possible to correct the gap by forming a large Au bump size (especially bump diameter and bump height) formed on the electrode pad inside the area of the semiconductor element, and the SBB portion without applying a high temperature and high load. Measures are taken to stabilize the connectivity.

一方、半導体キャリア基板４の反り形状が凸型の場合における半導体素子１上へのＡｕ等のバンプ３の形成に伴う本発明の第２の実施形態の半導体装置の製造方法を図６に基づいて説明する。   On the other hand, a method of manufacturing a semiconductor device according to the second embodiment of the present invention accompanying the formation of bumps 3 such as Au on the semiconductor element 1 when the warp shape of the semiconductor carrier substrate 4 is a convex shape is shown in FIG. explain.

図３および図６に示すように、半導体素子１上の外周部１ａのＡｌ電極パッド２ａにＡｕバンプ３ａを形成する。また、エリア内部１ｂ領域の電極パッド部２ｂにＡｕバンプ３ｂ（前記３ａのパンプ寸法が大きい）を形成する。尚、バンプ３の寸法が大きいＡｕバンプ３ａ部の台座形状は表面積を大きくするため、バンプ台座部３−１に窪みをつけ、且つバンプ台座部３−１の周辺部より中央部の凸部を高くした形状を有している。   As shown in FIGS. 3 and 6, Au bumps 3 a are formed on the Al electrode pads 2 a on the outer peripheral portion 1 a on the semiconductor element 1. Further, an Au bump 3b (the bump size of the 3a is large) is formed on the electrode pad portion 2b in the area 1b. In addition, in order to increase the surface area of the pedestal shape of the Au bump 3a portion where the bump 3 is large, the bump pedestal portion 3-1 is recessed, and the convex portion at the center from the peripheral portion of the bump pedestal portion 3-1. Has a raised shape.

以下、前記Ａｕバンプ３を形成する製造方法の第１の実施形態と同様に、Ａｕバンプ３（３ａ，３ｂ）を形成した向きに、半導体素子１の寸法より大きく、且つ強い剛性と高い熱伝導性と耐熱性がある金属材から成ることを特徴としたもう一つのレベリングツール１０−２で、形成済みのＡｕバンプ３（３ａ，３ｂ）のレベリングを実施する。この際、半導体素子１の外周部１ａとエリア内部１ｂの領域に形成しているＡｕバンプ３（３ａ，３ｂ）は、それぞれの領域において、バンプ３の高さが異なるため、前記もう一つのレベリングツール１０−２の形状を凸型に設けたことで、異なるバンプ３の高さの状態で、半導体素子１上の外周部１ａとエリア内１ｂ領域のＡｕバンプ３を同時に一括でレベリングすることができる生産性の優れたレベリング機構を有したＡｕバンプ３の形成方法の工程を有するものである。   Hereinafter, in the same manner as in the first embodiment of the manufacturing method for forming the Au bump 3, the direction in which the Au bump 3 (3a, 3b) is formed is larger than the size of the semiconductor element 1 and has a strong rigidity and high heat conduction. The leveling of the formed Au bumps 3 (3a, 3b) is carried out with another leveling tool 10-2 characterized by being made of a metal material having heat resistance and heat resistance. At this time, the Au bumps 3 (3a and 3b) formed in the outer peripheral portion 1a and the inner area 1b of the semiconductor element 1 have different heights in the respective bumps. By providing the tool 10-2 in a convex shape, the outer bumps 1a on the semiconductor element 1 and the Au bumps 3 in the area 1b can be simultaneously leveled at the same time with different bump 3 heights. It has a process of forming Au bumps 3 having a leveling mechanism with excellent productivity.

次に、半導体キャリア基板４の反り形状が凹型に著しく大きい場合の半導体素子１上へのＡｕバンプ３の形成に伴う本発明の第３の実施形態の半導体装置の製造方法を図７および図８に基づいて説明する。第１および第２の実施形態と同一部分には同一符号を付して説明を省略する。   Next, a method of manufacturing a semiconductor device according to the third embodiment of the present invention accompanying the formation of the Au bump 3 on the semiconductor element 1 when the warped shape of the semiconductor carrier substrate 4 is remarkably large will be described with reference to FIGS. Based on The same parts as those in the first and second embodiments are denoted by the same reference numerals and description thereof is omitted.

図７および図８に示すように、半導体素子１に形成するＡｕバンプ３は、特に半導体素子１の中央部１ｃを最も高く、外周部１ａを最も低く、また中央部と外周部の中間部１ｂにもバンプ寸法が異なるＡｕバンプ３（３ａ〜３ｃ）を形成している。この場合も前記同様に、２段階の凹型形状を有する別のレベリングツール１０−３の形状を用いることで、容易に半導体素子１と半導体キャリア基板４のＦＣ実装時の大きな隙間のギャップを補正することができるレベリング済みのＡｕバンプ３（３ａ〜３ｃ）を形成することができるものである。   As shown in FIG. 7 and FIG. 8, the Au bump 3 formed on the semiconductor element 1 has the highest central part 1c, the lowest outer peripheral part 1a, and the middle part 1b between the central part and the outer peripheral part. In addition, Au bumps 3 (3a to 3c) having different bump dimensions are formed. Also in this case, similarly to the above, by using the shape of another leveling tool 10-3 having a two-stage concave shape, a gap of a large gap at the time of FC mounting of the semiconductor element 1 and the semiconductor carrier substrate 4 is easily corrected. A leveled Au bump 3 (3a to 3c) that can be formed can be formed.

更に、半導体キャリア基板４の反り形状が凸型に著しく大きい場合の半導体素子１上へのＡｕバンプ３の形成に伴う本発明の第４の実施形態の半導体装置の製造方法を図９および図１０に基づいて説明する。第１および第２の実施形態と同一部分には同一符号を付して説明を省略する。   Further, a method of manufacturing a semiconductor device according to the fourth embodiment of the present invention accompanying the formation of Au bumps 3 on the semiconductor element 1 when the warp shape of the semiconductor carrier substrate 4 is remarkably large is shown in FIGS. Based on The same parts as those in the first and second embodiments are denoted by the same reference numerals and description thereof is omitted.

図９および図１０に示すように、半導体素子１に形成するＡｕバンプ３は、特に半導体素子１の外周部１ａを最も高く、中央部１ｃを最も低く、また中央部と外周部の中間部１ｂにも異なるバンプ寸法のＡｕバンプ３（３ａ〜３ｃ）を形成している。この場合も前記同様に、２段階の凸型形状を有する別のレベリングツール１０−４の形状を用いることで、容易に半導体素子１と半導体キャリア基板４のＦＣ実装時の大きな隙間のギャップを補正することができるもう一つのレベリング済みのＡｕバンプ３（３ａ〜３ｃ）を形成することができるものである。   As shown in FIG. 9 and FIG. 10, the Au bump 3 formed on the semiconductor element 1 has the highest outer peripheral portion 1a, the lowest central portion 1c, and the middle portion 1b between the central portion and the outer peripheral portion. In addition, Au bumps 3 (3a to 3c) having different bump dimensions are formed. Also in this case, similarly to the above, by using the shape of another leveling tool 10-4 having a two-stage convex shape, a gap of a large gap at the time of FC mounting of the semiconductor element 1 and the semiconductor carrier substrate 4 is easily corrected. It is possible to form another leveled Au bump 3 (3a to 3c) that can be formed.

次に、上記実施形態において、前記エリアパッド配列の半導体素子１（Ａｕバンプ３形成済み）と半導体キャリア基板４を半田或いは導電性接着材６を介して電気的に接続し、その周辺を絶縁性のエポキシ系封止樹脂で充填被覆されたエリアパッド化した小型半導体装置の製造方法について、図１１および図１２を用いて以下、説明する。なお、図１１および図１２は第３の実施形態の半導体キャリア基板４が凹型の場合であるが、他の実施形態でも同様である。   Next, in the above embodiment, the semiconductor element 1 (with the Au bump 3 formed) and the semiconductor carrier substrate 4 in the area pad arrangement are electrically connected via solder or a conductive adhesive 6, and the periphery thereof is insulative. A method for manufacturing an area pad-filled small semiconductor device filled and coated with an epoxy-based sealing resin will be described below with reference to FIGS. 11 and 12 show the case where the semiconductor carrier substrate 4 of the third embodiment is concave, but the same applies to other embodiments.

図１１に示すように、回路形成部を上面にした半導体素子１上の外周部１ａの電極パッド２ａ部とエリア内部１ｂ，１ｃの電極パッド部２ｂ，２ｃに、Ａｕバンプ３の寸法や形状が異なるＡｕ等のバンプ３（３ａ〜３ｃ）を形成する工程（図１１（１））と、凹型を有した剛性力と高い熱伝導性と耐熱性を有した金属材から成るレベリングツール１０−３を用いて半導体素子１の外周部１ａとエリア内部１ｂ，１ｃに形成したＡｕバンプ３のレベリングを同時に一括して平坦化することができるバンプレベリング工程（図１１（２））とを有する。次に、Ａｕバンプ３の高さが異なるレベリング済みＡｕバンプ３に半田或いは導電性接着材６塗布した転写ステージ１１で転写し（図１１（３）、図１２（１））、複数の配線電極５を有する向きを上面にした半導体キャリア基板４上にＡｕバンプ３形成済みの半導体素子１をＦＣ実装し、その後、熱硬化するフリップチップ実装工程と、エポキシ系の封止樹脂７を半導体素子１と半導体キャリア基板４間に充填し、硬化させる封止工程（図１２（２））とを有していることを特徴としたエリアパッド化した小型半導体装置の製造方法である。   As shown in FIG. 11, the size and shape of the Au bump 3 are formed on the electrode pad 2a portion of the outer peripheral portion 1a and the electrode pad portions 2b and 2c of the inner areas 1b and 1c on the semiconductor element 1 with the circuit forming portion on the upper surface. A step of forming bumps 3 (3a to 3c) made of different Au or the like (FIG. 11 (1)), and a leveling tool 10-3 made of a metal material having a concave shape, rigidity, high thermal conductivity and heat resistance And a bump leveling step (FIG. 11 (2)) that can simultaneously level the leveling of the Au bumps 3 formed on the outer peripheral portion 1a of the semiconductor element 1 and the inner areas 1b and 1c. Next, the Au bumps 3 are transferred onto the leveled Au bumps 3 having different heights by the transfer stage 11 coated with solder or the conductive adhesive 6 (FIG. 11 (3), FIG. 12 (1)), and a plurality of wiring electrodes The semiconductor element 1 on which the Au bumps 3 are formed is FC-mounted on the semiconductor carrier substrate 4 with the orientation 5 having the upper surface, and then a flip chip mounting process in which the semiconductor element 1 is thermally cured and an epoxy-based sealing resin 7 is applied to the semiconductor element 1. And a sealing step (FIG. 12 (2)) for filling and curing between the semiconductor carrier substrate 4 and the manufacturing method of a small semiconductor device formed into an area pad.

以上説明したように、半導体素子１とそれを支持する半導体キャリア基板４とがフリップチップ実装した際、半導体キャリア基板４の反り形状に応じて発生する大きな隙間のギャップを補正するために、Ａｕバンプ３の寸法（径や高さ等）を大きくするだけでなく、半田或いは導電性接着材６を十分に転写塗布できるようにＡｕバンプ３の台座部分の表面積を大きくするため、バンプ台座部３−１に窪みをつけ、且つバンプ台座部３−１の周辺部より中央部の凸部を高くした形状を有している。また、半導体素子１のエリア内部（１ｂ，１ｃ）と外周部１ａの領域とで、Ａｕバンプ３の高さを可変するが、生産性を向上させるため、形成したＡｕバンプの寸法（径や高さ）に応じた、強い剛性と高い熱伝導性及び耐熱性のある凹み部を有した金属製のレベリングルール装置１０を用いて同時に一括レベリングすることができ、その後、レベリング済みのＡｕバンプ３に半田或いは導電性接着材６を転写塗布させ、半導体キャリア基板４上の複数の配線電極部５とが電気的に接続されている。尚、半導体素子１と半導体キャリア基板４の間に絶縁材であるエポキシ系の液状樹脂７が充填被覆された構造を有したエリアパッド化した小型半導体装置とその製造方法である。   As described above, when the semiconductor element 1 and the semiconductor carrier substrate 4 supporting the semiconductor element 1 are flip-chip mounted, in order to correct a gap of a large gap generated according to the warp shape of the semiconductor carrier substrate 4, the Au bump In order to increase the surface area of the pedestal portion of the Au bump 3 so that not only the dimensions (diameter, height, etc.) 3 but also the solder or the conductive adhesive 6 can be sufficiently transferred and applied, the bump pedestal portion 3- 1 has a shape in which a depression is formed and a convex portion at the center is made higher than the peripheral portion of the bump pedestal 3-1. Further, although the height of the Au bump 3 is varied between the area inside (1b, 1c) of the semiconductor element 1 and the region of the outer peripheral portion 1a, the dimensions (diameter and height) of the formed Au bump are improved in order to improve productivity. Can be simultaneously leveled using a metal leveling rule apparatus 10 having a strong rigidity, a high thermal conductivity, and a heat-resistant dent, and then the leveled Au bump 3 can be applied to the leveled Au bump 3. Solder or conductive adhesive 6 is transferred and applied, and the plurality of wiring electrode portions 5 on the semiconductor carrier substrate 4 are electrically connected. In addition, the semiconductor device 1 and the semiconductor carrier substrate 4 are an area pad miniaturized semiconductor device having a structure in which an epoxy liquid resin 7 as an insulating material is filled and coated, and a method for manufacturing the same.

本発明にかかる半導体装置およびその製造方法および製造装置は、半導体キャリア基板の反り形状に応じて発生する大きな隙間である、ギャップをバンプの寸法（径や高さ）をコントロール補正することで、組立検査工程でのＯＰＥＮ不良率を大きく低減させ、組立歩留の向上を図ることができる等の効果を有し、半導体素子の回路形成部の電源系を強化する電源補強を目的とするものだけでなく、シグナルパッドとしても利用する必要性のある半導体素子を用いた半導体装置すべてに有効である。   The semiconductor device and the manufacturing method and manufacturing device according to the present invention are assembled by controlling and correcting the bump size (diameter and height), which is a large gap generated according to the warp shape of the semiconductor carrier substrate. It has the effect of greatly reducing the OPEN failure rate in the inspection process and improving the assembly yield, and only for the purpose of power supply reinforcement that strengthens the power supply system of the circuit formation part of the semiconductor element. It is effective for all semiconductor devices using semiconductor elements that need to be used as signal pads.

本発明の第１の実施形態の半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device of the 1st Embodiment of this invention. 図１の概略平面図である。FIG. 2 is a schematic plan view of FIG. 1. 本発明の第２の実施形態の半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device of the 2nd Embodiment of this invention. 図３の概略平面図である。FIG. 4 is a schematic plan view of FIG. 3. 本発明の第１の実施形態の半導体装置の製造方法の断面図である。It is sectional drawing of the manufacturing method of the semiconductor device of the 1st Embodiment of this invention. 本発明の第２の実施形態の半導体装置の製造方法の断面図である。It is sectional drawing of the manufacturing method of the semiconductor device of the 2nd Embodiment of this invention. 本発明の第３の実施形態の半導体装置の製造方法の断面図である。It is sectional drawing of the manufacturing method of the semiconductor device of the 3rd Embodiment of this invention. 第３の実施形態の概略平面図である。It is a schematic plan view of 3rd Embodiment. 本発明の第４の実施形態の半導体装置の製造方法の断面図である。It is sectional drawing of the manufacturing method of the semiconductor device of the 4th Embodiment of this invention. 第４の実施形態の概略平面図である。It is a schematic plan view of 4th Embodiment. 本発明の実施形態の半導体装置の製造方法の工程断面図である。It is process sectional drawing of the manufacturing method of the semiconductor device of embodiment of this invention. 図１１の次の工程断面図である。FIG. 12 is a process sectional view subsequent to FIG. 11. 従来例の半導体装置の断面図である。It is sectional drawing of the semiconductor device of a prior art example. 図１３の概略平面図である。FIG. 14 is a schematic plan view of FIG. 13. 従来例のバンプ形成工程フロー図である。It is a bump formation process flowchart of a prior art example.

符号の説明Explanation of symbols

１ 半導体素子
1ａ 半導体素子上の外周部領域
1ｂ 半導体素子上のエリア内部領域
1ｃ 半導体素子上の中央部領域
２ Ａｌ等の電極パッド
2ａ 半導体素子上の外周部領域にあるＡｌ電極パッド部
２ｂ 半導体素子上のエリア内部領域にあるＡｌ電極パッド部
２ｃ 半導体素子上の中央部領域にあるＡｌ電極パッド部
３ Ａｕ等のバンプ
３ａ 半導体素子上の外周部領域にあるＡｌ電極パッド部に形成したＡｕバンプ
３ｂ 半導体素子上のエリア内部領域にあるＡｌ電極パッド部に形成したＡｕバンプ
３ｃ 半導体素子上の中央部領域にあるＡｌ電極パッド部に形成したＡｕバンプ
３−１ 表面積を大きくした山型やイカリ型等のバンプ台座部
４ 半導体キャリア基板
５ 半導体キャリア基板上にある複数の配線電極部
６ 半田或いは導電性接着材
７ 液状のエポキシ系封止樹脂
８ 半導体キャリア基板裏面の外部端子
９ 半導体キャリア基板内に形成したビア
１０ 強い剛性力と熱伝導性を有した金属材ら成るレベリングルール装置
１０−１凹型の逆形状を有したレベリングルール
１０−２ 凸型の逆形状を有するもう一つのレベリングツール
１０−３ ２段階の凹がたの逆形状を有するレベリングツール
１０−４ ２段階の凸型の逆形状を有するレベリングツール
１１ 半田或いは導電性接着材を塗布した転写ステージ 1 Semiconductor device
1a Peripheral area on semiconductor element
1b Area internal area on semiconductor element
1c Central region on semiconductor element 2 Electrode pad such as Al
2a Al electrode pad portion in outer peripheral region on semiconductor element 2b Al electrode pad portion in area inner region on semiconductor element 2c Al electrode pad portion in central region on semiconductor element 3 Bump such as Au 3a Semiconductor element Au bump 3b formed on the Al electrode pad portion in the outer peripheral region on the upper side Au bump 3c formed on the Al electrode pad portion in the inner area on the semiconductor element on the Al electrode pad portion in the central region on the semiconductor element Formed Au bumps 3-1 Bump pedestal parts such as ridges and squids with a large surface area 4 Semiconductor carrier substrate 5 Multiple wiring electrode parts on the semiconductor carrier substrate 6 Solder or conductive adhesive 7 Liquid epoxy seal Stop resin 8 External terminal on the back side of the semiconductor carrier substrate 9 Via formed in the semiconductor carrier substrate 10 Strong rigidity and thermal conductivity Leveling rule device made of a metal material 10-1 leveling rule having a concave reverse shape 10-2 another leveling tool having a convex reverse shape 10-3 leveling having a reverse shape of two-step concave shape Tool 10-4 Leveling tool having two-stage convex reverse shape 11 Transfer stage coated with solder or conductive adhesive

Claims (8)

半導体素子の回路形成面の外周部に複数個の電極パッド部を配列し、かつ、前記外周部の前記電極パッド部より内側の領域であるエリア内部に、一つ以上の電極パッド部を設けた半導体素子と、前記半導体素子を搭載する半導体キャリア基板とを備えた半導体装置であって、前記外周部の電極パッド部と前記エリア内部の電極パッド部に、互いに寸法が異なるバンプを形成し、前記バンプに半田あるいは導電性接着材を転写させ、前記半導体キャリア基板とフリップチップ接続したことを特徴とする半導体装置。   A plurality of electrode pad portions are arranged on the outer peripheral portion of the circuit formation surface of the semiconductor element, and one or more electrode pad portions are provided in an area that is an area inside the electrode pad portion of the outer peripheral portion. A semiconductor device comprising a semiconductor element and a semiconductor carrier substrate on which the semiconductor element is mounted, wherein bumps having different dimensions are formed on the electrode pad part in the outer peripheral part and the electrode pad part in the area, A semiconductor device, wherein a solder or a conductive adhesive is transferred to a bump and is flip-chip connected to the semiconductor carrier substrate. 前記バンプは、ボールボンディング法によるスタッドバンプ法で形成した請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the bump is formed by a stud bump method using a ball bonding method. 前記バンプの寸法は、前記半導体キャリア基板の反り形状に応じて、外周部よりエリア内部のバンプを大きく、または、エリア内部より外周部のバンプを大きくした請求項１記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the bump has a larger bump in the area than the outer peripheral portion or a larger bump in the outer peripheral portion than in the area, depending on the warp shape of the semiconductor carrier substrate. 前記バンプは、隣接する電極パッド間と、バンプ上に転写塗布される半田あるいは導電性接着材とがショートしない範囲でバンプの寸法を大きくすることができる許容範囲を設けている請求項３記載の半導体装置。   4. The bump according to claim 3, wherein the bump is provided with an allowable range in which the size of the bump can be increased within a range that does not cause a short circuit between the adjacent electrode pads and the solder or conductive adhesive transferred and applied onto the bump. Semiconductor device. 前記寸法が大きいバンプは、表面積を大きくするために窪みを形成したバンプ台座部を有し、かつ、前記バンプ台座部の周辺部より高くした凸部を中央部に有する形状である請求項３記載の半導体装置。   4. The bump having a large dimension has a bump pedestal portion in which a depression is formed in order to increase the surface area, and has a convex portion at a central portion that is higher than a peripheral portion of the bump pedestal portion. Semiconductor device. 半導体素子の回路形成面の外周部に形成した電極パッド部と、前記外周部の電極パッド部より内側の領域であるエリア内部に形成した電極パッド部に、互いに寸法が異なるバンプを形成する工程と、凹型または凸型を有したレベリングツールを用いて、前記外周部と前記エリア内部のバンプを同時に一括平坦化するレベリング工程と、高さが異なるレベリング済みのバンプに半田或いは導電性接着材を転写し、半導体キャリア基板にフリップチップ接続するフリップチップ実装工程と、樹脂を前記半導体素子と前記半導体キャリア基板の間に充填硬化させる封止工程とを含む半導体装置の製造方法。   Forming bumps having different dimensions on an electrode pad portion formed on an outer peripheral portion of a circuit forming surface of a semiconductor element and an electrode pad portion formed in an area inside the electrode pad portion on the outer peripheral portion; Using a leveling tool having a concave shape or a convex shape, a leveling step of simultaneously flattening the bumps in the outer peripheral portion and the area at the same time, and transferring solder or conductive adhesive to leveled bumps having different heights And a flip chip mounting step for flip chip connection to the semiconductor carrier substrate, and a sealing step for filling and curing a resin between the semiconductor element and the semiconductor carrier substrate. 請求項６記載の半導体装置の製造方法に用いる凹型または凸型を有したレベリングツールを備えた半導体装置の製造装置であって、前記レベリングツールは、半導体素子の寸法より大きく、かつ、高い剛性および熱伝導率と耐熱性を有した金属材質からなることを特徴とする半導体装置の製造装置。   7. A semiconductor device manufacturing apparatus comprising a concave or convex leveling tool used in the method of manufacturing a semiconductor device according to claim 6, wherein the leveling tool is larger than a semiconductor element and has high rigidity and An apparatus for manufacturing a semiconductor device, comprising a metal material having thermal conductivity and heat resistance. 請求項６記載の半導体装置の製造方法に用いる凹型または凸型を有したレベリングツールを備えた半導体装置の製造装置であって、半導体素子の回路形成面の外周部とエリア内部の電極パッド部に形成したバンプを、半導体素子を回転させることなく、前記レベリングツールで、一括で同時に平坦化することができることを特徴とする半導体装置の製造装置。   7. A semiconductor device manufacturing apparatus including a concave or convex leveling tool used in the method of manufacturing a semiconductor device according to claim 6, wherein the outer peripheral portion of the circuit formation surface of the semiconductor element and the electrode pad portion inside the area are provided. An apparatus for manufacturing a semiconductor device, characterized in that the formed bumps can be simultaneously planarized by the leveling tool without rotating the semiconductor element.
JP2004023276A 2004-01-30 2004-01-30 Semiconductor device, and its manufacturing method and manufacturing equipment Pending JP2005217264A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004023276A JP2005217264A (en) 2004-01-30 2004-01-30 Semiconductor device, and its manufacturing method and manufacturing equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004023276A JP2005217264A (en) 2004-01-30 2004-01-30 Semiconductor device, and its manufacturing method and manufacturing equipment

Publications (1)

Publication Number Publication Date
JP2005217264A true JP2005217264A (en) 2005-08-11

Family

ID=34906362

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004023276A Pending JP2005217264A (en) 2004-01-30 2004-01-30 Semiconductor device, and its manufacturing method and manufacturing equipment

Country Status (1)

Country Link
JP (1) JP2005217264A (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007109746A (en) * 2005-10-12 2007-04-26 Matsushita Electric Ind Co Ltd Semiconductor device and method of manufacturing same
JP2007329451A (en) * 2006-06-07 2007-12-20 Samsung Sdi Co Ltd Chip and planar display device equipped therewith
JP2008187881A (en) * 2007-01-31 2008-08-14 Seiko Epson Corp Actuator, manufacturing method thereof, optical scanner, and image forming apparatus
CN101964334A (en) * 2009-07-24 2011-02-02 株式会社村田制作所 Semiconductor package body and semiconductor package module
US8076787B2 (en) 2008-10-09 2011-12-13 Renesas Electronics Corporation Semiconductor device, manufacturing method thereof, and manufacturing method of semiconductor module
JP5002583B2 (en) * 2006-03-16 2012-08-15 パナソニック株式会社 Bump formation method
JP2012156453A (en) * 2011-01-28 2012-08-16 Kyocera Corp Wiring board and implementation structure thereof
US8703600B2 (en) 2009-06-02 2014-04-22 Kabushiki Kaisha Toshiba Electronic component and method of connecting with multi-profile bumps
CN104425415A (en) * 2013-08-27 2015-03-18 力领科技股份有限公司 Chip lug structure
JP2020178017A (en) * 2019-04-17 2020-10-29 日亜化学工業株式会社 Mounting method
WO2022215907A1 (en) * 2021-04-06 2022-10-13 (주)포인트엔지니어링 Positive electrode oxide film-based interposer for electrical connection and manufacturing method therefor, semiconductor package and manufacturing method therefor, multi-stage stacked-type semiconductor device and manufacturing method therefor, display and manufacturing method therefor
WO2023146257A1 (en) * 2022-01-28 2023-08-03 (주)포인트엔지니어링 Micro bumps and manufacturing method thereof

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4744259B2 (en) * 2005-10-12 2011-08-10 パナソニック株式会社 Semiconductor device and manufacturing method thereof
JP2007109746A (en) * 2005-10-12 2007-04-26 Matsushita Electric Ind Co Ltd Semiconductor device and method of manufacturing same
JP5002583B2 (en) * 2006-03-16 2012-08-15 パナソニック株式会社 Bump formation method
JP2007329451A (en) * 2006-06-07 2007-12-20 Samsung Sdi Co Ltd Chip and planar display device equipped therewith
JP2008187881A (en) * 2007-01-31 2008-08-14 Seiko Epson Corp Actuator, manufacturing method thereof, optical scanner, and image forming apparatus
US8076787B2 (en) 2008-10-09 2011-12-13 Renesas Electronics Corporation Semiconductor device, manufacturing method thereof, and manufacturing method of semiconductor module
US8405231B2 (en) 2008-10-09 2013-03-26 Renesas Electronics Corporation Semiconductor device, manufacturing method thereof, and manufacturing method of semiconductor module
US8703600B2 (en) 2009-06-02 2014-04-22 Kabushiki Kaisha Toshiba Electronic component and method of connecting with multi-profile bumps
CN101964334A (en) * 2009-07-24 2011-02-02 株式会社村田制作所 Semiconductor package body and semiconductor package module
JP2011029374A (en) * 2009-07-24 2011-02-10 Murata Mfg Co Ltd Semiconductor package and semiconductor package module
US8378501B2 (en) 2009-07-24 2013-02-19 Murata Manufacturing Co., Ltd. Semiconductor package and semiconductor package module
JP2012156453A (en) * 2011-01-28 2012-08-16 Kyocera Corp Wiring board and implementation structure thereof
CN104425415A (en) * 2013-08-27 2015-03-18 力领科技股份有限公司 Chip lug structure
JP2020178017A (en) * 2019-04-17 2020-10-29 日亜化学工業株式会社 Mounting method
JP7189441B2 (en) 2019-04-17 2022-12-14 日亜化学工業株式会社 Implementation method
WO2022215907A1 (en) * 2021-04-06 2022-10-13 (주)포인트엔지니어링 Positive electrode oxide film-based interposer for electrical connection and manufacturing method therefor, semiconductor package and manufacturing method therefor, multi-stage stacked-type semiconductor device and manufacturing method therefor, display and manufacturing method therefor
WO2023146257A1 (en) * 2022-01-28 2023-08-03 (주)포인트엔지니어링 Micro bumps and manufacturing method thereof

Similar Documents

Publication Publication Date Title
US6107685A (en) Semiconductor part and fabrication method thereof, and structure and method for mounting semiconductor part
US11276631B2 (en) Module and method of manufacturing module
JP2008166373A (en) Semiconductor device and its manufacturing method
US5814890A (en) Thin-type semiconductor package
JP2011166051A (en) Semiconductor device and method of manufacturing the same
US20060157865A1 (en) Circuit board and manufacturing method therefor and semiconductor package and manufacturing method therefor
JP2005217264A (en) Semiconductor device, and its manufacturing method and manufacturing equipment
KR20090070916A (en) Semiconductor device and manufacturing method thereof
US20200185290A1 (en) Semiconductor package having sealant bridge
JP2011171427A (en) Laminated semiconductor device
US6750552B1 (en) Integrated circuit package with solder bumps
JP2009105209A (en) Electronic device and method of manufacturing the same
JP2012064991A (en) Flip-chip bonded package
WO2010109703A1 (en) Electronic device, substrate, and method for manufacturing electronic device
US20080164604A1 (en) Heat dissipating semiconductor package
CN110164781B (en) Method for manufacturing electronic packaging piece
US20100283145A1 (en) Stack structure with copper bumps
JP2004253544A (en) Manufacturing method of semiconductor device
JPH08250835A (en) Method for mounting lsi package having metallic bump
JP2012015554A (en) Semiconductor device manufacturing method and multilayer semiconductor device manufacturing method
JP2002237546A (en) Semiconductor device and manufacturing method
US8315063B2 (en) Solder pad structure with high bondability to solder ball
JP4417974B2 (en) Manufacturing method of stacked semiconductor device
JP2009266972A (en) Laminated semiconductor module and method of manufacturing the same
JP2011249398A (en) Circuit device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20060511

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20060526

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20071214

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20071218

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20080408