JP2011166051A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a structure with narrow pitches while suppressing its cost in connection between upper and lower semiconductor devices stacked in POP. <P>SOLUTION: In the semiconductor device, in which on a first semiconductor device comprising a first substrate 100 and a first semiconductor chip 110 mounted thereon, a second semiconductor device comprising a second substrate and a second semiconductor chip mounted on the top surface thereof is mounted, at the undersurface of the second substrate, which faces the first semiconductor chip 110, a plurality of connection terminals electrically connected with the second semiconductor chip is provided, the first semiconductor device includes a plurality of bonding wires 120 having an arc convex upward on the upper side of the first substrate, the bonding wire 120 is electrically connected with the connection terminal at the vertex of the arc convex upward, and at least one of the bonding wires 120 is electrically connected with the first semiconductor chip 110 directly or indirectly. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a narrow connection terminal pitch between upper and lower semiconductor devices in a POP (Package on Package) in which different semiconductor devices are stacked, and freedom of combination between upper and lower semiconductor devices.

  In response to demands for miniaturization and higher functionality of various electronic devices such as mobile phones and digital still cameras, advanced packages that support higher functionality of semiconductor devices, faster processing speeds, lower costs, and shorter development periods Technology is required. One of the advanced package technologies is a semiconductor device having a POP (Package on Package) structure as shown in FIG. Here, in FIG. 37, each part is demonstrated easily. 5030 is an upper semiconductor device on which POP is laminated, 5001 is a lower semiconductor device on which POP is laminated, 5025 is a solder ball for connecting the upper semiconductor device 5030 and the lower semiconductor device 5001, and 5035 is an upper semiconductor device. The mold sealing resin of the semiconductor device 5030, 5031 is the resin substrate of the upper semiconductor device 5030, 5000 is the resin substrate of the lower semiconductor device 5001, 5015 is the solder ball disposed on the back layer of the resin substrate 5000, and 5010 is the lower A semiconductor chip mounted on the semiconductor device 5001 on the side, 5011 indicates a gold bump that electrically connects the semiconductor chip 5010 and the resin substrate 5000, and 5012 indicates an underfill that fixes the resin substrate 5000 and the semiconductor chip 5010. The upper semiconductor device 5030 and the lower semiconductor device 5001 are individually assembled independently, and then electrically connected via the solder balls 5025 by a reflow process.

  However, in the conventional POP structure, in order to secure the height of the semiconductor chip sandwiched between the upper and lower semiconductor packages, a solder ball having a large size corresponding to the height is required. There was a problem that the pitch could not be narrowed. As methods for solving the problem, there are methods such as Patent Document 1 and Patent Document 2.

Japanese Patent Laid-Open No. 2007-250764 JP 2007-287906 A

However, the configuration of Patent Document 1 has the following problems and is difficult to adopt.
(1) Since the cost for the intermediate substrate is added, the assembly cost is greatly increased.
(2) Since the number of steps for connecting the intermediate board increases, the assembly period is extended.
(3) It is difficult to ensure connection reliability due to two reflows for the solder balls on both sides of the intermediate board and an increase in the amount of warping due to the difference in configuration of the upper and lower packages.
(4) In order to improve connection reliability in response to (3), it is necessary to make the intermediate substrate larger than the original package size as shown in the upper right figure.
(5) Since the connection connecting the lower package and the upper package is increased from once to twice as much as the intermediate substrate is inserted, the connection position accuracy is deteriorated.

  Also, in the configuration of Patent Document 2, many steps are required to create a metal post, which is difficult to realize in terms of cost.

  The present invention has been made to solve such a problem, and solves the problem of increasing the number of connection terminals between upper and lower semiconductor devices to be stacked and narrowing the pitch by reducing the number of steps from the viewpoint of cost. With the goal.

  In order to achieve the above-described object, a semiconductor device of the present invention includes a first substrate and a first semiconductor device including a first semiconductor chip mounted on the first substrate, and a second substrate. And a second semiconductor device comprising a second semiconductor chip mounted on the upper surface of the second substrate, wherein the lower surface of the second substrate facing the first semiconductor chip is A plurality of connection terminals electrically connected to the second semiconductor chip are provided, and the first semiconductor device includes a plurality of bonding wires having a convex arc on the upper side of the first substrate. The bonding wire is electrically connected to the connection terminal at the top of an upwardly convex arc, and at least one of the bonding wires is directly or indirectly electrically connected to the first semiconductor chip. It was Configurations.

  An interposer may exist between the first substrate and the first semiconductor chip, and at least one end of the bonding wire may be on the interposer.

  The connection terminal is rectangular on the lower surface of the second substrate, and a long side of the rectangle extends in a direction connecting both ends of the bonding wire connected to the connection terminal.

  The connection terminal is rectangular on the lower surface of the second substrate, and a long side of the rectangle is inclined with respect to a direction connecting both ends of the bonding wire connected to the connection terminal. Can do.

  The semiconductor device may further include an insulator layer laminated on the lower surface of the second substrate, and the insulator layer may have a hole with the connection terminal as a bottom.

  The first semiconductor chip may have a rectangular plate shape, and a direction connecting both ends of the bonding wire may be inclined with respect to a rectangular side of the first semiconductor chip.

  The bonding wire may have a ground surface with the apex ground, and the ground surface and the connection terminal may be electrically connected.

  The bonding wire may include a first bonding wire and a second bonding wire, and the first bonding wire may have a greater distance from the first substrate to the apex than the second bonding wire. .

  At least one of the bonding wires may be configured to include two or more apexes of an upwardly convex arc.

  The bonding wire may include a third bonding wire that passes above the upper surface of the first semiconductor chip.

The first semiconductor device and the second semiconductor device can be configured to be bonded by at least two different types of adhesive members. The first manufacturing method of the present invention includes a first substrate and the first substrate. A semiconductor on which a second semiconductor device including a second substrate and a second semiconductor chip mounted on an upper surface of the second substrate is mounted on a first semiconductor device including the first semiconductor chip mounted on the semiconductor substrate. A method of manufacturing an apparatus, comprising: a step S for mounting a first semiconductor chip on a first substrate; a step A for providing a plurality of bonding wires having a convex arc on the upper side of the first substrate; Mounting a lower surface of the second substrate of the second semiconductor device on the first semiconductor device, wherein a plurality of connection terminals are provided on the lower surface of the second substrate; smell Thus, the connection terminal and the apex of the convex arc on the bonding wire are electrically connected.

  After Step A and before Step B, Step C for forming a resin layer for burying the bonding wire on the first substrate, and grinding the resin layer to expose the bonding wire The process D can be further included.

  In the step C, the region where the bonding wire exists can be configured to have a larger distance from the upper surface of the first substrate to the surface of the resin layer than the other region.

  The process further includes a step E of forming a resin layer on the first substrate so as to expose the apex of the convex arc on the bonding wire after the step A and before the step B. It can be.

  In the step E, a gap can be formed between the bonding wire and the resin layer immediately below the apex.

  The bonding wire includes a first bonding wire and a second bonding wire, and the first bonding wire has a greater distance from the first substrate to the apex than the second bonding wire. The first semiconductor device and the second semiconductor device are brought close to each other until the second semiconductor device and the second bonding wire are electrically connected, and then the first semiconductor device and the second semiconductor device are fixed. It can be set as the structure to do.

  In the step A, at least one position of both ends of the bonding wire can be selected from three or more terminals in the first semiconductor device according to the type of the second semiconductor device.

  In the step S, a plurality of the first semiconductor chips are mounted on a first substrate assembly in which a plurality of the first substrates are connected, and after the step A and before the step B, Sealing the first semiconductor chip on the first substrate assembly with a sealing resin, and cutting the first substrate assembly with the sealing resin into individual first substrates, and In the step T, at least a part of the bonding wires can be cut.

A second method of the present invention includes mounting a second substrate and an upper surface of the second substrate on a first semiconductor device including a first substrate and a first semiconductor chip mounted on the first substrate. A method of manufacturing a semiconductor device having a second semiconductor device provided with a second semiconductor chip, the step of mounting the first semiconductor chip on the first substrate, and above the first substrate Forming a plurality of bonding wires having convex arcs; forming a resin layer in which the bonding wires are embedded on the first substrate; grinding the resin layer to form the arcs of the bonding wires; Cutting the apex portion of the second semiconductor device to expose the cut surface, and mounting the lower surface of the second substrate of the second semiconductor device on the first semiconductor device B,
A plurality of connection terminals are provided on the lower surface of the second substrate, and the connection terminals and the cut surfaces of the bonding wires are electrically connected in the step B.

  According to the present invention, in a semiconductor device in which two semiconductor devices are stacked, the connection terminal pitch between the upper and lower semiconductor devices can be reduced at a low cost and the number of assembly steps is small, so that the short TAT is achieved. Can be assembled.

It is the simple sectional view which looked at the semiconductor device concerning a 1st embodiment from the side. It is the simple top view which looked at the semiconductor device concerning a 1st embodiment from the top. It is the simplified sectional view which looked at the mounting state of the upper and lower semiconductor devices concerning a 1st embodiment from the side. It is the simplified sectional view which looked at the completed state after mounting of the upper and lower semiconductor devices concerning a 1st embodiment from the side. It is the simplified sectional view which looked at the completed state after mounting of the upper and lower semiconductor devices concerning a 1st embodiment from the side. It is the simplified sectional view which looked at the completed state after mounting of the upper and lower semiconductor devices concerning a 1st embodiment from the side. It is the simplified sectional view which looked at the completed state after mounting of the upper and lower semiconductor devices concerning a 1st embodiment from the side. It is the simplified sectional view which looked at the completed state after mounting of the upper and lower semiconductor devices concerning a 1st embodiment from the side. It is the simple sectional view which looked at the semiconductor device concerning a 2nd embodiment from the side. It is the simple top view which looked at the semiconductor device concerning a 2nd embodiment from the top. It is the simplified sectional view which looked at the mounting state of the upper and lower semiconductor devices concerning a 2nd embodiment from the side. It is the simplified sectional view which looked at the mounting state of the upper and lower semiconductor devices concerning a 3rd embodiment from the side. It is the simplified sectional view which looked at the mounting state of the upper and lower semiconductor devices concerning a 4th embodiment from the side. It is the simplified sectional view which looked at the mounting state of the upper and lower semiconductor devices concerning a 5th embodiment from the side. It is the simplified sectional view which looked at the semiconductor device concerning a 6th embodiment from the side. It is the simplified sectional view which looked at the semiconductor device concerning a 6th embodiment from the side. It is the simplified sectional view which looked at the semiconductor device concerning a 7th embodiment from the side. It is the simple top view which looked at the semiconductor device concerning 7th Embodiment from the top. It is the simplified sectional view which looked at the completed state after mounting of the upper and lower semiconductor devices concerning an 8th embodiment from the side. It is the simplified sectional view which looked at the completed state after mounting of the upper and lower semiconductor devices concerning an 8th embodiment from the side. It is the comparison image figure which looked at the completion state after mounting of the upper and lower semiconductor devices concerning an 8th embodiment from the top. It is the simplified sectional view which looked at the completed state after mounting of the upper and lower semiconductor devices concerning a 9th embodiment from the side. It is the simplified sectional view which looked at the mounting state of the upper and lower semiconductor devices concerning a 10th embodiment from the side. It is the simple top view which looked at the semiconductor device concerning 10th Embodiment from the top. It is the simplified sectional view which looked at the completed state after mounting of the upper and lower semiconductor devices concerning a 10th embodiment from the side. It is the simplified sectional view which looked at the completed state after mounting of the upper and lower semiconductor devices concerning an 11th embodiment from the side. It is the simplified sectional view which looked at the completed state after mounting of the upper and lower semiconductor devices concerning an 11th embodiment from the side. It is the image figure which showed the combination of the starting point end point of the copper pad concerning 12th Embodiment. It is the image figure which showed the combination of the starting point end point of the copper pad concerning 12th Embodiment. It is the simplified sectional view which looked at the frame substrate of the semiconductor device concerning a 13th embodiment from the top. It is the simplified sectional view which looked at a part of semiconductor device on a frame substrate concerning a 13th embodiment from the side. It is the simple top view which looked at some semiconductor devices on the frame board | substrate concerning 13th Embodiment from the top. It is the simplified sectional view which looked at the completed state after mounting of the upper and lower semiconductor devices concerning a 13th embodiment from the side. It is the simplified sectional view which looked at the semiconductor device concerning a 14th embodiment from the side. It is the simplified sectional view which looked at the mounting state of the upper and lower semiconductor devices concerning a 15th embodiment from the side. It is the image figure which looked at the completion state of the semiconductor device concerning 15th Embodiment from the top. It is sectional drawing which looked at the semiconductor device concerning the conventional embodiment from the side.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, the same code | symbol is attached | subjected to the same element and description may be abbreviate | omitted. In each drawing, the thickness, length, and the like are different from the actual shape in creating the drawing. Further, the connection electrodes of the semiconductor chip, the connection terminals of the substrate, the wiring patterns, the vias, and the like are omitted or easy to illustrate.

(First embodiment)
The semiconductor device according to the first embodiment will be described with reference to FIGS.

  1, 5, 6, 7, and 8 are cross-sectional views of the configuration of the semiconductor device according to the present embodiment as viewed from the side. FIG. 2 is a plan view of the configuration of FIG. 1 viewed from above. FIG. 3 shows a state in which a semiconductor device as a memory is stacked on the semiconductor device of FIG. FIG. 4 is a cross-sectional view of the completed state after the upper and lower semiconductor devices are connected as viewed from the side through FIG.

  First, reference numerals in FIGS. 1 to 8 will be described.

  Reference numeral 100 denotes a substrate (first substrate) in the lower semiconductor device (first semiconductor device) on which the POP is stacked, 110 denotes a rectangular plate-like semiconductor chip (first semiconductor chip) mounted on the substrate 100, 111 is a gold bump for electrically connecting the substrate 100 and the semiconductor chip 110, 112 is an underfill for fixing the semiconductor chip 110 to the substrate 100, and 120 is a copper wire (bonding) for electrically connecting the upper and lower semiconductor devices. , 121 is a copper pad on the surface of the substrate 100 that is the starting point of the copper wire 120, and 122 is a copper pad on the surface of the substrate 100 that is the end point of the copper wire 120.

  Reference numeral 130 denotes an upper semiconductor device (second semiconductor device) on which the POP is stacked, 131 is a substrate (second substrate) in the semiconductor device 130, 132 is on the back surface of the substrate 131, and the top of the copper wire 120 is Copper lands (connection terminals) to be connected, 133 is a resist (insulator layer) that opens a part of the copper lands 132 and protects the wiring on the other side of the substrate, 140 is a temporary semiconductor device to be stacked by POP. It is an adhesive sheet (adhesive member) for fixing.

  In addition, 141 is an underfill that is injected after the upper and lower semiconductor devices are temporarily fixed, 123 is a gold wire that electrically connects the substrate 100 and the semiconductor chip 110, and 124 is a sealing resin that protects the semiconductor chip 110 and the gold wire 123. , 150 denotes a silicon interposer that relays the connection between the semiconductor chip 110 and the substrate 100.

  The copper wire 120 and the semiconductor chip 110 are electrically connected to each other through wiring on and inside the substrate 100, and the interposer 150 is also used as an intermediary.

  In the present embodiment and the following second to eleventh embodiments, the material of each component is not particularly limited, and as an upper semiconductor device, no matter how a semiconductor chip is mounted, Not a problem. In the drawings of the present embodiment, the upper semiconductor device describes a package covered with a mold sealing resin in a state where semiconductor chips are stacked.

  Next, the semiconductor device according to the present embodiment will be described.

First, the upper semiconductor device and the lower semiconductor device of the semiconductor device according to the present embodiment are individually assembled and inspected, and then the upper and lower semiconductor devices are connected to form a completed type.
1 and 2, components and configurations indicated by 100, 110, 111, and 112 of the lower semiconductor device are mounted by a general flip-chip method that has already been commercialized, and will be described in detail. Is omitted.

In this embodiment, in addition to the configuration of the conventional semiconductor device, a copper wire 120 is connected to connect to the upper semiconductor device. The copper wire 120 has an upwardly convex arc, the apex of the arc is arranged from the outer peripheral side of the semiconductor device, and the apex height is set higher than the back surface of the semiconductor chip 110. Further, since the copper wire 120 needs to have a strength that does not cause wire collapse when connected to the upper semiconductor device, a thick wire having a diameter of 80 μm is used. However, the material and the wire diameter are not particularly defined in the present invention because there are other options depending on the cost and assembly conditions. (For example, if a thicker 250 μm diameter wire is used, the required height can already be achieved with the wire diameter, so it is possible to connect just by rubbing the copper wire on the board surface, and suppress variations in height. Becomes easier)
Also, the starting and ending copper pads 121 and 122 that receive the copper wire 120 are plated with gold to prevent oxidation, and one of the copper pads is electrically connected to the semiconductor chip 110 through the substrate wiring. ing. However, the power supplied to the upper semiconductor device via the lower semiconductor device may not be connected to the semiconductor chip 110 in some cases. Furthermore, it is desirable that the copper wire 120 is also used as one of the substrate wirings to facilitate the substrate wiring.
Next, a state where the upper semiconductor device is mounted on the lower semiconductor device will be described with reference to FIGS.

  A gold-plated copper land 132 is disposed on the back surface side of the substrate 131 of the upper semiconductor device 130, and the shape of the copper land 132 is rectangular so that there is no problem even if the apex position of the copper wire 120 is slightly shifted. It is possible to absorb the positional deviation of the apex. The long side of the rectangle extends in the longitudinal direction of the copper wire 120, that is, the direction connecting both ends of the copper wire 120. Note that both ends of the copper wire 120 are placed on the copper pads 121 and 122.

  Further, an insulating resist 133 covering the back side of the substrate 131 is also opened in a rectangular shape corresponding to the shape of the copper land 132, and the copper land 132 is surrounded and formed to be concave by the thickness of the resist 133. Has been. That is, since the resist 133 is provided with a hole with the copper land 132 as the bottom, it is combined with the convex portion of the bonding wire apex, so that displacement is suppressed and connection accuracy can be improved.

  Next, when the semiconductor device 130 is gradually lowered to a position where it adheres to the adhesive sheet 140, the convex vertex of the copper wire 120 and the concave portion where the copper land 132 is the bottom come into contact with each other, and along the concave portion of the copper land 132 Thus, the copper wire 120 is deformed and the electrical connection between the upper and lower semiconductor devices is completed. Thereafter, the underfill 141 is injected into the gap between the upper and lower semiconductor devices and fixed, thereby completing a POP stacked semiconductor device.

  Similarly, FIG. 5 shows the semiconductor chip 110 mounted by the wire bonding method instead of the flip chip method. After the semiconductor chip 110 and the gold wire 123 are protected by the sealing resin 124, the copper wire 120 is shown. Is forming. Further, the sealing resin 124 is deleted, the adhesive sheet 140 is moved to the four corners where the copper wire 120 does not exist, and the upper semiconductor device 130 is temporarily fixed by the four corners adhesive sheet 140, and then the sealing resin 124 is substituted. There is no problem even if the underfill 141 is injected all at once.

  Similarly, in FIG. 6, the copper wire 120 is directly connected to the semiconductor chip 110, and the configuration is effective with respect to a loose semiconductor process design rule.

  Similarly, FIG. 7 shows a configuration in which a silicon interposer 150 for relaying the connection between the semiconductor chip 110 and the substrate 100 is used, and the wiring connecting the silicon interposer 150 to the substrate 100 is also used by the copper wire 120. Yes.

  Further, in FIG. 8, the copper wire 120 is used as one wiring in the silicon interposer 150 and is also used for connection to the upper semiconductor device 130.

  As a result, in the first embodiment, by using the copper wire 120, it is possible to easily earn the height corresponding to the thickness of the semiconductor chip 110, and the upper and lower semiconductor devices according to the wire diameter of the copper wire 120 are obtained. The pitch between the connecting terminals can be reduced at a low cost and with a short TAT. Further, the bonding wire can be used as a part of the substrate wiring, and the wiring can be easily routed.

(Second Embodiment)
In the second embodiment, the rectangular plate-shaped first semiconductor chip in the first embodiment corresponds to an increase in chip size. FIG. 9 is a cross-sectional view of the configuration of the semiconductor device according to the present embodiment as seen from the side. FIG. 10 is a plan view of the configuration of FIG. 9 as viewed from above. FIG. 11 shows a state in which a semiconductor device as a memory is stacked on the semiconductor device of FIG.

  Reference numeral 1020 denotes a copper wire for electrically connecting the upper and lower semiconductor devices, and reference numeral 1132 denotes a copper land provided on the back surface of the substrate 131 and connected to the apex of the copper wire 1020.

  Next, the semiconductor device according to the present embodiment will be described.

  In FIG. 9, as in the first embodiment, in addition to the configuration of the conventional semiconductor device, a copper wire 1020 for connecting to the upper semiconductor device is stretched. In FIG. 10, unlike the first embodiment, the direction in which the copper wire 1020 is stretched, that is, the direction connecting both ends of the copper wire 1020 is inclined with respect to each rectangular side of the first semiconductor chip 110. In FIG. 11, the copper land 1132 is also inclined according to the direction of the copper wire 1020.

  Normally, there is no problem if the copper pad 121 is moved to the outer peripheral side and the copper wire 1020 is shortened in accordance with the increase in the size of the semiconductor chip 110, but the wire collapses in connection with the upper semiconductor device. Since strength that does not occur is required, it is difficult to shorten the wire. In the second embodiment, in order to avoid this problem, the distance between the semiconductor chip 110 and the copper pad 121 can be increased without reducing the distance between the copper pad 121 and the copper pad 122. It becomes possible to effectively utilize the empty spaces at the four corners that are difficult to use in the form. Further, the distance between the semiconductor chip and the bonding wire is increased, and a larger semiconductor chip can be mounted.

(Third embodiment)
In the third embodiment, the copper wire in the first embodiment is ground and flattened to reduce the connection resistance value with the semiconductor device mounted on the upper side. FIG. 12 shows a state in which a semiconductor device as a memory is stacked on the semiconductor device according to the third embodiment.

  1260 in FIG. 12 represents the connection surface at the apex of the copper wire 120 in the first embodiment, and 1261 represents the connection surface (grinding surface) at the apex of the copper wire 120a in the third embodiment. It is a representation.

  Next, the semiconductor device according to the present embodiment will be described.

  In the third embodiment, after the copper wire 120 in the first embodiment is stretched, the vertex of the copper wire 120 is ground. At this time, since the copper wire has a structure that is weak against lateral force, the grinding is always performed from the copper pad 122 toward the copper pad 121. Further, since the grinding process is performed with the height of the top of the copper wire being held down to a certain position, it also serves as an error correction for adjusting the height to a certain position. As a result, in the third embodiment, the connection area at the apex of the copper wire 120a increases from the connection surface 1260 to the connection surface 1261, and the connection resistance with the semiconductor device mounted on the upper side can be reduced.

(Fourth embodiment)
In the fourth embodiment, the copper wire 120 in the first embodiment is once covered with a sealing resin and then ground and exposed. FIG. 13 shows a state in which a semiconductor device as a memory is stacked on the semiconductor device according to the fourth embodiment.

  In FIG. 13, 1334 represents solder pre-coated on the copper land 132 of the semiconductor device 130, 1345 is a resin layer that reinforces the copper wire 120 b, and 1361 is a connecting surface at the apex of the copper wire 120 b that is ground and exposed It represents.

  Next, the semiconductor device according to the present embodiment will be described.

  In the fourth embodiment, after the copper wire is stretched, the resin layer 1345 is formed by sealing with a resin up to a height at which the copper wire 120b is hidden (the copper wire 120b is buried with the resin). Thereafter, as in the third embodiment, the copper wire 120b is exposed by gradually grinding. Here, the radius of the copper wire is ground from the exposed point so that the area of the connection surface (grinding surface) 1361 of the copper wire 120b is increased. However, since there is a variation in the height of the vertices, some correction is necessary. At this time, since the copper wire 120b and the resin layer 1345 have the same height, the copper land 132 cannot be secured in the concave shape as in the first embodiment, and the solder 1334 is additionally formed in the convex shape. Need to be coated.

  On the contrary, since the copper wire 120b is fixed by the resin layer 1345, unlike the third embodiment, the copper wire 120b is not easily affected by the grinding direction, and all four directions are collectively and ground in one direction. There is no particular problem. Furthermore, since the copper wire 120b is not displaced even when connected to the semiconductor device 130 mounted thereon, a thinner copper wire can be used, and a narrow pitch can be realized. In addition, it is possible to suppress the deviation when connecting the upper and lower semiconductor devices and improve the accuracy.

(Fifth embodiment)
In the fifth embodiment, the copper wire in the fourth embodiment is ground until the copper wire is cut to expose the cut surface of the copper wire. FIG. 14 shows a state in which a semiconductor device as a memory is stacked on the semiconductor device according to the fifth embodiment.

  Reference numeral 1462 in FIG. 14 represents a connection surface (cut surface) at the apex of the copper wire 120c exposed by grinding.

  Next, the semiconductor device according to the present embodiment will be described.

  In the fifth embodiment, grinding is further performed from the fourth embodiment to completely cut the copper wire. The tip portion of the cut copper wire is necessary for stretching the copper wire, but is no longer necessary when the copper wire is hardened with the sealing resin 1345. Therefore, it is preferable to cut so as not to be an electrical noise source due to the open stub. Furthermore, the side to be cut and left is preferably the copper pad 121 side that is the starting point rather than the copper pad 122 side that is the end point, and the direction where the copper wire 120c stands more vertically reduces the amount of deviation when grinding, Even when the height of the top of the copper wire varies, the height can be made constant by increasing the amount of grinding.

(Sixth embodiment)
In the sixth embodiment, the sealing resin is added to a height that does not cover all of the copper wire in the copper wire in the first embodiment. FIG. 15 shows the semiconductor device in which the sealing resin 141a is injected to the vicinity of the top of the copper wire 120. FIG. 16 shows a height enough to secure a space (a gap) between the top of the copper wire 120 and the sealing resin 141a. 1 shows a semiconductor device into which a sealing resin is injected.

  Next, the semiconductor device according to the present embodiment will be described.

  In the sixth embodiment, the sealing resin 141a is additionally injected into the first embodiment, but since it is difficult to control near the top of the copper wire 120, liquid sealing with high fluidity is performed. Resin is used. Further, the sealing resin 141a is molded in a lump over the entire substrate serving as a frame on which a plurality of sealing resins are mounted, and then separated individually by dicing.

  In FIG. 15, the copper wire 120 is hardened with sealing resin to the vicinity of the top of the copper wire 120, so that the copper wire 120 is not misaligned, a copper wire with a smaller diameter can be used, and the number of grinding steps with less narrow pitch Can be realized. In FIG. 16, since a space is provided below the apex and the copper wire 120 is formed in an arc shape, vertical height correction by an elastic force such as a spring is possible. As a result, the height variation of the copper wire can be absorbed, and the connection with the semiconductor device laminated thereon is improved.

(Seventh embodiment)
In the seventh embodiment, a copper wire for inspection (second bonding wire) is added to the copper wire in the first embodiment. FIG. 17 is a cross-sectional view of the configuration of the semiconductor device according to the present embodiment as seen from the side. FIG. 18 is a plan view of the configuration of FIG. 17 as viewed from above.

  Reference numerals 1720 in FIGS. 17 and 18 denote copper wires for inspection.

  Next, the semiconductor device according to the present embodiment will be described.

  In the seventh embodiment, the inspection copper wire (second bonding wire) 1720 has a lower apex height than the other copper wires (first bonding wire) 120, and the inspection copper wire The potential of the copper land 132 of the upper semiconductor device 130 connected to the wire 1720 is set to GND. As a result, if the potential of the inspection copper wire 1720 changes to GND, it can be determined that the apex of the inspection copper wire 1720 is connected to the copper land 132 of the upper semiconductor device 130 (both are conductive). If the copper wire 120 having a height higher than that is also connected to the upper semiconductor device 130, it can be determined although it is simple. When the determination is made in this manner, an underfill is inserted between the lower first semiconductor device and the upper semiconductor device 130 to fix them.

  In addition, regarding the connection of the upper and lower semiconductor devices, if the pitch is reduced, it is necessary to reduce the diameter of the copper wire 120. In order to cope with the strength lowered by the reduction, it is necessary to adjust the height with high accuracy. come. In the seventh embodiment, the height can be adjusted by using the copper wire for inspection 1720 during the assembly process, and the upper semiconductor device 130 is gradually brought closer to the potential until the potential changes to GND. By using this method, joining at an optimal position is possible. As a result, the upper semiconductor device 130 is not pressed against the lower semiconductor device more than necessary in the assembly process, and connection failures can be suppressed.

(Eighth embodiment)
In the eighth embodiment, in the copper wire in the first embodiment, two convex arcs are created on one copper wire to create two vertices, and in accordance with the application to be used, For example, the present invention relates to a manufacturing method for selecting and mounting semiconductor devices having different memory capacities. 19 and 20 are cross-sectional views of the semiconductor device according to the present embodiment as viewed from the side, and show a completed state after the semiconductor devices to be the upper memory are stacked. FIG. 21 is an image diagram when the configurations of FIGS. 19 and 20 are compared from above.

  19 in FIG. 19 is a copper wire having two apexes, 1930 is a semiconductor device (second semiconductor device) that is a memory A to be stacked, and 2030 in FIG. 20 is a semiconductor device (second semiconductor device) that is a memory B to be stacked. , 2041 is an underfill injected after lamination, and 2120 in FIG. 21 is an optional copper wire. Memory A and memory B are different memories.

  Next, the semiconductor device according to the present embodiment will be described.

  In the eighth embodiment, the copper wire 1920 is formed with two convex vertices, and thereafter, an additional sealing resin is formed to reinforce the wire collapse. Here, the heights of the two vertices formed by the copper wire 1920 do not need to be the same, and the sealing resin that reinforces the wire collapse is also necessarily required when the diameter of the copper wire 1920 is large. is not.

  Thereafter, the process proceeds to a step of selecting and mounting a semiconductor device having a different memory capacity in accordance with the specification application. In the semiconductor device shown in FIG. 19, an adhesive sheet suitable for the semiconductor device 1930 stacked on the upper side is attached, the semiconductor device 1930 is mounted, and an underfill is injected into the gap between the upper and lower semiconductor devices. Become.

  In the semiconductor device shown in FIG. 20, similarly, when mounting the semiconductor device 2030, an adhesive sheet suitable for the semiconductor device 2030 is attached, the semiconductor device 2030 is mounted, and an underfill is formed in the gap between the upper and lower semiconductor devices. inject. However, since the size of the semiconductor device 2030 is small and the copper wire 1920 is exposed, the underfill 2041 needs to be controlled so that the copper wire 1920 is hidden.

  FIG. 21 shows an image in which FIGS. 19 and 20 are compared. The semiconductor device 1930 has a larger number of terminals than the semiconductor device 2030. The copper wire 2120 shows the difference, and is used only when the semiconductor device 1930 is used. In the semiconductor device 2030, the copper land 132 connected to the copper wire 2120 does not exist. Further, since the formation of the copper wire 1920 is likely to vary, it is better to coat the copper lands 132 of the upper semiconductor devices 1930 and 2030 with the solder 1334 and add a reflow process. As described above, in the eighth embodiment, it is possible to divide and stack the minimum necessary memory according to the specification application, and it is also possible to stack semiconductor devices with different specifications according to the function. It becomes possible.

(Ninth embodiment)
In the ninth embodiment, the copper wire in the first embodiment passes through the upper surface of the semiconductor chip and is connected to the upper semiconductor device on the upper surface of the semiconductor chip. FIG. 22 is a cross-sectional view of the semiconductor device according to the present embodiment as viewed from the side, and shows a completed state after the semiconductor device to be the upper memory is stacked.

  2220 in FIG. 22 indicates a copper wire (third bonding wire) passing above the upper surface of the semiconductor chip.

  Next, the semiconductor device according to the present embodiment will be described.

  In the ninth embodiment, the copper wire 2220 passes above the upper surface of the semiconductor chip, and two apexes connected to the upper semiconductor device are formed on the upper surface of the semiconductor chip, so as to reinforce the wire collapse. The sealing resin is additionally molded.

  The closer the power supplied to the semiconductor device (second semiconductor device) mounted on the upper side is to the semiconductor chip, the lower the impedance and the better. Furthermore, by bringing the power supply terminals supplied from the outside of the conventional semiconductor device to the inside, it is possible to add signal terminals to the outside terminals corresponding to the moved power supply terminals. Thus, in the ninth embodiment, it is possible to strengthen the power supply of the upper semiconductor device and switch the power supply terminal on the outside to the signal terminal.

(Tenth embodiment)
In the tenth embodiment, in the adhesive sheet in the first embodiment, there is no expansion / contraction with the elastic adhesive sheet having elasticity in order to absorb the difference in warpage between the upper and lower semiconductor devices and reduce the residual stress. A combination of adhesive sheets is used. That is, in this embodiment, two types of adhesive members of different types are used as the adhesive member. FIG. 23 shows a state in which a semiconductor device as a memory is stacked on the semiconductor device according to this embodiment. FIG. 24 is a simplified view of the state where the adhesive sheet is attached as seen from above. FIG. 25 is a sectional view of the completed state after the upper and lower semiconductor devices are connected as viewed from the side through FIG.

  In FIG. 23, reference numeral 2320 denotes a copper wire drawn and stretched from one direction, and reference numeral 2340 denotes a stretchable elastic adhesive sheet.

  Next, the semiconductor device according to the present embodiment will be described.

  In the tenth embodiment, the vertices of the copper wires 2320 are stretched so as to be concentrated on the left side. Further, an adhesive sheet 140 having low stretchability is stretched at a portion connecting the upper and lower semiconductor devices, and an elastic adhesive sheet 2340 having stretchability is stretched at a portion not connected. Further, as shown in FIG. 24, there is no problem even if the adhesive sheet 140 is divided. Thereafter, as shown in FIG. 25, the underfill 141 is injected only into the portion connecting the upper and lower semiconductor devices.

  As described above, in the tenth embodiment, the connection between the upper and lower semiconductor devices is consolidated in one place and completely fixed, and the portion without connection is made operable by the elastic elastic adhesive sheet 2340. Thus, the difference in warpage between the upper and lower semiconductor devices can be absorbed, the residual stress can be reduced, and a good connection can be maintained.

(Eleventh embodiment)
In the eleventh embodiment, in the copper wire in the first embodiment, the height of the copper wire apex is changed in accordance with the additionally mounted components. FIG. 26 is a cross-sectional view of the semiconductor device according to the present embodiment as viewed from the side, and shows a completed state after stacking the semiconductor devices with components added on the back surface. Similarly, FIG. 27 is a cross-sectional view of the semiconductor device according to the present embodiment as seen from the side, and shows a state where a heat sink is added.

  2670 in FIG. 26 is a bypass capacitor, 2671 is a semiconductor chip on which an analog circuit is mounted, and 2780 in FIG. 27 is a heat sink.

  Next, the semiconductor device according to the present embodiment will be described.

  In the eleventh embodiment, the height of the apex of the copper wire 120d is freely changed and optimized in accordance with the conditions of the semiconductor device (second semiconductor device) mounted on the upper side. Is set higher by the height of the added capacitor 2670 and semiconductor chip 2671. That is, the height of the copper wire 120d is selected from a plurality of preset heights according to specifications. In addition, since the copper wire becomes higher, the wire is more likely to fall down, so a process of hardening with a sealing resin is also added. Also, in FIG. 27, a heat sink 2780 is added to increase the heat dissipation of the semiconductor device for applications where the operating temperature is high, and a heat sink 2780 cut out only in the copper wire region is inserted. As described above, in the eleventh embodiment, it is possible to add components and a heat sink by changing the height of the copper wire, and it is possible to provide a semiconductor device corresponding to different applications.

(Twelfth embodiment)
In the twelfth embodiment, in the copper wire in the first embodiment, the copper pad 121 serving as the start point and the copper pad 122 serving as the end point are matched with the semiconductor device (second semiconductor device) stacked on the upper side. The combination is changed. That is, the positions of both ends of the copper wire in the first semiconductor device are appropriately selected from a plurality of preset positions (corresponding to the positions of the copper pads) according to the type of the second semiconductor device. FIG. 28 is an image diagram showing a combination of start and end points of a copper pad that is the first pattern of the semiconductor device according to the present embodiment. FIG. 29 is an image diagram showing a combination of start and end points of a copper pad which is the second pattern of the semiconductor device according to the present embodiment.

  2821 in FIG. 28 is a copper pad that is the start point of the first pattern, 2822 is a copper pad that is the end point of the first pattern, 2830 is the upper semiconductor device that is the first pattern, and 2921 in FIG. 29 is the start point of the second pattern. A copper pad 2922, a copper pad serving as the end point of the second pattern, and 2930, an upper semiconductor device serving as the second pattern.

  Next, the semiconductor device according to the present embodiment will be described.

  In the twelfth embodiment, as the first pattern, a copper wire is stretched from the copper pad 2821 to the copper pad 2822 and connected to the semiconductor device 2830. Next, as a second pattern, a copper wire is stretched from the copper pad 2921 to the copper pad 2922 and connected to the semiconductor device 2930. Thus, by changing the combination of the copper pad as the starting point and the copper pad as the ending point, different semiconductor devices can be mounted, and the range of choices according to the usage can be increased.

(Thirteenth embodiment)
In the thirteenth embodiment, in the copper wire in the first embodiment, the copper pad 122 serving as the end point is provided on the adjacent semiconductor device, and is separated by cutting in the package dicing process. It is a thing of composition. FIG. 30 is a simplified diagram showing a state where a plurality of substrates of the semiconductor device according to the present embodiment are mounted in a frame. FIG. 31 is a cross-sectional view of the configuration of the semiconductor device according to the present embodiment viewed from the side. FIG. 32 is a plan image view of the configuration of FIG. 31 viewed from above. 33 is a cross-sectional view of the completed state when the upper semiconductor device is mounted on the semiconductor device according to the present embodiment as viewed from the side. 305 in FIG. 30 is a substrate frame (first substrate assembly in which the first substrates are connected) on which individual semiconductor devices are mounted together, and 3090 is a dicing for individually separating after the semiconductor devices are formed in the frame. The blade, 3091 is a line cut by the dicing blade 3090, 3092 is a region shown in FIGS. 31 and 32, and 3093 is a sealing resin that is collectively sealed as a frame.

  Next, the semiconductor device according to the present embodiment will be described.

  In the thirteenth embodiment, a plurality of semiconductor devices (first semiconductor devices) are mounted together on a frame-structured substrate, and as shown in FIG. 5 of 25 semiconductor devices and 25 semiconductor devices in the same way as the right block, a total of 50 semiconductor devices are mounted. In the embodiment, the left block and the right block are divided in order to reduce the warp in the frame, but it is not particularly necessary for the present invention to be divided. In addition, the substrate of the semiconductor device in the frame is not necessarily a non-defective product.

  Next, a semiconductor chip is mounted on the substrate of 50 semiconductor devices in the frame, and then a copper wire 120 connected to the semiconductor devices to be stacked is stretched. At this time, as shown in FIG. 31, the copper pad 122 serving as the end point of the copper wire 120 is disposed in the adjacent semiconductor device, and the copper wire 120 is stretched toward the adjacent semiconductor device. Become. Further, in the semiconductor device on the end side where there is no adjacent semiconductor device, a copper wire 120 is stretched in a region that becomes an outer frame of the frame. Thereafter, as in the case of the sealing resin 3093 shown in FIG. 30, the left block and the right block are divided into 25 blocks at a time. Next, the wafer is cut into individual semiconductor devices by a dicing blade 3090 according to a cutting line 3091. At this time, the copper wire 120 is also cut. The semiconductor device, which is separated individually, is then connected to the upper semiconductor device (second semiconductor device) by solder 1334, adhesive sheet 140, and underfill 141, as shown in FIG.

  As a result, in the embodiment, since the copper pad 122 serving as the end point of the copper wire is disposed in the adjacent semiconductor device, the distance between the copper pad 122 and the semiconductor chip 110 can be increased, and the larger semiconductor chip 110 is mounted. It becomes possible. In addition, it is possible to reduce open stub noise caused by the copper wire to be cut including the copper pad 122.

(Fourteenth embodiment)
In the fourteenth embodiment, in the sealing resin in the fourth embodiment, the sealing resin area to be ground flat is reduced in advance, and the grinding time and dust discharged by grinding are reduced. is there. That is, in the embodiment in which the thickness of the sealing resin for sealing the other region is smaller than the thickness of the sealing resin for sealing the region where the copper wire exists (height from the upper surface of the first substrate). is there. FIG. 34 is a cross-sectional view of the configuration of the semiconductor device according to the present embodiment viewed from the side.

  Reference numeral 3575 in FIG. 34 simply represents a convex mold used when forming the sealing resin.

  Next, the semiconductor device according to the present embodiment will be described.

  In the fourteenth embodiment, after mounting a semiconductor chip, a copper wire connected to a semiconductor device stacked on the upper side is stretched. Thereafter, when the sealing resin 1345 is injected, in the portion (region) where the copper wire is not stretched, the convex mold 3575 is used so that the sealing resin 1345 becomes concave. Mold. Thereafter, the semiconductor device is completed by grinding so that the copper wire is exposed. At this time, since it is desirable that the height of the concave bottom is lower than the height at which the copper wire is exposed, the semiconductor chip is preferably mounted on the flip chip. As a result, only the region where the copper wire exists is ground, so that the grinding time and dust discharged by grinding can be reduced, and the work efficiency can be improved.

(Fifteenth embodiment)
In the fifteenth embodiment, the copper wire in the first embodiment is deformed into an intentional shape when connected to the upper semiconductor device, thereby confirming the connection. FIG. 35 is a cross-sectional view of the semiconductor device according to the present embodiment as viewed from the side, and shows a state of stacking. FIG. 36 is an image view of the lower semiconductor device as viewed from above when the upper semiconductor device is stacked.

  3532 in FIG. 35 is a copper land on the lower surface of the semiconductor device stacked on the upper side, 3720 in FIG. 35 is a copper wire when normally connected to the upper semiconductor device, and 3725 is normally connected to the upper semiconductor device. The copper wire is not shown.

  Next, the semiconductor device according to the present embodiment will be described.

  In FIG. 35, as in the first embodiment, a copper wire 120 for connecting to the upper semiconductor device is stretched. The shape of the copper land 3632 is concave as in the first embodiment, and is set so that the copper wire 120 is deformed according to the concave shape. However, in the embodiment, unlike the first embodiment, the extending direction of the long side of the copper land 3632 is in a direction different from the direction in which both ends of the copper wire 120 are connected. Yes. As a result, when it is connected to the upper semiconductor device, it is deformed to the intended shape as shown by the copper wire 3720 in FIG. The copper wire 3725 in FIG. 36 is not connected to the upper semiconductor device due to factors such as a difference in height from other copper wires. Can be determined.

  As a result, even without using a large-scale inspection device such as a tester, multiple defective samples on the tray can be analyzed in a short time with the X-ray analyzer, greatly reducing the number of failure analysis steps. Is possible.

  As described above, the semiconductor device of the present invention can realize a narrow pitch of connection terminals between stacked upper and lower semiconductor devices at a low cost and with a short TAT, thereby reducing the cost of the semiconductor device and shortening the TAT. By realizing recombination of the upper and lower semiconductor devices according to the application, it is useful in the field of electronic equipment such as a mobile phone or a digital still camera having problems such as high cost, a long development period, and an increase in man-hours for various developments.

100 substrate (first substrate)
131 Substrate (second substrate)
110 First semiconductor chip 111 Gold bump 112, 141, 2041 Underfill 120 Copper wire (first bonding wire)
120a, 120b, 120c, 120d, 1020 copper wire (bonding wire)
121, 122, 2821, 2822, 2921, 2922 Copper pad 123 Gold wire 124, 1345, 3093 Sealing resin 130, 1930, 2030, 2830, 2930 Semiconductor device 132, 1132, 3632 Copper land (connection terminal)
133 Resist 140, 2340 Adhesive sheet (adhesive member)
141a Sealing resin 150 Silicon interposer 1720 Copper wire (second bonding wire)
1920, 2120, 2320, 3720, 3725 Copper wire 1260 Connection surface (vertex)
1261, 1361 Connection surface (grinding surface)
1462 Connection surface (cut surface)
1334 Solder 2220 Copper wire (third bonding wire)
2670 Bypass capacitor 2780 Heat sink 3005 Frame substrate (first substrate assembly)
3090 Dicing blade 3091 Dicing line 3092 Enlarged range area 3575 Sealing mold

Claims (20)

On a first semiconductor device comprising a first substrate and a first semiconductor chip mounted on the first substrate, a second substrate and a second semiconductor chip mounted on the upper surface of the second substrate are provided. A semiconductor device having a second semiconductor device mounted thereon,
The lower surface of the second substrate facing the first semiconductor chip is provided with a plurality of connection terminals electrically connected to the second semiconductor chip,
The first semiconductor device includes a plurality of bonding wires having a convex arc on the upper side of the first substrate,
The bonding wire is electrically connected to the connection terminal at the top of an upwardly convex arc;
At least one of the bonding wires is electrically connected directly or indirectly to the first semiconductor chip.   2. The semiconductor device according to claim 1, wherein an interposer exists between the first substrate and the first semiconductor chip, and at least one end of the bonding wire exists on the interposer. The semiconductor device according to claim 1 or 2,
In the lower surface of the second substrate, the connection terminal is rectangular,
The long side of the rectangle extends in a direction connecting both ends of the bonding wire connected to the connection terminal. The semiconductor device according to claim 1 or 2,
In the lower surface of the second substrate, the connection terminal is rectangular,
The long side of the rectangle has an inclination with respect to a direction connecting both ends of the bonding wire connected to the connection terminal. The semiconductor device according to any one of claims 1 to 4,
Further comprising an insulator layer laminated on the lower surface of the second substrate;
2. A semiconductor device according to claim 1, wherein a hole having the connection terminal as a bottom is formed in the insulator layer. The semiconductor device according to any one of claims 1 to 5,
The first semiconductor chip has a rectangular plate shape,
The semiconductor device according to claim 1, wherein a direction connecting both ends of the bonding wire is inclined with respect to a rectangular side of the first semiconductor chip. The semiconductor device according to claim 1,
The bonding wire has a ground surface with the apex ground;
The semiconductor device, wherein the grinding surface and the connection terminal are electrically connected. The semiconductor device according to any one of claims 1 to 7,
The bonding wire includes a first bonding wire and a second bonding wire,
The semiconductor device according to claim 1, wherein the first bonding wire has a greater distance from the first substrate to the apex than the second bonding wire. The semiconductor device according to claim 1,
At least one of the bonding wires includes two or more apexes of an upwardly convex arc. The semiconductor device according to any one of claims 1 to 9,
The semiconductor device according to claim 1, wherein the bonding wire includes a third bonding wire that passes above the upper surface of the first semiconductor chip. The semiconductor device according to claim 1,
The semiconductor device, wherein the first semiconductor device and the second semiconductor device are bonded by at least two different bonding members. On a first semiconductor device comprising a first substrate and a first semiconductor chip mounted on the first substrate, a second substrate and a second semiconductor chip mounted on the upper surface of the second substrate are provided. A method of manufacturing a semiconductor device on which a second semiconductor device is mounted,
A step S of mounting the first semiconductor chip on the first substrate;
Providing a plurality of bonding wires having a convex arc on the upper side of the first substrate; and
Mounting the lower surface of the second substrate of the second semiconductor device on the first semiconductor device; and
A plurality of connection terminals are provided on the lower surface of the second substrate,
A method of manufacturing a semiconductor device, wherein in step B, the connection terminal and the apex of a convex arc on the bonding wire are electrically connected. The method for manufacturing a semiconductor device according to claim 12,
After Step A and before Step B, Step C for forming a resin layer for burying the bonding wire on the first substrate, and grinding the resin layer to expose the bonding wire A method for manufacturing a semiconductor device, further comprising a step D. The method for manufacturing a semiconductor device according to claim 13,
In the step C, the method of manufacturing a semiconductor device, wherein the region where the bonding wire exists has a greater distance from the upper surface of the first substrate to the surface of the resin layer than the other region. The method for manufacturing a semiconductor device according to claim 12,
After the step A and before the step B, the method further includes a step E of forming a resin layer on the first substrate so as to expose the apex of the convex arc on the bonding wire. A method of manufacturing a semiconductor device. The method for manufacturing the semiconductor device according to claim 15,
In the step E, a method of manufacturing a semiconductor device, wherein a gap is formed between the bonding wire and the resin layer immediately below the apex. The method for manufacturing a semiconductor device according to claim 12,
The bonding wire includes a first bonding wire and a second bonding wire, and the first bonding wire has a greater distance from the first substrate to the apex than the second bonding wire,
In the step B, the first semiconductor device and the second semiconductor device are brought close to each other until the second semiconductor device and the second bonding wire are electrically connected, and then the first semiconductor device and the second semiconductor device A method of manufacturing a semiconductor device, wherein a semiconductor device is fixed. The method for manufacturing a semiconductor device according to any one of claims 12 to 17,
In the step A, a method of manufacturing a semiconductor device, wherein at least one position of both ends of the bonding wire is selected from three or more terminals in the first semiconductor device according to the type of the second semiconductor device. The method for manufacturing a semiconductor device according to claim 12,
In the step S, a plurality of the first semiconductor chips are mounted on a first substrate assembly in which a plurality of the first substrates are connected,
After the step A and before the step B, the step of sealing the first semiconductor chip on the first substrate assembly with a sealing resin, and the first step including the sealing resin Cutting one substrate assembly into the individual first substrates, and
In the step T, a semiconductor device is manufactured by cutting at least a part of the bonding wires. On a first semiconductor device comprising a first substrate and a first semiconductor chip mounted on the first substrate, a second substrate and a second semiconductor chip mounted on the upper surface of the second substrate are provided. A method of manufacturing a semiconductor device on which a second semiconductor device is mounted,
Mounting the first semiconductor chip on the first substrate;
Forming a plurality of bonding wires having a convex arc on the upper side of the first substrate;
Forming a resin layer in which the bonding wire is buried on the first substrate; and
Step X of grinding the resin layer to cut the apex portion of the arc of the bonding wire to expose the cut surface;
Mounting the lower surface of the second substrate of the second semiconductor device on the first semiconductor device; and
A plurality of connection terminals are provided on the lower surface of the second substrate,
A method of manufacturing a semiconductor device, wherein the connection terminal and the cut surface of the bonding wire are electrically connected in the step B.

Images