JP2011249398A - Circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit device which includes a thin substrate mounting a circuit element with multiple connection pads as well as secures a rigidness of the entire device.SOLUTION: The circuit device 10 mainly includes a substrate 12, a circuit element such as an element for signal processing 16 mounted on a top surface of the circuit substrate 12, and a case material 14 arranged on the top surface of the substrate 12 so as to enclose the circuit element. In addition, a part of an external connection bump 32 provided on an undersurface of the substrate 12 is arranged on a position overlapped with a side surface 14B of the case material 14.

Description

  The present invention relates to a circuit device in which a plurality of circuit elements are mounted on an upper surface of a substrate.

  As one measure for modularizing a plurality of circuit elements, there is a structure in which a plurality of circuit elements are mounted on the upper surface of a substrate and the circuit elements are connected via a conductive pattern formed on the substrate (Patent Document). 1).

  A circuit device 100 shown in FIG. 6 includes a substrate 112, a semiconductor device 102 mounted on the upper surface of the substrate 112, and a chip-type element 104. The semiconductor device 102 and the chip-type element 104 are electrically connected via a wiring layer formed on the substrate 112. Here, the semiconductor device 102 is a lead frame type package, and leads protruding from both side surfaces are used as connection means.

  Further, the substrate 112 having a thickness of, for example, 1.0 mm or more is employed in order to have rigidity enough to prevent deformation even when circuit elements such as the semiconductor device 102 are mounted. Further, in order to incorporate a predetermined electric circuit into the circuit device 100, the circuit board 112 is provided with a plurality of wiring layers.

JP 2008-167052 A

  However, the above-described structure has a problem that it is difficult to mount a semiconductor element having a large number of connection pins.

  Specifically, for example, when connecting a semiconductor element having several hundred pads in a flip-chip state, it is necessary to form connection pads formed at the same pitch as the pads on the upper surface of the substrate 112. Furthermore, it is necessary to form a via hole that connects the connection pad to the lower wiring layer. Here, the area occupied by the via hole is proportional to the thickness of the substrate 112. Therefore, in order to form a large number of via holes in a limited area, the thickness of the substrate 112 needs to be about 0.4 mm or less, for example.

  However, when the substrate 112 is thinned in this way, the mechanical strength of the substrate 112 is not sufficient, and it is difficult to support the circuit element such as the semiconductor element 102 mounted on the upper surface with the substrate 112. Furthermore, when a bump electrode is provided on the lower surface of the substrate 112 as an external connection terminal, there is a problem that it is difficult to connect the bump electrode if the flatness of the substrate 112 is impaired.

  The present invention has been made in view of the above-described problems, and a main object of the present invention is to provide a thin substrate on which circuit elements having a large number of pads are mounted and to ensure the rigidity of the entire apparatus. Another object of the present invention is to provide a circuit device.

  The circuit device of the present invention includes a substrate having a first main surface and a second main surface, a circuit element disposed on the first main surface of the substrate, a bottom surface portion, and a side surface portion, A case material attached to the first main surface of the substrate so as to surround the circuit element; and a connection bump disposed on the second main surface of the substrate, wherein at least a part of the connection bump is The case material is disposed at a position overlapping the side surface portion of the case material.

  According to the circuit device of the present invention, the case material having the bottom surface portion and the side surface portion is attached to the upper surface of the substrate, and the connection bump is provided on the lower surface of the substrate at a position overlapping the side surface portion of the case material. By doing so, the substrate in the region where the connection bumps are arranged is reinforced by the side surface portion of the case material, so that it is possible to mount the circuit device via the connection bumps while keeping the substrate flat. Become.

It is a perspective view which shows the circuit apparatus of this invention. It is a figure which shows the circuit apparatus of this invention, (A) is sectional drawing, (B) is a top view which shows a lower surface, (C) is sectional drawing which shows the part in which an external connection bump is provided. It is a figure which shows the circuit apparatus of this invention, (A) is sectional drawing which shows the location in which the signal processing element was mounted partially, (B) is a top view of this location. It is a figure which shows the circuit apparatus of this invention, (A)-(D) is sectional drawing which shows the circuit apparatus of another form. It is a figure which shows the circuit apparatus of this invention, (A) is a top view which shows the state to which each element is connected, (B) is a top view which shows the comparative example. It is sectional drawing which shows the circuit apparatus of background art.

  With reference to FIG. 1, the overall configuration of the circuit device 10 of the present embodiment will be described.

  The circuit device 10 mainly includes a substrate 12, a circuit element such as a signal processing element 16 mounted on the upper surface of the circuit substrate 12, and a case material 14 disposed on the upper surface of the substrate 12 so as to surround the circuit element. In preparation. Here, the case material 14 is shown in a state of being separated from the upper surface of the substrate 12, but the case material 14 is actually fixed to the peripheral surface portion of the upper surface of the substrate 12.

  The substrate 12 is an insulating substrate having a resin as a base material, and has a plurality of wiring layers. As a material of the base material constituting the substrate 12, a thermosetting resin such as an epoxy resin or a thermoplastic resin such as a polyethylene resin can be employed. The thickness of the substrate 12 is, for example, 400 μm or less.

  Furthermore, when a resin material filled with fibrous or particulate filler is adopted as the base material of the substrate 12, the mechanical strength of the substrate 12 is improved. Silicon oxide or silicon nitride can be used as the filler material. Furthermore, the thermal expansion coefficient of the base material of the substrate 12 approaches the thermal expansion coefficient of the wiring layer provided on the substrate 12, and the warpage of the entire substrate 12 when a temperature change is suppressed is suppressed.

  On the upper surface of the substrate 12, a signal processing element 16, memories 18 and 20, a signal processing element 22, a chip-type element 24 and an oscillator 26 are provided. Here, these elements are surface-mounted by a reflow process of melting solder, but may be connected to the wiring layer of the substrate 12 through a thin metal wire. These circuit elements are connected to each other via a wiring layer provided on the substrate 12. Further, the external connection bumps formed on the lower surface of the substrate 12 are also connected via the wiring layer.

  The signal processing element 16 is an LSI that processes an audio signal and an image signal, and is flip-chip mounted on the substrate 12 in a bare semiconductor element state. Dozens to hundreds of pads are arranged on the peripheral surface portion of the lower surface of the signal processing element 16, and are connected to the connection pads arranged on the upper surface of the substrate 12 via bump electrodes made of solder or gold. It is connected.

  Here, the signal processing element 16 is not necessarily mounted in a bare state. For example, a state of WLP (Wafer Level Package) in which bump electrodes are rearranged in a wiring layer provided on the lower surface of the semiconductor substrate. May be implemented.

  The memories 18 and 20 are disposed on the upper surface of the substrate 12 at a position sandwiching the signal processing element 16. The memories 18 and 20 are, for example, DDR-SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), and have a function of storing data before being processed by the signal processing element 16 or data after being processed.

  The memories 18 and 20 are in a package state in which a semiconductor chip is sealed with a resin, and a plurality of pads provided on the lower surface are connected to a wiring layer of the substrate 12 via a conductive adhesive such as solder. .

  The signal processing element 22 is an LSI that converts data in order to input / output data to / from the outside of the apparatus, and the wiring provided on the upper surface of the substrate 12 with pads provided on the lower surface via connection bumps. Connected with. Here, the signal processing element 22 may be flip-chip mounted in a bare state or may be mounted in a WLP state.

  The oscillator 26 oscillates a clock having a predetermined frequency, and this clock is used as a system clock by the signal processing elements 16 and 22.

  The chip-type element 24 is, for example, a chip capacitor or a chip-type resistor, and two electrodes arranged at both ends are connected to the wiring layer of the substrate 12 via solder.

  The case material 14 is formed by forming a metal having a thickness of about 0.2 mm to 0.5 mm into a lid shape. As the material, for example, white is used. Here, Western white is an alloy mainly composed of copper, zinc and nickel.

  Further, the case material 14 includes a bottom surface portion 14A and a side surface portion 14B. The lower end of the side surface portion 14B is fixed to the upper surface of the substrate 12 so as to seal circuit elements such as the signal processing element 16 disposed on the upper surface of the substrate 12. A dummy wiring layer for connection is provided on the periphery of the surface of the substrate 12, and the lower end of the side surface part 14B is fixed to the wiring layer via solder.

  Furthermore, an opening 28 is provided by partially removing and opening the side surface 14B of the case material 14. By doing in this way, it will be in the state which the interior space covered with the case material 14 and the board | substrate 12 and the exterior were connected. Accordingly, since the signal processing element 16 generates heat under use conditions, even if the air inside the case material 14 is heated, the heated air is released to the outside via the opening 28. Overheating inside the case material 14 is suppressed.

  Further, in this embodiment, the thin substrate 12 is reinforced by the case material 14, which will be described later with reference to FIG.

  The configuration of the circuit device 10 will be further described with reference to FIG. 2A is a cross-sectional view of the portion of the circuit device 10 where the signal processing element 16 is disposed, and FIG. 2B is a view of the circuit device 10 as viewed from below, and FIG. FIG. 2 is a sectional view partially showing the circuit device 10.

  Referring to FIGS. 2A and 2B, first, as described above, the signal processing element 16 and the memories 18 and 20 are mounted on the upper surface of the substrate 12, and these elements are covered. Thus, most of the upper surface of the substrate 12 is covered with the case material 14. The signal processing element 16 and the memories 18 and 20 are surface-mounted via connection bumps 30 made of solder.

  A plurality of external connection bumps 32 in which solder is molded into a ball shape are welded to the lower surface of the substrate 12. These external connection bumps 32 are electrically connected to circuit elements such as the signal processing element 16 via a wiring layer formed on the substrate 12.

  Referring to FIG. 2B, external connection bumps 32 are arranged in a rectangular ring shape along the outer peripheral side of substrate 12 near the peripheral surface portion of substrate 12. Here, the external connection bumps 32 are triple arranged in a rectangular ring shape, but may be arranged four or more in a rectangular ring shape. The external connection bumps 32 arranged in a rectangular ring shape are used as connection electrodes through which electrical signals pass.

  A plurality of external connection bumps 32 are arranged in a matrix near the center of the substrate 12. The external connection bumps 32 arranged in this region do not pass electrical signals. The external connection bump 32 in this region functions as a path through which heat generated by the operation of the signal processing element 16 is conducted. Furthermore, by disposing a plurality of external connection bumps 32 in the central part, there is also an effect that the thermal stress acting on the external connection bumps 32 disposed in the peripheral part is alleviated. Here, these external connection bumps 32 may be used as terminals through which electrical signals pass.

  In this embodiment, the mechanical strength of the thin substrate 12 is supplemented by the case material 14, thereby obtaining an effect that the external connection bumps 32 can be stably connected.

  Specifically, when the circuit device 10 is mounted on a mounting substrate such as a mother board, the substrate 12 is placed on the upper surface of the mounting substrate and heated to a predetermined temperature to melt the external connection bumps 32. That is, the circuit device 10 is surface-mounted on the mounting substrate by a reflow process.

  The flatness of the substrate 12 is important when performing surface mounting by the reflow process. If the substrate 12 is mounted in a flat state, all the external connection bumps 32 are connected to predetermined positions. On the other hand, when the substrate 12 is bent, some external connection bumps 32 may be separated from the mounting substrate. In particular, the substrate 12 of the present embodiment is a thin substrate having a thickness of about 400 μm and has low rigidity, so that there is a high risk of bending.

  For this reason, in this embodiment, the case material 14 is fixed to the upper surface of the substrate 12. Specifically, the end portion of the side surface portion 14 </ b> B of the case material 14 is fixed near the outer peripheral end portion of the substrate 12. By doing in this way, since the board | substrate 12 is reinforced with the case material 14 entirely, the curvature of the board | substrate 12 in the middle stage of a manufacturing process or under use condition is suppressed.

  Furthermore, in this embodiment, referring to FIG. 2C, at least a part of the external connection bump 32 is disposed at a position overlapping the side surface portion 14B of the case material 14. Here, the external connection bumps 32 </ b> A arranged on the outermost side are arranged at positions that overlap with the side surface parts 14 </ b> B of the case material 14. By doing so, the flatness of the portion of the substrate 12 where the external connection bumps 32A are disposed is ensured. Therefore, when the circuit device 10 is surface-mounted on the mounting board by the reflow process, the external connection bumps 32A are stably welded to the mounting board side.

  A relatively large thermal stress acts on the external connection bumps 32A arranged on the outermost periphery after mounting, but the shape of the external connection bumps 32A after connection is an ideal column by performing reflow stably in this way. Thus, the external connection bump 32A is prevented from being broken due to thermal stress.

  Referring to FIG. 2B, the external connection bumps 32 arranged in a rectangular ring shape on the outermost periphery are arranged at positions where they overlap with the side surface part 14 </ b> B of the case material 14. By doing in this way, it becomes possible to connect stably the external connection bump 32 arrange | positioned at the outermost periphery at the rectangular ring shape in the reflow process.

  With reference to FIG. 3, the configuration of the wiring layer provided on the substrate 12 of the circuit device 10 will be described. FIG. 3A is a cross-sectional view partially showing a part where the signal processing element 16 is mounted, and FIG. 3B is a view of this part as seen from above.

  Referring to FIG. 3A, the signal processing element 16 is flip-chip mounted on the upper surface of the substrate 12 in a bare chip state where the semiconductor substrate is exposed. Specifically, the pad 48 provided on the lower surface of the signal processing element 16 is connected to the wiring pad 52 provided on the upper surface of the substrate 12 through the connection bump 50. The connection bump 50 is made of a conductive adhesive material such as solder.

  A plurality of wiring layers 56, 58, 60, 62 and 63 are stacked on the substrate 12 in order to realize a predetermined circuit. Furthermore, the wiring layers are insulated by an insulating layer made of a resin such as glass epoxy. The wiring layers are electrically connected to each other through a via hole 64 that penetrates the insulating layer at a predetermined location. Further, a part of the lowermost wiring layer 63 constitutes a wiring pad 54. The external connection bumps 32 made of solder balls are disposed on the lower surface of the wiring pad 54.

  Since the signal processing element 16 incorporates a complicated electric circuit for processing an image signal and a video signal, several hundred pads 48 are arranged. Therefore, the pitch L1 of the pads 48 is very short, for example, about 60 μm or more and 70 μm or less. Here, the pitch is a distance at which the centers of adjacent pads 48 are separated from each other. Further, the pitch of the wiring pads 52 arranged on the upper surface of the substrate 12 is the same as the pitch of the pads 48 provided in the signal processing element 16.

  Referring to FIG. 3B, a via hole 64 for connecting the wiring layer connected to the pad 48 of the signal processing element to the lower wiring layer is provided in the peripheral portion of the signal processing element 16. Yes. Specifically, here, pads 48 are arranged in a staggered pattern around the signal processing element 16. A wiring portion 68 connected to each pad 48 is drawn from the signal processing element 16 to the periphery, and a land 66 is provided at an end thereof. Further, a via hole 64 is provided in the land 66.

  As described above, since the signal processing element 16 has several hundred pads 48, in order to provide the via holes 64 corresponding to the pads 48 around the signal processing elements 16, each via hole is provided. The area of 64 and land 66 needs to be reduced. As an example, the diameter of the via hole 64 is 80 μm or less, and the diameter of the land 66 is 150 μm or less.

  The via hole 64 is formed by partially removing the insulating layer between each wiring layer to provide a through hole and embedding a conductive material such as metal in the through hole by plating. A thin through hole having a diameter of about 80 μm is formed by laser processing. However, since it is difficult to form a through-hole with respect to a thick substrate by laser processing, the substrate 12 used in this embodiment has a thickness of about 400 μm.

  As described above, since the substrate 12 on which the signal processing elements 16 having the pads 48 arranged at a narrow pitch are placed is extremely thin, the flatness of the substrate 12 on which the circuit elements are mounted is ensured. It becomes difficult. In this embodiment, as shown in FIG. 1 and the like, the flatness of the substrate 12 is ensured by fixing the case material 14 formed from a metal plate to the upper surface of the substrate 12.

  With reference to FIG. 4, the shape and the like of the case material 14 employed in the substrate 12 will be described. FIGS. 4A and 4D are structures for radiating heat generated from the signal processing element 16. FIG.

  Referring to FIG. 4A, here, a heat conductive sheet 34 is disposed between the upper surface of the signal processing element 16 and the inner surface of the bottom surface portion 14A of the case material 14. The heat conductive sheet 34 is a sheet made of a resin material mixed with a filler and having excellent heat conductivity. The lower surface is in contact with the signal processing element 16, and the upper surface is in contact with the bottom surface portion 14 </ b> A of the case material 14. . By doing so, the signal processing element 16 and the case material 14 are thermally coupled, and the heat generated by the operation of the signal processing element 16 passes through the heat conductive sheet 34 and the case material 14. Is released to the outside well.

  On the other hand, the memories 18 and 20 that generate less heat during operation than the signal processing element 16 are separated from the case material 14. By doing so, it is possible to suppress the heat generated from the signal processing element 16 from being conducted to the memories 18 and 20 via the case material 14.

  In FIG. 4B, a concave portion 36 is formed by recessing the bottom surface portion 14A of the case material 14 where the signal processing element 16 is mounted. By doing so, the lower surface of the concave portion 36 is in direct contact with the upper surface of the signal processing element 16. Therefore, the heat generated from the signal processing element 16 is released to the outside through the case material 14 satisfactorily. Also in this case, the memories 18 and 20 are separated from the case material 14.

  With reference to FIG. 4C, still another form of the circuit device 10 will be described. Here, the upper surfaces of the memories 18 and 20 are also thermally coupled to the bottom surface portion 14 </ b> A of the case material 14 via the heat conductive sheet 34. By doing in this way, the heat | fever generate | occur | produced by operation | movement of the memories 18 and 20 is discharge | released favorably outside via the case material 14, and the overheating of the memories 18 and 20 is prevented.

  Referring to FIG. 4D, here, a radiator 70 is attached to the bottom surface portion 14 </ b> A of the case material 14. The radiator 70 is made of a metal having excellent thermal conductivity, such as aluminum or copper, the lower surface is a flat surface that is in surface contact with the case material 14, and the upper surface is formed into an atypical liquid in order to increase the surface area. . By doing so, the heat generated from the circuit elements such as the signal processing element 16 is released to the outside through the case material 14 and the heat radiator 70, so that the heat dissipation of the entire apparatus is further improved. .

  The direction when the signal processing element 16 is mounted will be described with reference to FIG. FIG. 5A is a plan view showing a state in which the signal processing elements 16 are arranged to be inclined in plan view, and FIG. 5B is a plan view showing a comparative example.

  Referring to FIG. 5A, the signal processing element 16 is arranged such that its side is inclined with respect to the direction in which the memories 18 and 20 are aligned. In general, when three elements are arranged in the horizontal direction, they are arranged so that the sides are parallel to each other, but here, the signal processing element 16 at the center is rotated 45 degrees in plan view. And implemented.

  In this figure, the direction of alignment is indicated by a one-dot chain line, and the angle θ formed by the direction in which the memories 18 and 20 are arranged (the one-dot chain line) and the side of the signal processing element 16 is 45 degrees, for example. .

  By doing so, the difference in length between the wiring 44 connecting the memory 18 and the signal processing element 16 and the wiring 46 connecting the memory 20 and the signal processing element 16 is shortened.

  Specifically, the pad included in the signal processing element 16 is connected to either the memory 18 or the memory 20. For example, a pad 40 provided along one side of the signal processing element 16 is connected to the left memory 18 on the paper surface, and a pad 41 provided on the side adjacent to this side is connected to the right memory 20. May be connected.

  In this case, as shown in FIG. 5B, a problem is expected when the signal processing element 16 is mounted in the same manner as the memories 18 and 20 by a general mounting method. That is, the length L4 of the wiring 44 connecting the left memory 18 and the pad 40 on the paper is longer than the length L5 of the wiring 46 connecting the right memory 20 and the pad 41 on the paper. In this case, a problem of signal delay occurs due to a difference in wiring length.

  In this embodiment, as shown in FIG. 5A, the signal processing element 16 is mounted in a state rotated by 45 degrees in plan view. Thus, although the lengths of the wiring 46 and the wiring 44 are slightly different from each other, the difference in length between the wiring 46 and the wiring 44 is shorter than that in the case of FIG. As a result, problems such as signal delay due to different wire lengths are alleviated.

DESCRIPTION OF SYMBOLS 10 Circuit apparatus 12 Board | substrate 14 Case material 14A Bottom surface part 14B Side surface part 16 Signal processing element 18 Memory 20 Memory 22 Signal processing element 24 Chip type element 26 Oscillator 28 Opening part 30 Connection bump 32, 32A External connection bump 34 Thermal conduction sheet 36 concave portion 38 pad 40 pad 41 pad 42 pad 44 wiring 46 wiring 48 pad 50 connection bump 52 wiring pad 54 wiring pad 56 wiring layer 58 wiring layer 60 wiring layer 62 wiring layer 63 wiring layer 64 via hole 66 land 68 wiring portion

Claims (12)

A substrate having a first main surface and a second main surface;
A circuit element disposed on the first main surface of the substrate;
A case material having a bottom surface portion and a side surface portion and attached to the first main surface of the substrate so as to surround the circuit element;
A connection bump disposed on the second main surface of the substrate,
At least a part of the connection bump is disposed at a position overlapping the side surface portion of the case material.   2. The circuit device according to claim 1, wherein the connection bumps are provided in a row at positions overlapping with the four side portions constituting the case material.   The circuit device according to claim 1, wherein an opening is provided in the side surface of the case material.   The circuit device according to any one of claims 1 to 3, wherein a heat conductive sheet is disposed between the circuit element and the bottom surface portion of the case material.   The circuit device according to claim 1, wherein the connection bumps are arranged in a matrix on the second main surface of the substrate.   6. The circuit device according to claim 1, wherein the connection bumps arranged in a rectangular ring shape at an outermost periphery are arranged so as to overlap with the side surface portion of the case material. The circuit element includes a semiconductor element arranged face down,
7. The circuit device according to claim 1, wherein wiring pads arranged at a pitch equal to a pad included in the semiconductor element are provided on the first main surface of the substrate. 8. .   The circuit device according to claim 7, wherein a via hole connected to the wiring pad is disposed on the substrate around the semiconductor element.   The circuit element includes a first memory, a second memory, and a signal processing element disposed in a region sandwiched between the first memory and the second memory. The circuit device according to claim 8. Thermally coupling the signal processing element to the bottom surface of the case material;
The circuit device according to claim 9, wherein the first memory and the second memory are separated from the bottom surface portion of the case material.   11. The signal processing element according to claim 9, wherein the signal processing element is arranged such that a side thereof is inclined with respect to a direction in which the first memory and the second memory are aligned. Circuit device. 12. The circuit device according to claim 11, wherein the side of the signal processing element is inclined at an angle of 45 degrees with respect to a direction in which the first memory and the second memory are aligned.

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