JPH03173435A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To sharply increase the degree of freedom of wiring between chips by using a metallic wiring layer used for the internal wiring of a chip on a scribe line formed between the chips end forming in advance metallic wiring to be used for wiring between chips after inspections. CONSTITUTION:When wafer scale integration(WSI) is performed, metallic wiring to be used for the internal wiring of chips is formed in advance on a scribe line formed between the chips. The figure illustrates a chip 20 provided with, for example, 10 pieces of pads 10-19 respectively having bridges 2 and openings 1 for connection. Since the wiring lines are made to intersect each other on the chip, the wiring between the chips is made easier and the length of the lines is made shorter. As a result, the delay of signals can be reduced and, at the same time, the fraction nondefective of this semiconductor integrated circuit device can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device whose purpose is to improve the degree of freedom in interconnection between chips when forming a WSI.

[Prior art 1] As shown in FIG. 2, the conventional WSI configuration method is to remove an insulating protective film (passivation film) 23 formed on a wiring metal 2 in a chip using photoetching technology. An electrical test is performed by contacting the metal probe with the pad portions (10 to 19) that have been drilled to expose the metal wiring underneath, and the chip position determined to be normal is memorized. Using a normal semiconductor integrated circuit manufacturing method, a metal TLI3 such as aluminum or its alloy is formed, and the pads of chips determined to be normal are interconnected using photonolithography technology according to an appropriate inter-chip interconnection pattern. It was formed by doing.

[Problems to be Solved by the Invention] However, it is difficult to perform appropriate inter-chip interconnection according to the mutual arrangement of chips determined to be normal using only a single layer of inter-chip interconnection metal film. In many cases, it is incomprehensible. Even if it is possible, the signal line usually has to bypass the power supply wiring, which causes problems such as long wiring and signal delays, and the increase in parallel wiring, which tends to generate noise. . To avoid this, inter-chip interconnections can be formed using two or more layers of metal film and insulating film, but this not only complicates the process but also reduces the yield rate and increases cost. happens.

[Means for Solving the Problems] The present invention has been made to solve the above problems, and includes a plurality of chip-like machines in testable chips formed on the main surface of a semiconductor substrate. without dividing the
When forming a semiconductor integrated circuit device that integrates a plurality of functions by interconnecting chips that are determined to operate normally during inspection, the chips are placed on the scribe line formed between the chips. It is characterized in that metal wiring to be used for inter-chip interconnection after inspection is formed in advance (bridge) using a metal wiring layer used for internal wiring.

[Function] According to the above configuration of the present invention, the metal wiring (bridge) for inter-chip interconnection using the metal wiring layer used for the internal wiring of the chip formed in advance and the inter-chip interconnection formed after inspection. Since the interconnects are sandwiched by a passivation film (insulating film), they can cross each other, and single-layer inter-chip interconnects can be used to form interconnects with the same degree of freedom as two-layer inter-chip interconnects. becomes possible.

[Example] The present invention will be explained in detail below using figures.

To simplify the explanation, this example describes a case where WSI is performed using chips A, C, and D, which were determined to be normal in the inspection, and chip B, which was determined to be abnormal, but this is a simple example. , is actually more complicated. In particular, this example is an example in which all pads of three normal chips are connected in parallel. Also, there is a restriction that only three interconnections between chips can pass between adjacent pads, and 12.17
The assumption is made that the pads are power supply pads and that their interconnections are prioritized. FIG. 2 shows an example in which conventional single-layer inter-chip interconnections 3 are used, and since these interconnections cannot cross each other, some of the interconnections are thick (necessary to take detours). (a) shows 10 pads (
10 to 19). Figure 1 (
b) is an example of the same example in which the bridge 2 and connection opening 1 of the present invention are crossed at the upper part to facilitate interconnection between chips and to shorten the wiring length. In this case, interconnection between chips was possible using conventional methods, but in the case of more complex WSIs, interconnection between chips is often impossible using conventional methods. Although six bridges 2 are used in this example, it goes without saying that the degree of freedom in wiring can be greatly improved by appropriately arranging the number, position, and length of bridges according to the scale of the WSI and the number of pads. Needless to say, reliability can be improved by forming a passivation film made of an insulating film on the inter-chip interconnections 3. FIG. 1(C) is a cross-sectional view schematically showing that the bridge 2 on the scribe line and the interchip metal wiring 3 intersect in the present invention.

[Effects of the Invention 1] As described above, according to the present invention, when performing WSI, interchip interconnections are intersected by crossing the interchip interconnections on bridges formed in advance on scribe lines. The degree of freedom in mutual wiring can be greatly improved.

This made it possible to shorten the wiring, reduce signal delay, and improve the rate of non-defective products.As a result, large-scale WSI could be realized without increasing costs. Further, even when each chip is used alone, the bridge of the present invention does not become an obstacle.

[Brief explanation of the drawing]

FIGS. 1(a) to (c) are diagrams schematically representing a semiconductor integrated circuit device of the present invention, and FIGS. 2(a) and (b) are diagrams schematically representing a conventional WSI. However, Fig. 1(b)
And Figure 2 (a) shows chip A that was determined to be normal in the inspection.
, C, D and WSIL using chip B that was determined to be abnormal.
This is a simple example; FIG. 1(a) is a plan view showing ten pads of a chip including the bridge of the present invention, and FIG. 1(C) is a plan view showing the intersection of the bridge and inter-chip interconnection FIG. 2 is a sectional view taken along the line α-α' in FIG. 21... Semiconductor substrate 22... Insulating film 23... Passivation film 24... Field oxide film

Claims (1)

[Claims] In testable integrated circuits (hereinafter referred to as chips) formed on the main surface of a semiconductor substrate, chips that are determined to operate normally during testing are interconnected without mechanically dividing the multiple chips. When forming a semiconductor integrated circuit device (hereinafter referred to as wafer scale integration, WSI) in which multiple functions are integrated by wiring, the internal wiring of the chip is placed on the scribe line formed between the chips. 1. A semiconductor integrated circuit device characterized in that metal wiring (hereinafter referred to as a bridge) to be used for inter-chip interconnection after inspection is formed in advance using a metal wiring layer used for.