JPH0636580Y2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a semiconductor integrated circuit, and more particularly to a small scale semiconductor integrated circuit required to operate at high speed.

[Conventional technology]

Conventionally, this type of semiconductor integrated circuit has been inspected after being assembled into a package, without inspecting the high-speed operation performance in a wafer state.

[Problems to be solved by the invention]

In the conventional semiconductor integrated circuit described above, the inspection of the high speed operation performance of the integrated circuit cannot be performed due to the limitation of the high speed operation performance of the inspection device in the inspection in the wafer state. Therefore, this inspection can be performed only after the package is assembled. There is a problem.

Also, in order to solve this point in a large-scale semiconductor integrated circuit,
Some integrated circuits include an inspection circuit capable of inspecting high-speed operation performance in a wafer state, but there is a problem that it cannot be realized by a small-scale semiconductor integrated circuit because the circuit scale becomes large.

[Means for solving problems]

The semiconductor integrated circuit of the present invention comprises a plurality of first integrated circuit chips and a second integrated circuit chip on which a plurality of high-speed operation performance inspection circuits each having an input terminal, an output terminal and a power supply terminal are mounted. is doing.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.

As shown in FIG. 1, the semiconductor integrated circuit 1 of the present invention is 20 first integrated circuit chip of high-speed operation (internal circuit not shown) with 2 _{2-2 20,} for inspecting high-speed operation performance It has test chips 3 to 7 as five second integrated circuit chips on which a high-speed operation performance test circuit is separately mounted. The position of the pad 8 for bonding in the test chip 3-7 to identical integrated circuit chips 2 ₁ to 2 _20.

The high-speed operation performance inspection circuit mounted separately on the inspection chips 3 to 7 has a ring type oscillation circuit 9 in which an odd number of inverter circuits are connected in a loop and a frequency dividing circuit 10 and has a single inspection function.

High-speed operation performance inspection pad (internal wiring not shown) 8 _P , signal input pad 8 _IN, and signal output pad 8 on inspection chip 3
There are all _OUT pads, and the power supply line and the input and output signal lines are not connected to any of the pads 8 of the inspection chips 4 to 7.

Chip identification resistor 11 ₁ to 11 ₂₀ is provided between each of the special pad of the integrated circuit chip 2 ₁ to 2 _20, the chip identification resistor 12 ₃ between the same positions of each of the test chip 3-7 pads
~ 12 ₇ are provided. The chip identification resistors 11 _{1 to} 11 ₂₀ , the chip identification resistor 12 ₃ and the chip identification resistors 12 _{4 to} 12 ₇ have different resistance values, so that three types of chips can be identified.

During automatic wafer inspection probing, a signal is externally input to the signal input pad 8 _IN of the inspection chip 3 to oscillate the ring-shaped oscillator circuit 9, and the output of the frequency divider circuit 10 at a frequency that can be measured in the wafer state is output. By measuring at the signal output pad 8 _OUT of the inspection chip 3, the integrated circuit chips 2 ₁ to 2
₂₀ high-speed operation performance can be confirmed in a wafer state.

[Effect of device]

As described above, the semiconductor integrated circuit of the present invention is a small-scale semiconductor integrated circuit having a small chip area by deploying and mounting a large-scale circuit for high-speed operation performance inspection over a plurality of chips. Since high-speed operation performance can be inspected during wafer inspection, there is an effect that the high-speed performance of the integrated circuit can be confirmed before assembly.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention. 1 ...... semiconductor integrated circuit, 2 ₁ to 2 ₂₀ ...... integrated circuit chip,
3 to 7 ... Inspection chip, 8 ... Pad, 8 _IN ...... Signal input pad, 8 _OUT ...... Signal output pad, 8 _P ...... Power supply pad, 9 ...... Ring type oscillation circuit, 10 ...... Dividing Circuit, 11 ₁
~ 11 ₂₀ , 12 ₃ ~ 12 ₇ ... Chip identification resistor.

Claims (1)

[Scope of utility model registration request] 1. A first and a second formed on a semiconductor wafer.
Integrated circuit chips having first and second integrated circuit chips each having an input / output pad at the same position in the chip, and a predetermined test circuit formed over the plurality of second integrated circuit chips. And the input / output terminals of the inspection circuit are both connected to the input / output pad of one of the plurality of the second integrated circuit chips.