JPH04373143A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor integrated circuit device in which the area of a chip is reduced. CONSTITUTION:A test circuit 2a is formed on a dicing line 3, and connected with an internal circuit 4 constituted generally of a selector or the like, by using a wiring 6. A plurality of chips 1 are made to commonly use one test circuit 2a. Thereby the chip area can be reduced, so that the number of chips which can be obtained from one wafer is increased, and the device cost is reduced.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and particularly to one in which the area of one chip is reduced.

0002

2. Description of the Related Art FIG. 3 is a plan view of the main parts of a conventional semiconductor integrated circuit device in a wafer state. In the figure,
1 is a chip, 2a is a test circuit, a diagonally shaded area 3 for clarity is a dicing line which is a cutting margin when dividing the IC into each chip, 4 is an internal circuit generally consisting of a selector, etc. 5 is an internal circuit for achieving the original function of the integrated circuit; 7 is a bonding pad; 8 is an internal circuit for achieving the original function of the integrated circuit;
a is a test pad (bonding pad), and 9 is a wiring inside the chip 1.

Next, the operation will be explained. The internal circuit 4 is generally composed of a selector and the like, and selects the input from the bonding pad 7 during normal operation of the semiconductor integrated circuit device and the output from the test circuit 2a during testing.
Enter.

0004

[Problems to be Solved by the Invention] The conventional semiconductor integrated circuit device is provided with the test circuit 2a inside the chip 1 as described above, but the test circuit 2a is provided only to easily test the semiconductor integrated circuit device. This circuit is unnecessary during normal operation of this device. For this reason, the conventional semiconductor integrated circuit device has a problem in that the area of the chip 1 increases by the area occupied by the test circuit 2a. Further, since the test circuit 2a is provided inside the chip 1, there is a problem in that a test pad 8a (bonding pad) for inputting/outputting data and controlling input to the test circuit 2a is also required inside the chip.

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor integrated circuit device that can reduce the chip area.

[0006]

[Means for Solving the Problems] A semiconductor integrated circuit device according to the present invention includes a test circuit that is unnecessary during normal operation of the device, which is provided on a dicing line, and a wiring between this test circuit and an internal circuit within a chip. It is something. Also,
The above test circuit is shared by multiple chips.

[0007]

[Function] By providing a test circuit on the dicing line of the device substrate, the semiconductor integrated circuit device of the present invention can reduce the chip area by the area of the test circuit that is unnecessary during normal operation of the semiconductor integrated circuit device. By sharing the test circuit with multiple chips,
The number of chips obtained from one wafer can be increased.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view of the main parts of a semiconductor integrated circuit device according to an embodiment of the present invention when it is in a wafer state. In the figure, 1 is a chip, and 2a is a test circuit, which is provided on a dicing line 3. 4 is an internal circuit generally composed of a selector, etc.; 5 is an internal circuit for achieving the original functions of the integrated circuit; 6 is wiring connecting the test circuit 2a provided on the dicing line 3 and the internal circuit 4; 7 is a bonding pad, 8a is a test pad, and 9 is a wiring inside the chip 1.

Next, the operation of the above embodiment will be explained. The output of the test circuit 2a and the input from the bonding pad 7 are selected by the internal circuit 4 and input to the internal circuit 5. The internal circuit 4 is generally composed of a selector and the like, and selects the input from the bonding pad 7 during normal operation of the semiconductor integrated circuit device, and selects the output from the test circuit 2a during testing.

Since the test circuit 2a is a circuit for easily testing the semiconductor integrated circuit device, it is unnecessary during normal operation of the semiconductor integrated circuit device. Therefore, the test circuit 2a is not provided inside the chip 1 as shown in FIG. 2(a), but is formed on the dicing line 3 on the semiconductor integrated circuit device substrate. At this time, Figure 2 (
In the first embodiment shown in FIG. 2(b), one test circuit 2a is provided on the dicing line 3 for one chip 1, and the test circuit 2a is provided on the dicing line 3 for one chip 1. Also, the area of the chip 1 can be reduced by the area of the test circuit 2a. Further, in the second embodiment shown in FIGS. 1 and 2(c), one test circuit 2a provided on the dicing line 3 is shared by a plurality of chips 1. In this case, a test pad 8a for inputting and outputting to the test circuit 2a is also provided in the test circuit 2a, and the chip 1
Since the area of the chip 1 can be further reduced by the area occupied by the test circuit 2a and the test pad 8a.

[0011]

As described above, according to the present invention, a test circuit that is unnecessary during normal operation of a semiconductor integrated circuit device is provided on a dicing line, so that the chip area can be reduced. Furthermore, if this test circuit is shared by a plurality of chips, the number of chips that can be obtained from one wafer increases, which has the effect of making the device cheaper.

[Brief explanation of the drawing]

FIG. 1 is a plan view of essential parts of a semiconductor integrated circuit device in a wafer state according to an embodiment of the present invention.

[Fig. 2] A plan view of the wafer state of a conventional semiconductor integrated circuit device, a plan view of the wafer state in the case of one chip for one test circuit, and a plan view of the wafer state in the case of one chip for one test circuit, and one test circuit shared by multiple chips according to the present invention. FIG. 3 is a plan view of the wafer state when

FIG. 3 is a plan view of main parts of a conventional semiconductor integrated circuit device in a wafer state.

[Explanation of symbols]

1 Chip 2a Test circuit 3 Dicing line 4 Internal circuit (selector) 6 Wiring 7 connecting test circuit 2a and internal circuit 4 Bonding pad 8a Test pad

Claims (2)

[Claims] 1. A semiconductor integrated circuit device comprising: a test circuit provided on a dicing line on a semiconductor integrated circuit device substrate; and wiring connecting the test circuit to an internal circuit inside a chip. 2. A semiconductor integrated circuit device as described above, wherein a test circuit provided on a dicing line is shared by a plurality of chips.