JPH05175334A - Semiconductor integrated circuit and layout method thereof - Google Patents

Abstract

PURPOSE:To prevent the wiring length from becoming too long concerning a semiconductor integrated circuit of a standard cell method and a layout method thereof. CONSTITUTION:A macro module comprising a core region 23, a wiring region 24 formed on the circumference of the core region 23, and a buffer arrangement region 25 adjacent to the wiring region 24 is adopted. After determining the arrangement position of the core region 23 in the macro module, the arrangement position of the buffer region 25 in the macro module is determined.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a standard cell type semiconductor integrated circuit and a layout method thereof.

[0002]

2. Description of the Related Art The standard cell system is widely adopted as one of the design systems for semiconductor integrated circuits. The standard cell system is a semiconductor integrated circuit that registers various standard cells that have been designed and whose operation has been verified in advance, and that in the actual design, the various standard cells that have been registered are combined to satisfy a desired logic function. It is a method to realize a circuit. These standard cells are
Although it usually has simple logic gates and logical functions such as flip-flops, it registers various macro modules in which quite complicated circuits are integrated, arranges some macro modules, and then arranges those macro modules. In some cases, a circuit in one semiconductor chip may be configured by wiring between them and between the macro module and an input / output circuit connected to an external circuit.

FIG. 3 is a schematic diagram showing an example of a layout of a conventional semiconductor integrated circuit using a macro module. In this example, five macro modules A to E are used, and the internal output buffer 1 in the macro module A passes through a terminal a1, a wire l _{1 of} the macro module A, and a terminal d1 of the macro module D to It is connected to the internal input buffer 14 of the module D. Similarly, the internal input / output buffers ₂ , ₃ , ₄ of the macro module A have terminals a ₂ , a ₃ , a ₄ and wirings l, respectively.
Input / output buffers 15 and 1 for each internal of the macro module D via ₂ , l ₃ and l ₄ and terminals d ₂ , d ₃ and d _4.
6 and 17 are connected. Also, macro module A
The internal output buffers 5 and 6 of the macro module B are connected to the internal input buffers 13 and 12 of the macro module B via the terminals a ₅ and a ₆ , the wirings l ₈ and l ₉ and the terminals b ₂ and b ₁ , respectively. It is connected. Further, the internal output buffers 7 and 8 of the macro module are connected to the I / O buffers 21 and 22 via terminals a ₇ and a ₈ , wirings l ₁₀ and l ₁₁ , terminals f ₁ and g ₁ , respectively. ing. Further, the internal output buffer 9 and the input / output buffers 10 and 11 of the macro module A are connected to the terminals a.
₉ , a ₁₀ , a ₁₁ , wirings l ₅ , l ₆ , l ₇ and terminals e
The internal input buffer 18 of the macro module E and the internal input / output buffers 19, 20 via ₁ , e ₂ , e ₃
Connected with.

As described above, each macro module A to E
, The other macro module or I /
An internal input buffer, an internal output buffer, or an input / output buffer (hereinafter collectively referred to simply as “buffer” for simplicity) and each terminal for connecting to the O buffer are provided. The entire circuit is completed by wiring the terminals.

[0005]

However, since the macro module defines the arrangement position of each element constituting the macro module, including the buffer arrangement position and the terminal arrangement position in the macro module, the macro module is some modules of the combination or layout, for example, the wiring length as line _{l 5 ~l 7, l 10,} l 11 shown in FIG. 3 becomes extremely long, which may hinder high-speed operation. This forced us to change the layout,
If the layout cannot be dealt with, it may be necessary to take measures such as arranging a buffer on the way.

In view of the above circumstances, it is an object of the present invention to provide a standard cell type semiconductor integrated circuit in which the wiring length is prevented from becoming extremely long and a layout method thereof.

[0007]

A semiconductor integrated circuit of the present invention which achieves the above object is a standard cell type semiconductor integrated circuit, wherein a core region, a wiring region formed around the core region and the wiring are formed. The present invention is characterized in that a macro module including a buffer arrangement area adjacent to the area is provided.

The semiconductor integrated circuit layout method of the present invention is the same as the standard cell type semiconductor integrated circuit layout method, in which the core region, the wiring region formed around the core region, and the wiring region are adjacent to the core region. And a buffer arranging area of the macro module is used, and after arranging the arranging position of the core area of the macro module, the arranging position of the buffer of the macro module is determined.

[0009]

According to the present invention, the macro module is divided into the core area and the buffer arranging area, and the buffer arranging position is determined later. Therefore, the layout is simplified and the wiring length is prevented from becoming extremely long. To be done.

[0010]

EXAMPLES Examples of the present invention will be described below. Figure 1
FIG. 3 is a schematic diagram showing one macro module in a semiconductor integrated circuit according to an embodiment of the present invention. A macro module A ′ shown in this figure is a macro module having a function equivalent to that of the macro module A shown in FIG. 3, and the macro module A ′ has terminals arranged at the same positions as the terminals of the macro module A shown in FIG. 3 are denoted by the same reference numerals as those shown in FIG. 3, and terminals arranged in the same function and different arrangement as those of the terminals of the macro module A shown in FIG. 3 have the same reference numerals as those shown in FIG. The symbols are shown with dashes.

The macro module A'includes a core region 23 formed by combining a large number of logic circuit elements, a wiring region 24 around the core region 23, and a buffer placement region adjacent to the wiring region 24. 25 and 25. Here, the wiring region 2 around the core region 23
4 and buffer placement area 25,
First, the layout of the core region 23 on the semiconductor chip is determined, and then, considering the arrangement of another macro module or I / O buffer connected to this macro module A ′, the wiring extending from this macro module A ′ to the outside is considered. Layout each buffer and each terminal so that the length is short. At this time, the wiring from the core region 23 to the buffer may extend to some extent, but since it is wired in the vicinity of the core region 23, its length does not become extremely long. The length of the macro module A'can be sufficiently considered at the design stage.

FIG. 2 is a schematic diagram of a layout on a semiconductor chip when the macro module A'where the buffers are arranged as shown in FIG. 1 is arranged in place of the macro module A shown in FIG. In FIG. 2, the buffer is not shown in order to avoid complexity. 'By placing the buffer and terminals as shown in Figure 1, in the FIG. 2 line l _5' macro module A to l
₇ ', l _10', as shown in l ₁₁ ', it will be taking less wiring compared with each wiring _{l 5 ~l 7, l 10,} l 11 shown in FIG. 3, between the macro module or macro module and I This makes it possible to cope with high-speed operation without providing a buffer in the middle of the wiring that connects to the / O buffer.

[0013]

As described above, according to the semiconductor integrated circuit and the layout method thereof of the present invention, the core region and the buffer arranging region are separated from each other and the wiring region is provided between them, and the buffer is considered in consideration of the entire layout. Since the arrangement position is decided, the macro module and other circuits or I /
The length of the wiring connecting to the O buffer can be shortened,
A semiconductor integrated circuit suitable for high-speed processing will be realized.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing one macro module in a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a layout on a semiconductor chip in which a macro module A ′ shown in FIG. 1 is arranged instead of the macro module A shown in FIG.

FIG. 3 is a schematic diagram showing an example of a layout of a conventional semiconductor integrated circuit using a macro module.

[Explanation of symbols]

A, A ', B, C , D, E macromodule _{a 1, a 2, a 3} , ..., b 1, b 2, ... terminal _{l 1, l 2, l 3} , ... wire 23 core region 24 wiring region 25 buffer placement area

Claims (2)

[Claims] 1. A standard cell type semiconductor integrated circuit comprising a macro module comprising a core region, a wiring region formed around the core region, and a buffer arrangement region adjacent to the wiring region. A characteristic semiconductor integrated circuit. 2. A standard module type semiconductor integrated circuit layout method employs a macro module comprising a core region, a wiring region formed around the core region, and a buffer arrangement region adjacent to the wiring region. The layout method of the semiconductor integrated circuit is characterized in that after the arrangement position of the core region of the macro module is determined, the arrangement position of the buffer of the micro module is determined.