JPH08213467A - Designing scheme for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: To reduce a time required for development and a chip area by analyzing the first delay characteristic of an internal circuit, excluding an input/output buffer, subsequently, analyzing the second delay characteristic of a chip, including the input/output buffer, and then verifying whether characteristic requirements are met or not. CONSTITUTION: An internal block is laid out, and a first delay simulation is performed (101, 102). It is verified based on the result of the delay simulation whether there is no problem associated with characteristics (103). After a buffer allocating process, buffers in the internal block and a peripheral block are placed and wired, and the chip is finally laid out (104, 105). In addition a second delay simulation is performed, and final specifications are checked based on the result of the second delay simulation (106, 107). This accomplishes the reduction of the area of the chip and the time required for its development.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a layout method for a semiconductor integrated circuit.

[0002]

2. Description of the Related Art A conventional process flow of layout of a semiconductor integrated circuit chip will be described below with reference to FIG.

Referring to FIG. 2, in the conventional layout method, first, except for the blocks of the input / output buffers arranged on the outer periphery of the chip, only the internal circuits are automatically arranged and wired by a CAD system or the like (step
201). One block is formed by appropriately arranging and wiring the internal circuits. This one block is called "internal block". Further, the range in which the input / output buffers are arranged is called "outer peripheral block". Note that step 200 represents a step before the layout step of the semiconductor integrated circuit.

After the internal block is completed, wiring between the terminal of the internal block and the terminal of the input / output buffer in the outer peripheral block corresponding to this terminal is performed by a predetermined CAD system or the like (step 202).

By the way, the types of input / output buffers arranged in the outer peripheral block (for example, input buffer, output buffer,
The bidirectional buffer etc.) and the location of arrangement are often predetermined based on the specifications required for the integrated circuit. In this case, in the CAD system, only the wiring between the internal block and the external block is mainly used.

As described above, when the placement and wiring of the entire integrated circuit are completed, a simulation is performed to verify whether the completed integrated circuit satisfies the original electrical specifications (step 203).

The simulation is mainly performed on the AC characteristic, and the result of simulating the sense amplifier, the hold, the delay time, etc. is judged (step 204). If the predetermined characteristic is not satisfied, as shown in the figure. Return to step 201, re-arrange the internal circuit and wiring performed earlier, or move the arrangement of the input / output buffer on the outer peripheral block, and then perform the series of operations described above.
Confirm the AC characteristics etc. by simulation again. Thereafter, this work is repeated until the desired characteristics are satisfied.

[0008]

In the above-mentioned conventional layout method, the required characteristics cannot always be achieved by the first layout, and the internal circuit is rearranged, re-routed, and the input / output on the outer peripheral block is repeated several times. In many cases, steps such as buffer placement and movement are repeated, which lengthens the development period. In addition, recently, the characteristics required for the integrated circuit are becoming stricter, which tends to prolong the development period.

By the way, among the items which do not satisfy the characteristics, one of the items which is a particularly serious problem is that the delay time difference (skew) of the input / output buffers is not uniform, so that one integrated circuit and a signal to and from this integrated circuit are transmitted and received. However, there is a problem that the interface with another integrated circuit is disturbed.

To solve such a problem, for example, Japanese Patent Laid-Open No.
-220522 includes a plurality of delay macros each having a different delay amount, and at least one of these different delay amounts is selected and connected between the output end of the internal macro and the input end of the output buffer, A method has been proposed in which a delay circuit for giving a predetermined delay amount to a macro output signal and inputting it to an output buffer circuit is provided, and the delay time is adjusted for each buffer. Further, in Japanese Patent Application Laid-Open No. 4-134922, for the purpose of providing a semiconductor integrated circuit capable of easily taking measures against a minimum delay time violation without requiring an external element or the like, the semiconductor integrated circuit is connected in a different number of stages depending on the wiring. A design method of a semiconductor integrated circuit has been proposed, which is characterized by adjusting a delay time of a delay time violation path by using a delay time adjustment cell which stores a plurality of buffer gates connected to each other. A plurality of cells for use are arranged in advance in a chip according to a predetermined pattern.

However, in the methods described in both of the above publications, the delay time between the buffers can be adjusted, but a plurality of delays are required to enable the adjustment of an arbitrary delay amount for each buffer. Macro, delay circuit for delay adjustment,
A control circuit such as a delay path, a switching terminal for the delay path, and a path selection multiplexer is required, which increases the buffer area.

That is, even if there is a buffer that does not require delay adjustment, a circuit for delay adjustment that is not used is included in the buffer as it is, and the chip area increases.

Further, this means that even if a common delay adjusting circuit is used among a plurality of buffers without preparing a circuit for adjusting the delay amount for each buffer, all the prepared circuits are It cannot be used (the redundant circuit must be prepared so that it can be used in any case), and the generation of an extra unused circuit cannot be avoided. Therefore, in any case, it is inevitable that the chip area increases.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to solve the above problems and to provide a layout method of a semiconductor integrated circuit which shortens the development period and reduces the chip area in the layout of the semiconductor integrated circuit chip.

[0015]

In order to achieve the above object, the present invention performs a first delay characteristic analysis on the internal block after laying out an internal circuit of the semiconductor integrated circuit excluding the input / output buffer, A buffer having an optimum delay characteristic is selected from input / output buffers registered in advance based on the result of the first delay characteristic analysis, and the layout of the internal circuit and the input / output buffer is selected by using the selected buffer. And performing a second delay characteristic analysis on a chip including the laid-out internal circuit and the input / output buffer, and confirming a required characteristic based on a result of the second delay characteristic analysis. Provided is a semiconductor integrated circuit design method.

In a preferred embodiment of the present invention, a plurality of input / output buffers of the same type having different delay times are registered in advance as macroblocks, and the layout process is performed in two stages, and the first stage layout process is performed. In the automatic placement / wiring CAD system,
After arranging and wiring the internal circuit excluding the input / output buffer, a first delay simulation is executed for the internal circuit, and among the plurality of input / output buffers registered in advance based on the result of the first delay simulation. A buffer having an optimum delay characteristic is selected from the above, and in the second-stage layout process, the automatic placement / wiring CAD is performed.
A system performs placement and wiring between the internal circuit and the input / output buffer by using the selected buffer, and a signal path of a chip including the arranged internal circuit and the input / output buffer The delay simulation is executed and whether or not the required characteristics are satisfied is confirmed based on the result of the second simulation.

[0017]

The operation and principle of the present invention will be described below. According to the layout method of the present invention, a plurality of types of buffers designed by gradually changing the delay amount are prepared, and each buffer is registered as a dedicated macro in the buffer block. And
The layout of the chip is divided into two stages, and after the layout of the first stage is completed, a delay amount simulation based on the layout information is performed. As a result of this delay simulation, for a signal line that requires adjustment of the delay amount, an optimum buffer for correcting it is selected from the dedicated macros registered as buffer blocks.

Then, after the types of buffers connected to the signal terminals of all integrated circuits are determined, the second stage layout is carried out. In this layout, the layout of the buffer and the wiring between the outer peripheral block in which the buffer is arranged and the internal block are implemented.

After the completion of the layout of the second stage, the delay simulation including the buffer is performed again.
As described above, according to the layout method, all the buffers are designed as dedicated macros with optimized delay amounts, so that there is no useless delay adjustment circuit. Further, since the optimized buffer has already been selected by the delay simulation of the first stage, the probability of occurrence of the non-conforming state is extremely low in the result of the delay simulation of the second stage. Therefore, according to the present invention, the probability of re-layout is significantly reduced as compared with the method of performing the delay simulation when the chip layout is completed as in the conventional example, and the LSI that guarantees the desired delay characteristic is obtained.
In comparison with the conventional method, the chip area can be further reduced and the development period can be shortened.

In the layout method according to the present invention,
Compared with the conventional method, the number of simulations at the time when the arrangement of internal circuits is completed increases, so it seems that the processing time increases once. However, in the conventional method layout, good results can be obtained only once. In most cases, the relayout may be repeated 2-3 times. In this case, considering that the relayout takes a long time and the development period becomes long, the layout method of the present invention is very effective in shortening the development period.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a flowchart illustrating a layout method according to an exemplary embodiment of the present invention.

Referring to FIG. 1, at the stage of laying out the internal blocks (step 101), the first delay simulation is performed (step 102), and the result of the delay simulation indicates whether there is any problem in characteristics. Confirmation (determination) is performed (step 103). In addition, step 1
Reference numerals 00 and 109 respectively indicate a pre-process and a post-process of the layout process according to this embodiment.

In the determination of step 103, if a characteristic fault that cannot be advanced to the next process as it is is found, the process returns to step 101 and the internal block layout is redone.

If no particular fault is detected from the result of the delay simulation, or if there is some problem but it can be absorbed in the buffer selection process of the next process, the optimum value for each signal line is obtained based on the result of the delay simulation. Allocate a buffer (step 104). This buffer is
As a buffer in which a plurality of different delay characteristics are given to the same type of buffer, it is registered in advance in the CAD system as a dedicated macro block. That is, for example, after designing buffers having a plurality of types of delay characteristics for each output buffer, these buffers are subjected to CAD
Register in advance on the system.

In the allocation of the optimum buffer, the purpose of correcting the delay time between the signal lines based on the result of the delay simulation (depending on the purpose, eliminating the delay time difference between the signal lines or conversely guaranteeing the delay time difference). Then, among these buffers, the buffer having the optimum delay time for the signal line is combined.

In this embodiment, since these buffers are exclusively designed to have their own delay time, they are described in JP-A-1-220522 or JP-A-4-134922. It does not include a redundant circuit like a buffer, and an optimized minimum layout design is possible. Therefore, the final chip size can be reduced.

According to the present embodiment, as shown in FIG. 1, after the buffer allocation process (step 104),
The final chip layout is performed by arranging and wiring the buffers of the inner block and the outer block (step 105), and then the second delay simulation is performed (step 106), based on the result of the second delay simulation. Confirm the final specifications (step
107).

In this embodiment, since the basic characteristic confirmation has already been completed in the first delay simulation (step 102), a large failure is detected in the second delay simulation (step 106). It's unlikely. Even if some inconveniences are detected in the determination in step 107, after determining a correction location (step 108), the process returns to step 105, and the chip layout can be corrected by a slight correction. For this reason,
Development TAT (Turn Around Time) can be shortened.

In contrast to this embodiment, in the conventional method shown in FIG. 2, the first simulation in this embodiment,
In addition, since the step of selecting a buffer based on this result is omitted, the influence when a failure is detected in the simulation after the chip layout is large, and often the change is frequent depending on the return destination, and the development TAT is Often significantly increased.

Although the present invention has been described with reference to the above embodiments, it is needless to say that the present invention is not limited to the above embodiments and includes various embodiments according to the principles of the present invention.

[0031]

As described above, according to the present invention, a dedicated buffer having a plurality of delay characteristics is registered in the CAD system in advance, and a delay simulation is first performed when the layout of internal blocks is completed. The optimum buffer for each signal line is selected from the registered buffers based on the delay simulation result, and then the outer peripheral block and the internal block including the selected optimum buffer are arranged,
LS that guarantees the desired delay characteristics by wiring
It enables the design of I, and can reduce the chip area and the development period as compared with the conventional method. Further, according to the present invention, the propagation delay time between the plurality of input / output buffers in the semiconductor integrated circuit is made uniform, and the skew between the respective signals in the signal paths of the internal circuit, the buffer, and the external input / output terminals (pins). Can be minimized.

[Brief description of drawings]

FIG. 1 is a flow chart illustrating an embodiment of the present invention.

FIG. 2 is a flowchart illustrating a layout of a conventional integrated circuit chip.

[Explanation of symbols]

 100 to 109, 200 to 206 steps

Claims (4)

[Claims] 1. A first delay characteristic analysis is performed on the internal block after laying out an internal circuit except an input / output buffer of a semiconductor integrated circuit, and is registered in advance based on a result of the first delay characteristic analysis. A buffer having an optimum delay characteristic is selected from the input / output buffers, the internal circuit and the input / output buffer are laid out using the selected buffer, and the internal circuit and the input / output buffer are laid out. A method of designing a semiconductor integrated circuit, comprising: performing a second delay characteristic analysis on a chip including and verifying whether a required characteristic is satisfied based on a result of the second delay characteristic analysis. 2. A plurality of input / output buffers of the same type having different delay times are registered in advance as macroblocks, and the layout process is divided into two steps. In the layout step of the first step, automatic placement / wiring is performed. After arranging and wiring the internal circuit except the input / output buffer by the CAD system,
Of the input / output buffers registered in advance based on the result of the first delay simulation, and selects a buffer having an optimum delay characteristic from the result of the first delay simulation. The automatic placement
A wiring CAD system is used to perform arrangement and wiring between the internal circuit and the input / output buffer using the selected buffer, and a signal path of a chip including the arranged and wired internal circuit and the input / output buffer. A method of designing a semiconductor integrated circuit, comprising: executing a second delay simulation, and confirming whether or not required characteristics are satisfied based on a result of the second simulation. 3. In the layout process of the first stage, if the result of the first delay simulation does not satisfy a predetermined required characteristic, the layout of the internal circuit except the input / output buffer is re-arranged. 3. The semiconductor integrated circuit design method according to claim 2, wherein the first delay simulation is performed after the simulation. 4. As a result of the second simulation, when the predetermined required characteristics are not satisfied, the arrangement and wiring between the internal circuit and the input / output buffer are performed again. Item 2. A semiconductor integrated circuit design method according to item 2.