JPH06151594A - Automatic wiring design method of semiconductor integrated circuit chip - Google Patents

Abstract

PURPOSE:To briefly perform an automatic wiring design by a method wherein an alteration of a macro-cell library and a sub-wiring path using wiring data at a general wiring design are added in a clock signal line having a plurality of paths realized by a manual wiring design. CONSTITUTION:A first circuit block 11 is selected from a macro-cell library to determine a location in a peripheral region 31 of a LSI chip 30. Simultaneously, a second circuit block 12 is selected to determine a plurality of locations in a chip inside region 32. In order to transmit clock signals from the first circuit block 11 to the second circuit blocks 12 in the plurality of locations, a main wiring path 131 of a clock signal line is automatically determined as usual. Also, based on a predetermined reference considering a reduction in clock skew for this main wiring path 131, a loop part is added to automatically determine a sub-wiring path 132.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for automatically designing a wiring of a semiconductor integrated circuit chip, and more particularly to automatically arranging circuit blocks on a large scale integrated circuit (LSI) chip and wiring between circuit blocks with the aid of a computer. Regarding the device to be designed.

[0002]

2. Description of the Related Art In the automatic wiring design of an LSI, the wiring design of a signal having a large load such as a clock signal supplied to a sequential circuit is often performed. 2 is L
It is a circuit diagram which shows an example of the sequential circuit provided in SI.

Here, 11 is a clock input buffer circuit, and 12 is a flip-flop circuit having a clock input terminal CK, forming a sequential circuit. Reference numeral 13 denotes a clock signal line commonly connected from the output end of the clock input buffer circuit 11 to each clock input terminal CK of the sequential circuit, and R denotes a resistance of the clock signal line existing between the circuits. FIG. 6 shows an example of circuit layout and inter-circuit wiring when the circuit shown in FIG. 2 is designed by a conventional automatic wiring design method.

The clock input buffer circuit 11 is an LSI
Peripheral area of chip 30 (terminal row / input / output circuit area)
The group of flip-flop circuits 12 arranged in 31 and forming a sequential circuit are arranged in the chip central region (internal circuit region) 32, and the clock signal line 13 is designed as a metal wiring (for example, aluminum) having a low wiring resistance. Is normal. Here, the flow of the conventional automatic wiring design will be briefly described.

First, a circuit block (macro cell) of the clock input buffer circuit 11 and the flip-flop circuit 12
The data of is registered in the macrocell library in advance. Next, the placement of each circuit block is automatically determined with reference to the registration data of each circuit block. next,
One system is automatically determined for the wiring route between each circuit block. After that, an actual wiring pattern is automatically designed according to the layout of the circuit blocks and the wiring between the circuit blocks.

By the way, since the wiring resistance R exists in the clock signal line 13 shown in FIG. 2, a difference in signal propagation time (clock skew) occurs between the stages of each circuit of the sequential circuit. The clock skew between the first-stage circuit and the last-stage circuit increases as the wiring resistance R accumulates. If this clock skew is large, it may cause a malfunction of the sequential circuit.

However, since the conventional automatic wiring design method does not have an automatic wiring design function in consideration of reduction of clock skew, in order to reduce the wiring resistance of the clock signal path as a measure against clock skew, the automatic wiring of the LSI chip is reduced. Manual wiring design is performed in the middle of design. 7 and 8 each show an example of manual wiring design.

FIG. 7 is shown by a dotted line in order to reduce clock skew by shortening the distance from the clock input buffer circuit 11 to each flip-flop circuit 12 after the automatic wiring design as shown in FIG. A state where a manual wiring design is performed so as to add such bypass wiring 71 is shown.

In FIG. 8, the flip-flop circuits 12 are arranged at the positions by arranging the clock signal lines 13 having a large load in a grid pattern before the automatic wiring design as shown in FIG. Even so, the manual wiring design is shown to minimize the wiring resistance of the clock signal path.

However, when performing the manual wiring design as shown in FIGS. 7 and 8, it is necessary to temporarily suspend the process in the middle of the automatic wiring design of the LSI chip and perform the special wiring design by the manual work. Means that.

Therefore, it is necessary to provide the automatic wiring design device for the LSI chip with the manual wiring design function.
In addition, as an environment for performing the above-mentioned manual wiring design, it is necessary to prepare equipment such as a very expensive graphic processing device.

[0012]

As described above, the conventional LSI chip automatic wiring design method does not have an automatic wiring design function in consideration of the reduction of clock skew. There is a problem in that it is necessary to temporarily interrupt the process in the middle of design and perform special wiring design by manual work.

The present invention has been made to solve the above problems, and does not interrupt the processing temporarily during the automatic wiring design of the LSI chip, and the wiring design algorithm of the existing main program of the automatic wiring design. An object of the present invention is to provide an automatic wiring design method for a semiconductor integrated circuit chip, which enables automatic wiring design in consideration of measures against clock skew without changing the above.

[0014]

According to the present invention, data of a first circuit block to which a clock signal is input from the outside and data of a second circuit block whose operation is controlled by the clock signal is used in an automatic wiring design apparatus. The first step of pre-registering in the macrocell library, and selecting the first circuit block from the macrocell library
A second step of automatically determining the arrangement in the peripheral area of the SI chip and automatically determining the arrangement of a plurality of locations in the LSI chip internal area by selecting the second circuit block; and the first circuit. The main wiring path of the clock signal line for transmitting the clock signal from the block to the second circuit blocks at the plurality of locations is automatically determined, and the main wiring path is provided with a predetermined wiring wiring in consideration of reduction of clock skew. A third step of automatically determining a sub-wiring path so as to add a loop portion based on a standard,
A fourth step of automatically designing a wiring pattern based on the layout of the circuit blocks and the wiring path of the clock signal line determined by the above steps.

[0015]

The automatic wiring design for determining the wiring route of the clock signal line so as to have the loop portion is performed based on the predetermined standard considering the reduction of the clock skew. Therefore, the processing is performed during the automatic wiring design of the LSI chip. It can be used as it is without any interruption and without changing the wiring design algorithm of the existing main program of the automatic wiring design.

[0016]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a flowchart showing an example of an LSI chip automatic wiring design method of the present invention. Figure 2
FIG. 3 is a circuit diagram showing an example of a sequential circuit provided in an LSI.

Here, 11 is a clock input buffer circuit, and 12 is a flip-flop circuit having a clock input terminal CK, forming a sequential circuit. Reference numeral 13 denotes a clock signal line commonly connected from the output end of the clock input buffer circuit 11 to each clock input terminal CK of the sequential circuit, and R denotes a resistance of the clock signal line existing between the circuits. FIG. 3 is a diagram showing an example of an image registered as macrocell data of the clock input buffer circuit 11 in FIG. This clock input buffer circuit 1
1 has, for example, three output terminals 111 to 113, and the output terminals are electrically connected to each other. Figure 4
FIG. 3 is a diagram showing an example of an image registered as macrocell data of a flip-flop circuit 12 in FIG. 2. This flip-flop circuit 12 has, for example, three input terminals 1
21 to 123, and the input terminals are electrically connected to each other. FIG. 5 shows L realized by the method of FIG.
An example of SI pattern is shown.

Here, 30 is an LSI chip area, 31 is a chip peripheral area, 32 is a chip internal area, 11 is a clock input buffer circuit arranged in the chip peripheral area, and 12
Is a flip-flop circuit arranged in the chip internal area,
Reference numeral 131 is a main wiring path, and 132 is a sub wiring path. Next, an example of an automatic wiring design method for the sequential circuit shown in FIG. 2 will be described with reference to FIGS. 1 to 5.

In the LSI chip automatic wiring design method of the present invention, a pattern of a plurality of circuit blocks accommodating functional circuits is arranged on a layout area for creating a pattern of the LSI chip area, and the plurality of the plurality of circuit blocks are arranged. It is applied to a cell-based layout method for forming a wiring pattern between circuit blocks to realize a desired LSI pattern.

In step S1, data (macro cell) of a clock input buffer circuit (first circuit block) 11 to which a clock signal is input from the outside and a flip-flop circuit (second circuit block) 12 whose operation is controlled by the clock signal. Data) is registered in advance in the macrocell library used in the automatic wiring design device.

In this case, the first circuit block 11 has
As shown in FIG. 3, the three output terminals 111 to 113 electrically connected to each other are registered with different attributes.

Similarly, as shown in FIG. 4, the three input terminals 121 to 123 electrically connected to each other are registered in the second circuit block with different attributes.

In other words, the first circuit block 11 described above
Output terminals 111 to 113 and the second circuit block 1
The two input terminals 121 to 123 may be designed in patterns so that they can be registered at a plurality of points by point coordinates.

In step S2, the layout of each circuit block is determined with reference to the registration data of each circuit block of the macrocell library and the wiring information of each circuit block registered in the database used in the automatic wiring design apparatus. Determined automatically. That is, the first circuit block 11 is selected from the macrocell library and the LSI chip 3 is selected.
0 in the peripheral region 31 is determined, and the second circuit block 12 is selected to select the chip internal region 32.
Determine the placement of multiple locations in.

In step S3, the main wiring path 131 of the clock signal line for transmitting the clock signal from the first circuit block 11 to the plurality of second circuit blocks 12 is automatically determined as usual ( (This corresponds to the conventional schematic wiring design.) And the sub wiring path 132 is automatically determined so that a loop portion is added to the main wiring path 131 based on a predetermined standard in which reduction of clock skew is taken into consideration. .

In this case, first, the main wiring path 131 for connecting the first output terminal 111 of the first circuit block 11 and the first input terminal 121 of the plurality of second circuit blocks 12 ... decide. Then, the main wiring path 1
To form a loop with at least a portion of 31
An output terminal (112 or 113) other than the first output terminal of the first circuit block 11 and an arbitrary number of input terminals (1 other than the first input terminal of the second circuit block 12).
22 or 123) to determine the sub wiring path 132.

In this example, the first circuit block 1 is used as a reference for determining the sub wiring path 132 of the clock signal line.
The second output terminal 112 of No. 1 and the second input terminal 122 of the second circuit block 12 corresponding to the intermediate stage of the sequential circuit (nth stage in the case of 2n sequential circuits) are connected, The third output terminal 113 of the first circuit block 11 is connected to the third input terminal 123 of the second circuit block 12 corresponding to the final stage of the sequential circuit.

In step S4, a wiring pattern is automatically designed based on the layout of the circuit blocks and the wiring paths 131 and 132 of the clock signal line determined in the above steps.

According to the automatic wiring design method of the present embodiment as described above, the processing is not temporarily interrupted during the automatic wiring design of the LSI chip, and based on the predetermined standard considering the reduction of the clock skew, Automatic wiring design is performed so that the wiring path of the clock signal line has a loop portion (in other words, a plurality of wiring paths are formed for one signal).

Moreover, in the wiring design process as described above, since the same signal is actually handled as a different signal in the automatic wiring design system, the wiring design algorithm of the existing main program of the automatic wiring design is changed. It is possible to use it as it is.

As another example of the criterion for determining the sub-wiring path 132 of the clock signal line in step S3 in the above-mentioned embodiment, in the first area (for example, the left half area) in the LSI chip internal area 32, By connecting the second output terminal 112 of the first circuit block 11 and the second input terminal 122 of the second circuit block 12,
In the second region (for example, the right half region) in the I-chip internal region 32, the third output terminal 113 of the first circuit block 11 and the third input terminal 123 of the second circuit block 12 are connected. You may do it.

[0032]

As described above, according to the LSI chip automatic wiring design method of the present invention, the macro cell library is changed and the rough wiring is performed for the clock signal line having a plurality of paths, which is conventionally realized by the manual wiring design. Automatic wiring design can be easily performed only by adding a sub-wiring route using wiring information at the time of design.

Therefore, the automatic wiring in consideration of the clock skew countermeasure is performed without interrupting the process during the automatic wiring design of the LSI chip and without changing the wiring design algorithm of the main program of the existing automatic wiring design. Design becomes possible.

Further, it is not necessary to provide the automatic wiring designing device of the LSI chip with the manual wiring designing function, and it is not necessary to prepare equipment such as a very expensive graphic processing device as an environment for performing the manual wiring designing.

[Brief description of drawings]

FIG. 1 is a flowchart showing an example of an automatic wiring design method for a semiconductor integrated circuit chip according to the present invention.

FIG. 2 is a circuit diagram showing an example of a sequential circuit provided in an LSI.

FIG. 3 is a diagram showing an example of an image registered as macrocell data of the clock input buffer circuit in FIG.

4 is a diagram showing an example of an image registered as macrocell data of the flip-flop circuit in FIG.

5 is a diagram showing an example of an LSI pattern realized by the method of FIG.

FIG. 6 is a diagram showing an example of circuit layout and inter-circuit wiring designed by the conventional automatic wiring design method for the circuit shown in FIG. 2;

7 is a diagram showing an example of manual wiring design performed during the automatic wiring design by the conventional automatic wiring design method shown in FIG.

FIG. 8 is a diagram showing another example of performing manual wiring design during the automatic wiring design by the conventional automatic wiring design method shown in FIG.

[Explanation of symbols]

11 ... Clock input buffer circuit, 111-113 ... Output terminal of clock input buffer circuit, 12 ... Flip-flop circuit, 121-123 ... Input terminal of flip-flop circuit, 131 ... Main wiring path, 132 ... Sub wiring path,
30 ... LSI chip area, 31 ... Chip peripheral area, 32
… Inside chip area.

Claims (3)

[Claims] 1. Data of a first circuit block to which a clock signal is input from the outside and data of a second circuit block whose operation is controlled by the clock signal are registered in advance in a macrocell library used in an automatic wiring design apparatus. The first step is to select the first circuit block from the macrocell library to automatically determine the layout in the peripheral area of the LSI chip, and select the second circuit block to select L.
A second step of automatically determining the arrangement of a plurality of locations in the SI chip internal region; and a main step of a clock signal line for transmitting a clock signal from the first circuit block to the second circuit blocks of the plurality of locations. A third step of automatically determining the wiring route and automatically determining the sub-wiring route so that the loop portion is added to the main wiring route based on a predetermined criterion considering the reduction of the clock skew. A fourth step of automatically designing a wiring pattern based on the layout of the circuit blocks and the wiring path of the clock signal line determined by the above steps. Design method. 2. The automatic wiring design method for a semiconductor integrated circuit chip according to claim 1, wherein when the data of each circuit block is registered in the macrocell library in the first step, a plurality of first circuit blocks are included in the first circuit block. An automatic wiring design method for a semiconductor integrated circuit chip, comprising: providing an output terminal, and providing the second circuit block with a plurality of input terminals. 3. The automatic wiring design method for a semiconductor integrated circuit chip according to claim 1, wherein in the third step, the first output terminal of the first circuit block and the plurality of second output terminals are provided. Of the first circuit block so as to form a loop together with at least a part of the main wiring path of the clock signal line which is connected to the first input terminal of the first circuit block. A sub wiring path of a clock signal line connecting an output terminal other than the output terminal and an arbitrary number of input terminals other than the first input terminal of the second circuit block is determined. Automatic wiring design method.