JP2933584B2 - Semiconductor integrated circuit device and macro terminal clamp processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly, to a technique for clamping a macro terminal.

[0002]

2. Description of the Related Art The input / output terminals of a macro created by a special design are created such that the number of macro input / output terminals is normally used. However, macros created by general-purpose design have terminals that are not used (unused terminals) depending on the scale of use and application.

For example, in a large-scale macro such as a RAM (random access memory), a plurality of scales such as × 4, × 8, and × 16 are often realized by one macro layout.

In this case, since the macro is designed on the assumption that the maximum size of × 16 is used, when the macro is used as a × 4 or × 8, FIG. ", A number of unused terminals become unnecessary, and it becomes necessary to clamp these unused terminals.

Conventionally, there are two methods of clamping unused terminals: a method of processing outside a macro, which is a main stream, and another method of processing inside a macro.

As shown in FIG. 10, a method of processing outside the macro is to prepare a clamp potential supply block 61, connect the clamp potential supply block 61 to an unused terminal of the macro, and clamp it. is there. In FIG. 10, reference numeral 60 denotes a functional block; 62, a wiring;
Denotes a power ring (power wiring), and 64 denotes the inside of the macro.

FIG. 11 shows this processing flow.
Referring to FIG. 11, a process 65 for adding connection information for clamping an unused macro terminal to the circuit connection information 12 is performed, an automatic placement and routing 66 is performed based on the connection information, a wiring result output 67, an artwork The processing is performed in the order of the merge processing 68 with the data 14.

As a method of automatically clamping unused macro terminals when creating circuit connection information, reference is made to, for example, Japanese Patent Application Laid-Open Nos. 4-235678 and 4-336675.

On the other hand, as a method of processing inside a macro, there are a method of preparing macro artwork data corresponding to each scale on a one-to-one basis, and a method of adding a circuit for stabilizing the potential of an unused terminal. is there.

As shown in FIG. 12, a wiring block directly connected to the high potential side or the low potential side from the vicinity of the macro terminal is prepared, and the processing block shown in FIG. 13 is used. And clamp it. FIG.
In 2, 63 is a power ring, 64 is inside the macro, 7
0 indicates a clamp pattern, and 71 indicates a macro internal wiring.
Referring to FIG. 13, circuit connection information 12 is input, and information for clamping an unused macro terminal with a wiring block is added in circuit connection information creation processing 73, and the circuit connection information to which the clamp information has been added, the wiring block pattern, Automatic placement and routing 74 is performed from the automatic placement and routing database 72 to which the placement coordinates have been added, and the artwork data 14
, A merge process 76 with the wiring result output 75 is performed.

[0011] For example, Japanese Patent Application Laid-Open No. 63-258041 discloses a technique for performing a clamping process by automatic wiring, and Japanese Patent Application Laid-Open No. 61-22648 and Japanese Patent Application Laid-Open No.
Japanese Patent Application Publication No. 22649 and the like disclose a technique in which a clamp potential supply block and a clamp power supply wiring are added in a macro at the time of macro configuration to make the macro configuration easy to clamp.

[0012]

However, these prior arts have the following problems.

The first problem in processing outside the macro is that the size of the chip increases.

The reason is that the required number of clamp potential supply blocks is arranged, so that the number of functional blocks that must be mounted decreases, and as a result, the chip size increases in order to increase the number of arrangements. Because you have to do it.

The second problem is that the wiring property is deteriorated.

The reason is that, similarly to the wiring of the mounted functional block, by wiring the macro input terminal to be clamped and the block for supplying the clamp potential, the number of wiring grids of the functional block is reduced. It is because it causes.

A third problem is that in the case of a mixed technology using different power supplies for the macro and the clamp potential supply block, they cannot be connected to the clamp potential supply block.

The reason is that the clamping process is to keep the operation of the clamped circuit constant by connecting to a high potential power supply or a low potential power supply. At this time, for example, when the high potential side of the macro is +5.0 V and the high potential side of the clamp potential supply block is +2.5 V,
Since a potential difference of 2.5 V is generated, the macro circuit cannot be clamped at all, and may cause a malfunction.

Next, the problem in the case of processing inside a macro will be described. The first problem is that the number of data of the macro increases.

The reason is that if macro artwork data corresponding to each scale is prepared on a one-to-one basis, the basic functions are the same, but only the number of terminals used is different.
This is because a large number of macro data having different macro names exist, and data management becomes complicated.

The second problem is that the macro size increases.

The reason is that since a circuit for stabilizing the potential of the unused terminal is formed in the macro, an extra component must be added to the macro. Due to this effect, the chip size may be increased.

A third problem is that the data amount of the macro increases.

The reason is that in the case of a gate array, high-potential and low-potential wirings are regularly arranged on the cell array, and the terminals of the functional blocks arranged on the cell array can be easily clamped. However, in the case of a memory macro, the high-potential and low-potential lines are irregular, so that wiring blocks for the number of terminals must be prepared. Furthermore, it is necessary to describe the wiring block coordinates and wiring block pattern names for the number of terminals in the automatic arrangement and wiring database, and the amount is three times the data amount of a normal terminal description.

Accordingly, the present invention has been made in view of the above problems, and has as its object to prevent an increase in chip size and deterioration of wiring properties, and to use different power supplies for the macro and clamp potential supply blocks. An object of the present invention is to provide a macro configuration and a clamp processing method that can cope with mixed mounting technology. Another object of the present invention is to provide a macro configuration and a clamp processing method for avoiding an increase in the number of macro data and an increase in macro size.

[0026]

In order to achieve the above-mentioned object, the present invention provides a macro input / output terminal (hereinafter referred to as "macro terminal") mounted on a semiconductor integrated circuit.
Clamping is performed on both the high potential side and the low potential side in the macro in the automatic placement and routing database, and the macro terminal is used by using the macro terminal information including the macro name, all terminal names, terminal clamp information, and circuit connection information. if Y / N of the clamp, distribution by performing clamping of unused pins by removing one of the clamping pattern or both of the clamp pattern having a high potential side and the low potential side within the macro
It is characterized in that data of a placement and routing result is obtained .

According to the present invention, (a) the use, unused, and clamp potential of each macro terminal are determined by using macro terminal information in which macro names, all terminal names, terminal clamp information are described, and circuit connection information. Determining; (b) changing a terminal definition not used in the automatic placement and routing database to routing prohibition data; and (c) performing automatic placement and routing using the changed automatic placement and routing database; (D)
Performing a merge result with the wiring result output of the automatic placement and routing process and the artwork data, and deleting a clamp pattern from the data after the merge process.

[0028]

Embodiments of the present invention will be described below. According to the present invention, the input / output terminals of the macro mounted on the semiconductor
Using the circuit connection information and the macro terminal information created from the existing data, all or one of the macro terminals is removed from the clamped pattern on the (high potential power supply) side and the GND (low potential power supply) side. By performing the process, the clamp process of the unused terminal is accurately performed.

Referring to FIG. 1A, macro terminals 1 and 2
2, 3 and 4 are clamped on the macro internal wiring 7 on both the VDD (high-potential power supply) side and the GND (low-potential power supply) side in the macro. The pattern cell name to be clamped is defined corresponding to each macro terminal. In FIG. 1, reference numeral 5 denotes a VDD-side clamp pattern, 6 denotes a GND-side clamp pattern, and 7 denotes a macro internal wiring.

FIG. 1B is a diagram showing an example of a macro terminal clamp arrangement after the clamping process. FIG.
Referring to (b), since the macro terminal 1 does not require clamping, both the VDD and GND patterns are deleted, and the macro terminal 2 is clamped to the GND side.
Side pattern is deleted, the macro terminal 3 is clamped to the VDD side and the GND side pattern is deleted, and the macro terminal 4 is not required to be clamped to VDD and GN.
D Both patterns have been deleted. In the figure, the symbol x indicates that the pattern has been deleted.

FIG. 2 is a diagram showing a processing flow of the clamp processing in the embodiment of the present invention. Referring to FIG. 2, using macro terminal information 11 in which a macro name, all terminal names, and terminal clamp information are described, and circuit connection information 12,
A process 15 for determining the use, unused, and clamp potential of each macro terminal is performed, and a process 16 for changing the unused terminal definition to the wiring prohibition data in the automatic placement and routing database 13 is performed.

Thereafter, the automatic placement and routing 17 is performed using the changed automatic placement and routing database.

After the automatic placement and routing 17 is completed, the wiring result output 1
8. A merge process 19 is performed with the artwork data 14, a process 20 for deleting the clamp pattern from the data after the merge process is performed, and all the processes are completed. As a result, the unused terminal can be clamped accurately.

[0034]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

FIG. 1A is a diagram showing a macro terminal clamp arrangement according to an embodiment of the present invention. Referring to FIG. 1A, macro terminals 1, 2, 3, and 4 are each connected to VDD.
(High potential) side clamp pattern 5 and GND (low potential)
It is clamped on the internal wiring 7 by the side clamp pattern 6. All macro terminals are connected to the VDD (high potential) side and GND until immediately before the execution of the clamp processing flow of the present invention.
Both (low potential) sides are clamped on the macro internal wiring 7.

In one embodiment of the present invention, the cell names when the VDD (high-potential) side clamp pattern 5 and the GND (low-potential) side clamp pattern 6 are arranged have a one-to-one correspondence with each macro terminal. I have.

FIG. 2 is a diagram showing a clamp processing flow in one embodiment of the present invention.

Referring to FIG. 2, macro names, all terminal names,
Macro terminal information 11 in which terminal clamp information is described;
Processing 1 for determining, using the circuit connection information 12, whether each macro terminal requires no clamping, needs clamping, and if necessary, is on the VDD (high potential) side or the GND (low potential) side.
5, the processing 16 for changing the unused terminal definition to the wiring prohibition definition is performed on the automatic placement and routing database 13.

Thereafter, the automatic placement and routing 17 is performed using the changed automatic placement and routing database. After the automatic placement and routing, from the data obtained by performing the merge processing 19 with the wiring result output 18 and the artwork data 14, if the clamp processing is unnecessary, all the clamp patterns of the terminals are deleted and the clamp processing is required. If the potential is on the VDD (high potential) side, the pattern that clamps the GND (low potential) side of the terminal needs to be deleted and a clamping process is required. If the potential is on the GND (low potential) side, Performs a clamp pattern deletion process 20 for deleting the pattern clamping the VDD (high potential) side of the terminal, and ends all the processes.

Next, an embodiment of the present invention will be described in more detail.

FIG. 1 is a diagram showing an example of a macro terminal clamp arrangement according to an embodiment of the present invention. Macro terminal 1,
2, 3, and 4 are clamped on the macro internal wiring 7 by a VDD (high potential) side clamp pattern 5 and a GND (low potential) side clamp pattern 6, respectively. All the macro terminals are clamped on the macro internal wiring 7 on both the VDD (high potential) side and the GND (low potential) side until immediately before the execution of the clamp processing flow.

By the way, when the VDD (high-potential) side clamp pattern 5 and the GND (low-potential) side clamp pattern 6 are arranged, the cell name is one to one for each macro terminal.
Yes, it is. For example, the terminal name of the macro terminal 1 is "H0
1 "and the terminal name of the macro terminal 2 is" H02 ",
The VDD (high potential) side clamp pattern cell names are "VDDH01" and "VDDH02", and the GND (low potential) side clamp pattern cell names are "GNDH01".
It is defined by the name of the macro terminal and the name of the cell whose clamp potential is known, such as “GNDH02”.

By defining in this way, it is possible to perform the clamping process without referring to the correspondence table between the macro terminal and the clamp pattern cell name, and also to reduce the processing load and the time required for the reference. I can do it.

FIG. 2 is a diagram showing a basic flow of the clamping process according to one embodiment of the present invention, and FIGS. 3 to 5 are diagrams showing a detailed flow of the clamping process according to one embodiment of the present invention. It is. First, a method of a clamping process according to an embodiment of the present invention will be described with reference to FIG.

Referring to FIG. 2, macro names, all terminal names,
Using the macro terminal information 11 in which the terminal clamp information is described and the circuit connection information 12, the usage status of each macro terminal,
A process 15 is performed to determine whether the clamp is unnecessary, whether the clamp is necessary, and if the clamp is necessary, whether the potential is the high potential side or the low potential side.
A process 16 of changing the unused terminal definition to the wiring prohibition definition is performed on the automatic placement and routing database 13. Thereafter, the automatic placement and routing 17 is performed using the changed automatic placement and routing database. After the automatic placement and routing is completed, the merging process 1 of the wiring result output 18 and the artwork data 14
From the data obtained by performing step 9, if the clamp processing is unnecessary, all the clamp patterns of the terminal are deleted, and the clamp processing is required. When the potential is on the VDD (high potential) side, the GND (low) of the terminal is used. The pattern clamping the potential) side is deleted, and a clamping process is required, and the potential is G
In the case of the ND (low potential) side, a process 20 for deleting the pattern clamping the VDD (high potential) side of the terminal 20
Is performed, and all the processing ends.

As shown in FIG. 6, the macro terminal information 11 including the macro name, all terminal names, and terminal clamp information includes an automatic placement and routing database 13, circuit information 22 of each block, a block name to be clamped, and the like. Clamp potential 2
3 is created by performing processing 49 for searching for macro name, terminal information, and clamp information.

Referring to FIGS. 3 to 5, the clamping process according to one embodiment of the present invention will be described. As a specific example of adaptation, as shown in FIG. 8, the macro name is “MACRO”, the number of input terminals for maximum use is “5” terminals, the terminal names are “H01” to “H05”, and the output terminals are Number of "5"
The terminals and their terminal names are “N01” to “N05”. In the case of using the smallest scale, the number of input / output terminals used is “3” terminals, the terminal names “H01” to “H03”, and the terminal name “N01”.
To "N03", the unused input terminal "H04" is clamped to the VDD (high potential) side and "H05" is clamped to the GND (low potential) side.

In FIG. 3 to FIG. 5, macro terminal information 11 in which a macro name, all terminal names, and terminal clamp information are described.
Is the macro name MACR according to the creation flow shown in FIG.
O, all terminal names H01 to H05, N01 to N05, and clamp information are described as VDD for H04 and GND for H05.

In the circuit connection information 12, unused input / output terminals H04, H05, N04 and N05 are not connected.

First, the macro terminal information 11 and the circuit connection information 12 in which the macro name, all terminal names, and terminal clamp information are described are read (step 24 in FIG. 3).

Next, in step 25 (see FIG. 3), it is determined whether the terminal to be clamped is not connected in the circuit connection information.
Terminal information and circuit connection information 12 of the macro terminal information in which the read macro name, all terminal names, and terminal clamp information are described.
Confirm that the unused terminals of the two match.

In this example, H04, H05, N04,
N05 is not connected.

Here, when a mismatch occurs, the macro name,
The macro terminal information 11 or the circuit connection information 12 in which the names of all the terminals and the terminal clamp information are described is output as having a description error, and the process ends (step 26 in FIG. 3).

When the terminal information of the macro terminal information 11 in which the macro name, all terminal names, and terminal clamp information are described and the unused terminal of the circuit connection information 12 match, the used terminal, the unused terminal, and the unused terminal are determined. In the case of the used terminal, it is determined whether the clamp is unnecessary, the clamp is necessary, and if necessary, the VDD (high potential) side or the GND (low potential) side is determined (Step 2 in FIG. 3)
7).

In this example, H01-H03, N01-
N05 does not require clamping, H04 is VDD (high potential)
Side H05 is clamped to the GND (low potential) side.

Next, the automatic placement and routing database is read (step 28 in FIG. 4), and the macro name described in the macro terminal information 11 in which the macro name, all terminal names, and terminal clamp information are described (FIG. 4). 4, step 29), and read the terminal of the corresponding macro (step 30 in FIG. 4).

Further, it is determined whether or not the read terminal is a used terminal (step 32 in FIG. 4). If it is a used terminal, the next terminal is read without changing the terminal definition in the automatic placement and routing database. Determines whether the terminal is an unused terminal (step 33 in FIG. 4), and if it is an unused terminal, changes the terminal definition in the automatic placement and routing database to a wiring prohibition definition (step 34 in FIG. 4). If neither of them is applicable, an error is described in the automatic placement and routing database, and the process is terminated (step 3 in FIG. 4).
5).

In this example, H04, H05, N04,
The terminal definition of the automatic placement and routing database of N05 is changed to the wiring prohibition definition.

Next, automatic placement and routing are performed (step 36 in FIG. 4), and after completion of the wiring, a wiring result is output (step 37 in FIG. 4), and a merge process with the artwork data 14 is performed (FIG. 5). Step 38). The processing of these steps 36 to 38 is not different from the processing steps of a normal master slice type semiconductor integrated circuit device.

Next, a clamp cell is read from the merged data (step 39 in FIG. 5), and it is determined whether or not the read clamp cell does not need to be clamped at a used terminal or an unused terminal (FIG. 5). Step 4 of
1) If applicable, delete all the cell arrangement information of the clamp cell (step 42 in FIG. 5);
It is determined whether or not the clamp potential of the unused terminal is on the VDD (high potential) side (step 43 in FIG. 5). If this is the case, the cell information on the GND (low potential) side of the corresponding cell is deleted (FIG. 5). Step 44), if not applicable, it is necessary to clamp the unused terminal and it is determined whether or not the clamp potential is on the GND (low potential) side (Step 45 in FIG. 5). The cell information on the (high potential) side is deleted (step 46 in FIG. 5). If none of the above applies, the artwork data is output as incorrect and the process is terminated (step 47 in FIG. 5). This process is repeated until there is no more data to be read.

In this example, H01-H03, N01-
Since N03 is a used terminal, all clamp cell information is deleted, and H04 is clamped on the VDD (high potential) side, so that clamp cell information on the GND (low potential) side is deleted.
5 is clamped to the GND (low potential) side, so that VDD
The (high potential) side clamp cell information is deleted.

Next, another embodiment of the present invention will be described. FIG. 7 is a diagram showing a clamping process according to the second embodiment of the present invention.

Referring to FIG. 7, in the second embodiment of the present invention, a process 15 for determining whether a terminal is used or unused and a clamp potential in the embodiment shown in FIG. A process 50 for adding the clamp information (potential) of the unused terminal to the process 16 for changing to data, and a circuit connection information 51 with the clamp information added between the clamp pattern deletion process 20 and the end 21. For reference, a comparison verification process 52 of the layout and the circuit connection information is provided.

In this embodiment, by adding a process of automatically adding the potential of the unused terminal to the circuit connection information, the connection verification between the artwork data after the clamping process and the circuit connection information can be smoothly performed without error. .

[0065]

As described above, according to the present invention, the following effects can be obtained.

A first effect of the present invention is that the chip size can be prevented from being increased due to the arrangement of the clamp potential supply block.

The reason is that, in the present invention, the clamping process is performed in the macro, so that the clamp potential supply block is not required.

A second effect of the present invention is that it is possible to prevent the wiring property from being deteriorated due to the wiring between the clamp potential supply block and the macro terminal.

The reason is that, in the present invention, since the clamping process is performed in the macro, the connection with the clamp potential supply block becomes unnecessary, and the wiring grid increases accordingly.
This is because the wiring property is improved.

A third effect of the present invention is that it is possible to cope with a mixed technology in which the power supply used for the macro and the clamp potential supply blocks is different.

The reason is that, in the present invention, the clamping process is performed by the power supply in the macro.

A fourth effect of the present invention is that one macro layout can handle a plurality of scales.

The reason is that, in the present invention, the clamping process is performed by judging from the macro name, all terminal names, terminal clamp information, and circuit connection information.

A fifth effect of the present invention is that the macro size can be reduced.

The reason for this is that, in the present invention, since the clamp processing is performed by the clamp pattern, a clamp processing circuit for stabilizing the electric potential in the macro becomes unnecessary, and an area corresponding to this need not be secured. is there.

A sixth effect of the present invention is that the amount of macro data is not increased.

The reason is that, in the present invention, since the layout switching of the wiring block pattern is not performed by using the automatic layout and wiring tool, the definition necessary for the layout switching is additionally described in the terminal definition of the automatic layout and wiring database. Is unnecessary, and the data amount is not increased accordingly.

[Brief description of the drawings]

FIG. 1A shows a macro terminal clamp arrangement according to a basic embodiment of the present invention. (B) is a diagram showing an arrangement after deleting a macro terminal clamp pattern according to a basic embodiment of the present invention.

FIG. 2 is a diagram showing a flow of a clamp processing method according to an embodiment of the present invention.

FIG. 3 is a diagram showing a flow of a clamp processing method according to an embodiment of the present invention.

FIG. 4 is a diagram showing a flow of a clamp processing method according to an embodiment of the present invention.

FIG. 5 is a diagram showing a flow of a clamp processing method according to an embodiment of the present invention.

FIG. 6 is a diagram showing a flow of creating macro terminal information describing macro names, all terminal names, and terminal clamp information used in one embodiment of the present invention.

FIG. 7 is a diagram showing a flow of a clamp processing method according to another embodiment of the present invention.

FIG. 8 is a diagram illustrating a macro name, a use terminal, and a clamp potential according to a use scale according to an embodiment of the present invention.

FIG. 9 is a diagram showing used terminals on a macro scale according to a conventional technique.

FIG. 10 is a diagram showing a macro connection according to a conventional technique.

FIG. 11 is a diagram showing a flow of a macro terminal clamping processing method according to a conventional technique.

FIG. 12 is a diagram showing a macro connection according to the related art.

FIG. 13 is a diagram showing a flow of a conventional macro terminal clamping method.

[Explanation of symbols]

 1-4 Macro terminal 5 VDD (high potential) side clamp pattern 6 GND (low potential) side clamp pattern 7 Macro internal wiring 60 Function block 61 Clamp potential supply block 62 Wiring 63 Power ring 64 Macro inside 70 Clamp pattern 71 Macro inside wiring

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-4-235678 (JP, A) JP-A-4-336675 (JP, A) JP-A-4-165646 (JP, A) JP-A-63- 258041 (JP, A) JP-A-62-104137 (JP, A) JP-A-61-22648 (JP, A) JP-A-61-22649 (JP, A) (58) Fields investigated (Int. ⁶ , DB name) H01L 21/82 G06F 17/50 H01L 21/822 H01L 27/04

Claims (8)

(57) [Claims] An input / output terminal of a macro mounted on a semiconductor integrated circuit (referred to as a "macro terminal") is automatically set in advance.
Clamping is performed on both the high potential side and the low potential side in the macro in the dynamic placement and routing database, and the macro terminal is used by using macro terminal information including macro name, all terminal names, terminal clamp information and circuit connection information. if Y / N of the clamp, distribution by performing clamping of unused pins by removing one of the clamping pattern or both of the clamp pattern having a high potential side and the low potential side within the macro
A method of clamping a macro terminal, comprising obtaining data of a wiring result . (A) determining the use, unused, and clamp potential of each macro terminal using macro terminal information including macro names, all terminal names, terminal clamp information, and circuit connection information; (B) a step of changing a terminal definition that is not used in the automatic placement and routing database to routing prohibition data; (c) a step of performing automatic placement and routing using the changed automatic placement and routing database; Performing a merge process between the wiring result output of the placement and routing process and the artwork data, and deleting a clamp pattern from the data after the merge process, wherein the clamp pattern in the macro is deleted to be unused. A method of clamping a macro terminal, comprising clamping a terminal. 3. The macro terminal according to claim 1, wherein all of the macro terminals are clamped on the macro internal wiring to both the high potential side and the low potential side by a high potential side clamp pattern and a low potential side clamp pattern, respectively. 3. The method of claim 2, wherein the macro terminal is clamped. 4. A cell name when a high-potential-side clamp pattern and a low-potential-side clamp pattern are arranged has a one-to-one correspondence with each macro terminal, and a macro terminal name and a cell name for which its clamp potential is known. 3. The macro terminal clamping method according to claim 2, wherein: 5. A macro circuit mounted on a semiconductor integrated circuit, wherein a macro terminal is provided with automatic placement and wiring data in advance.
A macro circuit including a macro clamped to a high-potential-side power supply and a low-potential power supply by a clamp pattern in the macro in a base . 6. The macro circuit according to claim 5, wherein a clamp potential is determined when the terminal is used, unused, and unused, and the clamp pattern of each macro is deleted. 7. The macro circuit according to claim 5, wherein said clamp pattern is defined as a cell name corresponding to each macro terminal. 8. A macro database which stores macro terminal information including macro names, all terminal names, and terminal clamp information, wherein the macro terminals are clamped in advance by a clamp pattern to a high-potential power supply and a low-potential power supply in the macro. Means for determining the use, unused, and clamp potential of each macro terminal using the macro terminal information and the circuit connection information; and defining the unused terminal definitions for the automatic placement and routing database in the wiring prohibition data. Means for performing automatic placement and routing using the changed automatic placement and routing database; performing a merge process between the wiring result output of the automatic placement and routing process and the artwork data; Means for deleting the clamp pattern in a macro;
And a clamp process for unused terminals by deleting the clamp pattern in the macro.