JP3130891B2 - Wiring method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a wiring method for a semiconductor integrated circuit.

[0002]

2. Description of the Related Art JP-A-63-187647 discloses that
A master slice type semiconductor integrated circuit is disclosed, and Japanese Unexamined Patent Publication No. 9-199598 discloses an automatic placement and routing method for layout design.

[0003] Recent LSIs (large-scale integrated ci
rcuit) With the remarkable progress of miniaturization of the manufacturing process,
The integration scale of LSI chips is increasing year by year, and it is necessary to mount one or more large-scale function cells (hereinafter, referred to as macro cells) on one LSI chip.

FIG. 15 shows a layout pattern of such an LSI chip 55. This L
When the macro cell 60 is arranged on the SI chip 55,
The macro cell 60 is a DRAM (dynamic random access
In a block such as a memory) and a PLL (phase locked loop), a power supply line 57 dedicated to a macro cell separated from a digital power supply is required.

The macro cell 60 is arranged on the LSI chip 55 by an inverter (NAND) or a NAND (input NAND) arranged in an IO (input-output) area 58 or an internal area 59 which is advantageous in terms of power supply from an external pad 56. , NOR, etc. are arranged in the internal region 59 for the purpose of speeding up signal transmission to cells having basic functions such as NOR (referred to as basic cells).

One of the problems when the macrocell 60 is arranged in the IO region 58 is that the number of connections between the terminals 51 and the external pads 56 of the macrocell 60 is small and the size of the macrocell 60 is, for example, 30% of the internal region 59. External pad 5
The usable number of 6 is extremely reduced.

For this reason, in order not to reduce the number of usable external pads 56, the macro cell 60 is arranged in the internal region 59, and the width of the wiring connecting the external pad 56 and the power supply wiring 57 of the macro cell 60 depends on the potential drop. In order to avoid a drop in power supply voltage, it is necessary to connect with thick wiring.

On the other hand, due to the increase in the circuit scale of the LSI chip 55, it is practically impossible to manually perform layout design, and an automatic placement and routing tool is indispensable for the design.

However, in the current wiring method using the automatic placement and routing tool, a wiring layer and a wiring direction to be wired by the tool are defined in advance as a library of tools, and the rules are followed and executed.

[0010] For this reason, unless the designer considers the specifications and restrictions of the tool in advance and sets the optimal parameters in the automatic placement and routing tool, dead space or unwiring that cannot be arranged in the LSI chip 55 occurs.

The wiring used in the basic cell used in the automatic placement and routing tool is typically a second-layer metal wiring which is a second-layer aluminum wiring (hereinafter, the second-layer aluminum is abbreviated as 2AL). Is used, the number of wiring channels of the second-layer metal wiring (2AL wiring) passing over the basic cell is reduced, or, typically,
Layer aluminum wiring (hereinafter, the first layer aluminum
AL), the resistance of the through hole connecting the first layer metal wiring and the second layer metal wiring (2AL wiring) is several tens times larger than the resistance of the metal wiring. This is a factor that degrades the characteristics. For this reason, the second layer metal wiring (2AL wiring) is generally not used as much as possible in the basic cell.

Therefore, the wiring used in the basic cell is mainly the first-layer aluminum wiring (1AL wiring), and the wiring connection between the basic cells by the automatic placement and routing tool is necessarily the second-layer aluminum wiring (2AL wiring). ) Alternatively, metal wiring of a layer higher than the second layer is mainly used.

[0013]

Next, various conventional power supply wiring methods and problems of the macro cell will be described in detail.

Referring to FIG. 16, there is shown a flowchart of a first conventional power supply wiring method for a macro cell.
In FIG. 16, before arranging the basic cell (10) (step 3), the macro cell is laid out (step 1), and the power supply wiring is widened (step 39). (Step 41), the placement prohibition is set (Step 41) so that the basic cell cannot be placed under the power supply wiring.

FIG. 17 shows that the wiring layers of the LSI chip are a first layer aluminum wiring (1AL wiring), a second layer aluminum wiring (2AL wiring), and a third layer aluminum wiring (3AL wiring).
FIG. 16 is a layout diagram in which the flowchart of FIG. 16 is applied to the power supply wiring of the macro cell when the wiring direction of the automatic arrangement wiring is 1AL and 2AL in the X direction and 3AL in the Y direction. It is.

The problem in this case is that the power supply wiring 45 for connecting the power supply terminal 51 of the macro cell and the power supply terminal 44 of the power supply block 43 of the interface block is 2AL wiring based on the wiring direction of the automatic placement and routing tool. Wiring will be performed.

Therefore, a basic cell having a 2AL wiring physically cannot be arranged below the power supply wiring 45.

Further, even in a basic cell having no 2AL wiring, the 1AL terminal in the basic cell and the 3AL wiring wired by the automatic placement and wiring tool are obstructed by the 2AL wiring of the power supply wiring 45, and wiring connection is impossible.

For the above reasons, even if the basic cell 10 is arranged under the power supply wiring 45, it is impossible to short-circuit the wiring or connect the wiring to the terminal in the basic cell. The arrangement prohibition must be prohibited by setting the arrangement prohibition (step 41) so that the arrangement cannot be performed under.

Referring to FIG. 18, there is shown a flowchart of a second conventional power supply wiring method for a macro cell.

The major difference between the method of FIG. 18 and the method of FIG. 16 is that the power supply wiring is wired in a narrow slit shape (step 42).

FIG. 19 is a layout diagram after the power supply wiring of the macro cell is performed by using the method of FIG.

The difference between the layout of FIG. 19 and the layout of FIG. 17 is that the power supply wiring 54 is wired in a narrow slit shape so as to avoid the 1AL terminal 49 of the basic cell and the 2AL wiring 50 in the basic cell. Is a point. Also, the first
In addition to the conventional method, not only the wiring connection between the 1AL terminal 49 of the basic cell and the 2AL wiring or 3AL wiring wired by the automatic placement and routing tool is possible,
Further, the 2AL wiring 50 in the basic cell has a shape that does not cause a short circuit with the 2AL power supply wiring 54.

However, in order to make the wiring resistance of the power supply wiring 54 equal to or less than that of the first conventional method, the size of the power supply terminal 51 of the macrocell or the length L2 of the power supply terminal 44 of the power supply block of the interface block must be changed. FIG.
In this case, it is necessary to increase the length of the power supply terminal 44 more than necessary as compared with the length L1 of the power supply terminal 44.

Therefore, an object of the present invention is to provide a power supply terminal (5
For example, when the large-scale function cell (macro cell) (60) having (1) is arranged in the internal area (59) of the LSI chip 55 as shown in FIG.
0) and a power supply terminal of the power supply block of the interface block (43). In addition, under the power supply wiring of the macro cell (60), basic functions such as an inverter, NAND, and NOR are provided. It is an object of the present invention to provide a power supply wiring method capable of arranging and wiring cells (basic cells) having the following.

[0026]

According to the present invention, as shown in FIG. 15, a large-scale functional cell having a power supply terminal (51) is provided in an internal area (59) of an LSI chip (55). ), The power supply wiring of the power supply terminal (51) of the macro cell (60) and the power supply terminal of the power supply block (43) of the interface block is realized, and the basic wiring is provided under the power supply wiring of the macro cell (60). A wiring method for arranging and arranging basic cells having a function, wherein after arranging a macro cell (step 1), arranging the basic cell (step 3), and after arranging the basic cell, powering the macro cell (60) Depending on the conditions at the time of setting the wiring layer (step 4), the basic cell under the power supply wiring is
By replacing either the basic cell (12) with the layer metal wiring or the basic cell (15) with the third layer metal wiring, the arrangement and wiring of the power supply wiring of the macro cell (60) and the basic cell under the power supply wiring are changed. In the above-described wiring method, the basic cell (12) having the second-layer metal wiring and the basic cell (15) having the third-layer metal wiring, which are the basic cells for replacement, are the power supply which is the basic cell before replacement. It has the same logical function as the basic cell under the wiring, and can perform wiring (52 in FIG. 3) to the terminal (49 in FIGS. 6, 7, 8, and 3) of the replacement basic cell. For this purpose, a wiring method is provided in which a power supply wiring portion on the terminal of the replacement basic cell is opened.

[0027]

According to the present invention, a basic cell (12) having a second-layer metal wiring and a basic cell (15) having a third-layer metal wiring are prepared in advance as shown in FIG. Depending on the conditions at the time of setting the power supply wiring layer of the macro cell (60) (step 4), the basic cell under the power supply wiring is replaced with a basic cell (12) having a second layer metal wiring and a third layer metallization. A wiring method characterized by replacing with any one of the basic cells (15) having a wiring is obtained.

Further according to the present invention, as shown in FIG.
Setting of power supply wiring layer of macro cell (60) (Step 4)
According to the condition at the time of the above, the basic cell (12) having the second-layer metal wiring and the third
One of the basic cells (15) having the layer metal wiring is automatically generated, and the basic cell under the power wiring is automatically generated according to the conditions at the time of setting the power wiring layer of the macro cell (60) (step 4). In addition, a basic cell (12) having a second-layer metal wiring and a basic cell (1
A wiring method characterized by substituting with any of the above 5) is obtained.

Preferably, in the step of automatically generating, the cell size of the basic cell, the terminal shape of the basic cell, and the terminal layer of the terminal of the basic cell are extracted as extraction data from the library of the basic cell (10). By performing a logical operation on the extracted data based on the prepared design rule file, a basic cell (12) having a second-layer metal wiring and a basic cell (15) having a third-layer metal wiring
Is a step of automatically generating any of the above.

According to the present invention, there is provided an automatic placement and routing tool having an algorithm for achieving the above-described routing method.

Further, according to the present invention, when a large-scale function cell having a power supply terminal (51) is arranged as a macro cell (60) in an internal area (59) of an LSI chip (55), A power supply wiring between a power supply terminal (51) and a power supply terminal of a power supply block (43) of an interface block is realized, and a basic cell having a basic function can be arranged and wired under a power supply wiring of a macro cell (60). In the wiring method, the basic cell arrangement (step 3) is performed after the macro cell arrangement (step 1) is performed, and after the basic cell arrangement, the condition for setting the power supply wiring layer of the macro cell (60) (step 4) is determined. A basic cell under a power supply wiring, a basic cell having a second-layer metal wiring (12).
In the above-described wiring method, the power supply wiring of the macro cell (60) and the basic cell under the power supply wiring can be arranged and wired by replacing the power supply wiring with any one of the basic cells (15) having the third-layer metal wiring. As shown in the table, the cell name of the basic cell to be arranged under the power supply wiring and the terminal names and terminal coordinates of the terminals of the basic cell are extracted and prepared in advance as a table, and from the wiring direction of the power supply wiring and the table, By arranging the terminals of the basic cells so as to be aligned on the same coordinate axis, a wiring method characterized by minimizing the wiring resistance of the power supply wiring is obtained.

As described above, the basic cell (12) having the second-layer metal wiring and the basic cell (15) having the third-layer metal wiring need to be prepared in advance in FIG. 9, the basic cell (1) is selected according to the conditions for setting the wiring layer (step 4).
Automatic generation is also possible from the library of 0).

In addition, by arranging the basic cells under the power supply wiring based on the flowchart of FIG. 10, the wiring resistance of the power supply wiring can be minimized.

Further, adding the present wiring method to the algorithm of the existing automatic placement and routing tool can be performed without largely changing the placement and routing algorithm of the existing placement and routing tool.

[0036]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 1, there is shown a wiring method for a semiconductor integrated circuit according to a first embodiment of the present invention. In this wiring method, first, after arranging the macro cells on the LSI chip (step 1), the power supply wiring area of the macro cells is set (step 2), and the basic cells are arranged (step 3).

Next, the wiring layer of the power supply wiring of the macro cell is set (step 4), and the name of the basic cell under the power supply wiring area is extracted (step 5). Thereafter, a basic cell 12 having a second-layer metal wiring (hereinafter referred to as a basic cell with 2AL dummy wiring) and a basic cell 15 having a third-layer metal wiring prepared in advance as a library are provided.
(Hereinafter referred to as a 3AL dummy wiring basic cell) is selected as a selected basic cell in a wiring layer selection step 11 based on the wiring layer information in the wiring layer setting step 4 described above. In step 6, the selected basic cell is replaced with the basic cell below the power supply wiring region.

Next, a power supply terminal cell 13 having a second-layer metal wiring and a second-layer power supply terminal (hereinafter referred to as a power supply terminal cell with 2AL dummy wiring) and a third One of the power supply terminal cells 16 having the layer metal wiring and the power supply terminal of the third layer (hereinafter referred to as a power supply terminal cell with 3AL dummy wiring) is connected to the wiring layer according to the information in the wiring layer setting step 4 described above. In a selection step 11, a selected power supply terminal cell is selected, and the selected power supply terminal cell is stored in the power supply arrangement area in step 7;
Place with

Further, a cell 14 having a second-layer metal wiring on the entire surface of the cell prepared in advance as a library (hereinafter referred to as a cell with 2AL dummy wiring for an empty cell portion) and a third-layer metal wiring on the entire surface of the cell are prepared. Cell 17 with
(Hereafter referred to as the cell with 3AL dummy wiring for the empty cell part)
Is selected as the selected cell with the dummy wiring in the wiring layer selecting step 11 based on the information of the wiring layer setting step 4 described above, and is selected in the unplaced area of the cell in the power wiring area. Is filled in the selected cell with the dummy wiring in step 8.

Finally, the power supply terminal of the macrocell and the power supply terminal of the interface block are wired in step 9 using a normal automatic wiring function, thereby realizing the power supply wiring of the macrocell.

FIG. 2 is a layout diagram of power supply wiring when the wiring method shown in the flowchart of FIG. 1 is implemented.

In FIG. 2, 43 is a power supply block of the interface block, 44 is a power supply terminal of the power supply block 43 of the interface block, and 45 is a second layer metal wiring (2AL wiring) to be wired in step 9
It is. Reference numeral 46 denotes a power supply terminal cell 13 with a 2AL dummy wiring, reference numeral 47 denotes a setting range of a power supply wiring area in step 2, and reference numeral 48 denotes a cell 17 with a 2AL dummy wiring for an empty cell portion. Reference numeral 49 denotes a first layer metal terminal (hereinafter referred to as a 1AL terminal) of the basic cell. Reference numeral 50 denotes a 2AL wiring used in the basic cell, and reference numeral 51 denotes a power supply terminal of the macro cell.

FIG. 3 is a layout diagram after wiring is performed to each terminal of the basic cell by the automatic placement and routing tool after performing the wiring method of FIG.

The wiring connection to the 1AL terminal 49 of the basic cell is performed by an automatic placement and routing tool using a third layer metal wiring (3AL wiring) 52 and a second layer through hole connecting the second layer metal wiring (2AL wiring) and 3AL wiring. (Hereinafter referred to as 2TH) 2AL wiring, first layer through hole (hereinafter 1TH wiring) connecting the first metal wiring (1AL wiring) and 2AL wiring.
) Are connected in the wiring order.

Next, the operation of the first embodiment will be described with reference to FIG. 1 (flowchart) and FIG. 2 (layout diagram).

According to the macro cell arrangement (step 1) of FIG. 1, the arrangement position of the power supply terminal 51 of the macro cell is determined.
The setting range 47 of the power supply wiring area is set by setting the power supply wiring area (step 2).

Next, in the basic cell arrangement (step 3), a basic cell having a 1AL terminal 49 as shown in FIG. 4 or a basic cell having a 1AL terminal 49 and a 2AL wiring 50 as shown in FIG. It is arranged within the setting range 47 of the area.

Next, in the wiring layer setting (step 4), the definition of each wiring layer and wiring direction of the automatic placement and routing tool and the arrangement of the power supply terminal 51 of the macro cell and the power supply terminal 44 of the interface block are used to determine the power supply wiring. Determine the wiring layer.

For example, in FIG. 2, if the LSI chip has a three-layer product and the wiring direction and the wiring direction of the automatic placement and wiring are 1AL wiring and X
The wiring direction is defined parallel to the axis, the 2AL wiring is parallel to the X axis, and the 3AL wiring is parallel to the Y axis. In addition, the power supply terminal 51 of the macro cell and the power supply terminal 44 of the interface block are arranged on the same Y axis. In this case, the wiring layer of the power supply wiring is a 2AL wiring layer in a direction parallel to the Y axis. In this case, the 1AL wiring layer is not selected because it is frequently used in the basic cell.

Separately from the library of the basic cells 10, the basic cell 12 with 2AL dummy wiring, the basic cell 15 with 3AL dummy wiring, the power terminal cell 13 with 2AL dummy wiring, the power terminal cell 16 with 3AL dummy wiring, and the empty The cell 14 with 2AL dummy wiring for the cell part and the cell 17 with 3AL dummy wiring for the empty cell part are prepared in advance as a library.

In the extraction of the cell name of the power supply wiring area (step 5), the basic cells arranged in the power supply wiring area 47 of FIG. 2 are extracted.

In the replacement of the basic cell under the power supply wiring area (step 6), the basic cell under the power supply wiring area is replaced with a 2AL dummy having the same dummy wiring layer as the wiring layer determined in the wiring layer setting (step 4). The replacement is performed with the basic cell 12 with wiring or the basic cell 15 with 3AL dummy wiring.

More specifically, assuming that the setting of the wiring layer (step 4) is the 2AL wiring layer as an example, FIGS.
Is connected to a 1AL terminal 49 as shown in FIGS.
And 2AL wirings 50 are replaced with basic cells with 2AL dummy wirings filled with 2AL wirings 51. In this case, the 2AL wiring 51, the 1AL terminal 49 and the 2AL wiring 5
As shown in FIG. 8, it is necessary that the aluminum interval of 0 is larger than the minimum aluminum interval 52 of the layout design standard.

In the arrangement of the cells with power supply terminals in the power supply wiring area (step 7), either the power supply terminal cell 13 with 2AL dummy wiring or the power supply terminal cell 16 with 3AL dummy wiring depends on the selection of the wiring layer (step 11). Is selected, and the cell is connected to the boundary portion 46 of the power supply wiring region 47 in FIG.
To place.

In filling the cells with dummy wiring in the power supply wiring area (step 8), the cell 14 with 2AL dummy wiring for empty cell section or the cell 17 with 3AL dummy wiring for empty cell section is selected by selecting the wiring layer (step 11). If, for example, the setting of the wiring layer in step 4 is the 2AL wiring layer, the unplaced area of the cell in the power supply wiring area 47 in FIG. Perform the deployment quickly.

In the automatic wiring of the power supply terminal of the macro cell and the power supply terminal of the interface block (step 9), for example, when the wiring layer setting (step 4) is the 2AL wiring layer, the power supply terminal 51 and the 2AL dummy of the macro cell in FIG. The 2AL wiring 45 is used to connect between the power supply terminals 46 with wiring and between the power supply terminal 44 of the interface block and the power supply terminal 46 with 2AL dummy wiring using a normal automatic wiring function.

By executing steps 1 to 17 in FIG. 1, power supply wiring for the macro cell as shown in FIG. 2 is enabled, and at the same time, the power supply wiring for arranging and wiring the basic cells under the power supply wiring is obtained. realizable.

FIG. 1 shows a wiring flow for an LSI chip of three layers or less. For example, in a four-layer LSI chip, FIG. 1 shows a basic cell with 4AL dummy wiring, a power supply terminal cell with 4AL dummy wiring, and an empty cell. The present invention can be easily applied by adding a cell with 4AL dummy wirings for the cell section as a library and selecting a plurality of layers in selecting a wiring layer (step 11).

In addition, it goes without saying that the present invention is applicable to an LSI chip having five or more layers.

Next, effects of the first embodiment will be described.

In the above-described conventional wiring method, it is impossible to dispose the basic cell under the power supply line 57 of the macro cell as shown in FIG. For this reason, the relatively small LSI chip 55 having a size of the internal region 59 of 4 mm × 4 mm.
Is assumed, the size of each macro cell 60 is 900 μm × 1500 μm, and the macro cell 60
The dedicated power supply terminal 57 has two GNDs and two VDDs in total, and the power supply wiring 57 per one wire is 700 μm × 150 μm.
If we take the case of wiring with m as an example,
Internal area 59 other than macro cell area of LSI chip 55
Area is 1.06 × 10 ⁷ μm ² (= 4000 μm ×
4000 μm−900 μm × 1500 μm × 4). The area occupied by the power supply wiring 57 of the macro cell 60 is 1.68 × 10 ⁶ μm ² (= 700 μm × 150 μm).
m × 4 × 4). Therefore, the area ratio of the usable internal region 59 when the conventional wiring method is used is:
55.75%.

On the other hand, when the wiring method according to the present invention is applied, the area ratio of the usable internal region is 66.
This is 25%, and the integration degree can be improved by 10.5% even if only the area ratio of the usable internal region is taken. Also,
For example, one P-channel transistor and N-channel transistor 1 each having a layout size of the inverter circuit of the basic cell of 2.52 μm in the X direction and 8.40 μm in the Y direction.
In the case of a two-transistor configuration, 79365 inverter circuits can be arranged under the power supply wiring of the macro cell by simple calculation in the present invention. Now, even if it is assumed that the wiring performance limit of the placement and routing tool is 50% of the allocable area, according to the present invention, approximately 39000 inverter circuits can be arranged and wired under the power supply wiring of the macro cell. There is an effect that the degree of integration can be improved as compared with the related art.

Next, a second embodiment of the present invention will be described.

Referring to FIG. 9, there is shown a wiring method of a semiconductor integrated circuit according to a second embodiment of the present invention. FIG.
The difference between FIG. 1 and FIG. 1 is that in FIG. 1, the basic cell 12 with 2AL dummy wiring and the basic cell 15 with 3AL dummy wiring had to be prepared in advance as a library.
Then, automatic generation is enabled based on the wiring layer setting (step 4) and the library of the basic cells 10. That is,
According to the first embodiment, it is necessary to prepare several hundred types of libraries each of a basic cell with 2AL dummy wirings and a basic cell with 3AL dummy wirings in advance for a library of hundreds of basic cells. Solving the problem.

FIG. 9 will be described below.

The cell size, cell terminal shape, and terminal layer are extracted from the library of the basic cells 10 (steps 18, 19, and 20), and the design rule file 23 prepared in advance is referred to. Then, using the terminal shape extracted in step 19 and the terminal layer of the terminal extracted in step 20 as input data, the terminal shape is thickened by a logical operation (step 22).

Here, in the design rule file 23, for example, the minimum distance between aluminum of 1AL wiring and 2AL wiring is defined. The logical operation (step 22) is
The terminal shape is thickened by the minimum interval of the aluminum in the design rule file 23 and processed to create intermediate data 2 (26).

On the other hand, based on the cell size extracted in step 18 and the setting of the wiring layer (step 4), 2AL is generated over the entire cell by selecting the wiring layer (step 11) (step 21). Or 3AL over the entire cell
(Step 24) is selected.

For example, FIG. 2 in which the wiring layer is a 2AL wiring layer
In the case of (2), step 21 is selected, and 2AL is generated over the entire area of the cell to create intermediate data 1 (25).

In the logical operation of step 27, the graphic data of the portion where the graphic data of the intermediate data 2 (26) and the graphic data of the intermediate data 1 (25) overlap are extracted, and the graphic data of the intermediate data 1 (25) is extracted. Subtraction from data (NO
T) Perform processing to create intermediate data 3 (28).

In the data handling of step 29,
By performing an addition process on the graphic data of the intermediate data 3 (28) and the graphic data of the basic cell 10, the target basic cell 30 with dummy wiring can be automatically generated.

Next, a third embodiment of the present invention will be described.

Referring to FIG. 10, there is shown a wiring method of a semiconductor integrated circuit according to a third embodiment of the present invention. FIG. 10 provides a method of arranging the basic cells in Step 3 of FIG. 1, and particularly arranges the basic cells so that the wiring resistance of the power supply wiring of the macro cell is minimized.

FIG. 11, FIG. 12, FIG. 13, and FIG.
It is explanatory drawing which supplements the flowchart of FIG.

In FIG. 10, after extracting the basic cells under the power supply wiring in step 31, the terminal name and terminal coordinates of each basic cell are extracted in step 32. For example, as shown in FIG.
Taking the case where there are three terminals of 5 as an example, the terminal names and terminal coordinates of the basic cell are extracted as follows.

In the terminal 53, the terminal name is H01 and the terminal X
The coordinate value is 1 and the Y coordinate value is 6. At the terminal 54, the terminal name is H02, the X coordinate value of the terminal is 8, and the Y coordinate value is 6. In the terminal 55, the terminal name is N01, the X coordinate value of the terminal is 6, and the Y coordinate value is 1.

Next, in step 33, the extracted data is converted into a table in a table format of cell name-terminal name-terminal coordinates.
FIG. 12 shows a specific example of the converted table in the table format.

In the selection of the cell arrangement direction in step 34, for example, when minimizing the wiring resistance of the power supply wiring in the direction parallel to the X axis, the Y direction is selected. Conversely, the wiring resistance is selected in the direction parallel to the Y axis. Indicates that the X direction is selected. For example, in the cell arrangement direction of step 34, Y
When the direction is selected, a basic cell having the same Y coordinate of the terminal is searched from the table in FIG. 12 in step 37, and as a result, the Y coordinate value of the terminal is changed as shown by 57 in FIG. A, C, and D of the block names of 1 or 6 are extracted.

Further, by arranging the basic cells extracted in the above description on the same Y coordinate in step 38, a layout diagram shown in FIG. 13 is obtained.

That is, reference numeral 58 in FIG. 13 indicates the basic cells arranged on the same Y coordinate in step 38, and the terminals of the basic cells are aligned on the same Y coordinate of Y1 and Y6 of the Y coordinate.

FIG. 14 shows the result of applying the wiring method of the present invention to the basic cell arrangement shown in FIG. 13. Reference numeral 60 denotes a power supply wiring of 2AL wiring, and 59 denotes a 1AL terminal of the basic cell. As apparent from FIG. 14, the 1AL terminal 59
Are aligned with Y1 and Y6, it is possible to minimize the wiring resistance of the power supply wiring.

[0083]

As described above, according to the present invention, L
A power supply wiring for a power supply terminal of a macro cell arranged in an internal region of an SI chip and a power supply terminal of a power supply block of an interface block, and a power supply wiring capable of arranging and wiring a basic cell under the power supply wiring of the macro cell You can get the way.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating a wiring method of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a layout diagram of power supply wiring when the wiring method of FIG. 1 is implemented.

FIG. 3 is a layout diagram after wiring is performed on each terminal of a basic cell by an automatic placement and routing tool after the wiring method of FIG. 1 is performed.

FIG. 4 is a diagram for explaining the wiring method of FIG. 1;

FIG. 5 is a diagram for explaining the wiring method of FIG. 1;

FIG. 6 is a diagram for explaining the wiring method of FIG. 1;

FIG. 7 is a diagram for explaining the wiring method of FIG. 1;

FIG. 8 is a diagram for explaining the wiring method of FIG. 1;

FIG. 9 is a flowchart illustrating a method of wiring a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 10 is a flowchart illustrating a wiring method of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 11 is a diagram for explaining the wiring method of FIG. 10;

FIG. 12 is a diagram for explaining the wiring method of FIG. 10;

FIG. 13 is a diagram for explaining the wiring method of FIG. 10;

FIG. 14 is a diagram for explaining the wiring method of FIG. 10;

FIG. 15 is a plan view of a layout pattern of a conventional LSI chip.

FIG. 16 is a flowchart illustrating a first conventional power supply wiring method for a macro cell.

FIG. 17 is a layout diagram of power supply wiring when the wiring method of FIG. 16 is implemented.

FIG. 18 is a flowchart for explaining a second conventional method for wiring power supply of a macro cell.

19 is a layout diagram of power supply wiring when the wiring method of FIG. 18 is implemented.

[Explanation of symbols]

 43 Power supply block 44 Power supply terminal 45 Second layer metal wiring (2AL wiring) 46 Power supply terminal cell with 2AL dummy wiring 48 Cell with 2AL dummy wiring for empty cell section 49 First layer metal terminal (1AL terminal) 50 2AL wiring 51 Power supply terminal 55 LSI chip 59 Internal area 60 Macro cell (large-scale function cell)

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/82 H01L 27/118

Claims (6)

(57) [Claims] When a large-scale function cell having a power supply terminal (51) is arranged as a macro cell (60) in an internal area (59) of an LSI chip (55), a power supply terminal (51) of the macro cell (60) is provided. And a power supply wiring of a power supply terminal of a power supply block (43) of an interface block, and a layout and wiring of a basic cell having a basic function under a power supply wiring of a macro cell (60). After the macro cell arrangement (Step 1) is performed, the basic cell arrangement (Step 3) is performed. After the basic cell arrangement, the power supply wiring layer of the macro cell (60) is set (Step 4). By replacing the basic cell with one of the basic cell (12) having the second-layer metal wiring and the basic cell (15) having the third-layer metal wiring, the macro cell ( 0) In the above-mentioned wiring method, in which the power supply wiring and the basic cells under the power supply wiring can be arranged and wired, the basic cell (12) having the second-layer metal wiring as the replacement basic cell and the third-layer metal wiring The basic cell (15) having the same logic function as the basic cell under the power supply wiring, which is the basic cell before replacement, has terminals of the basic cell for replacement (FIGS. 6, 7, 8, and 9).
A wiring method characterized in that a power supply wiring portion on a terminal of the replacement basic cell is opened so that wiring (52 in FIG. 3) to (49) in FIG. 3 can be performed. 2. The wiring method according to claim 1, wherein the basic cell (12) having the second-layer metal wiring and the basic cell (15) having the third-layer metal wiring are prepared in advance, and the macrocell ( 60) Setting of power supply wiring layer (step 4)
The basic cell under the power supply wiring is replaced with the basic cell (1
2) A wiring method characterized by replacing with one of the basic cells (15) having a third-layer metal wiring. 3. The wiring method according to claim 1, wherein a power supply wiring layer of the macro cell is set (step 4).
According to the condition at the time of the above, the basic cell (12) having the second-layer metal wiring and the third
Automatically generate any one of the basic cells (15) having the layer metal wiring, and set the power supply wiring layer of the macro cell (60) (Step 4)
The basic cell under the power supply wiring is replaced with one of the automatically generated basic cell (12) having the second-layer metal wiring and the basic cell (15) having the third-layer metal wiring according to the conditions in the above case. A wiring method characterized by the above-mentioned. 4. The wiring method according to claim 3, wherein the step of automatically generating is performed based on a cell size of a basic cell, a terminal shape of the basic cell, and a terminal of a terminal of the basic cell from a library of basic cells. By extracting a layer as extracted data and performing a logical operation on the extracted data based on a design rule file prepared in advance, a basic cell (12) having a second-layer metal wiring and a third-layer metal wiring can be obtained. A step of automatically generating any one of the basic cells (15) included in the wiring. 5. An automatic placement and routing tool having an algorithm for achieving the routing method according to claim 1. 6. A power supply terminal (51) of a macro cell (60) when a large-scale function cell having a power supply terminal (51) is arranged as a macro cell (60) in an internal area (59) of an LSI chip (55). And a power supply wiring of a power supply terminal of a power supply block (43) of an interface block, and a layout and wiring of a basic cell having a basic function under a power supply wiring of a macro cell (60). After the macro cell arrangement (Step 1) is performed, the basic cell arrangement (Step 3) is performed. After the basic cell arrangement, the power supply wiring layer of the macro cell (60) is set (Step 4). By replacing the basic cell with one of the basic cell (12) having the second-layer metal wiring and the basic cell (15) having the third-layer metal wiring, the macro cell ( 0) In the above-mentioned wiring method in which the power supply wiring and the basic cell under the power supply wiring can be arranged and wired, the cell name of the basic cell to be disposed under the power supply wiring, the terminal name and terminal coordinates of the terminal of the basic cell are extracted Then, create a table in advance, and from the wiring direction of the power supply wiring and the table,
A wiring method, wherein terminals of the basic cells are arranged so as to be aligned on the same coordinate axis, thereby minimizing wiring resistance of a power supply wiring.