JP2001308189A - Semiconductor integrated circuit device and method for routing clock line and recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress clock skew more efficiently and effectively. SOLUTION: In order to make uniform the capacity of clock line over the entire region between a signal line and a long distance clock line 112 generating a clock skew or a part thereof, that region is shielded by a power supply or ground line. A plurality of rectangular figure data are generated at a coordinate position of a shield line 115 which can lead out a clock branch not to cause any line short or design rule error from a clock main line 112 to a block 105 having a clock input terminal 114b arranged at an arbitrary place. When a clock branch is led out, a clock branch 113b associated with a shield line (115b) is led out for a region obtained by deleting a specified rectangular figure data 117b among the plurality of rectangular figure data and a power supply via 125b for the shield line of the clock branch is generated automatically in a region intersecting with the power supply or the ground line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having a plurality of circuits requiring a clock signal, such as a processor, and more particularly to a clock for improving a clock skew of a clock signal supplied to the plurality of circuits. The present invention relates to a wiring method and a recording medium that executes the clock wiring method.

[0002]

2. Description of the Related Art Synchronous integrated circuits use clock signals to control the timing of the entire system.
This clock signal must be transmitted to various functional blocks such as flip-flops and latches arranged over the entire area of the integrated circuit, and to memories and interface blocks that use the clock signal. If the functional blocks controlled by the same clock are arranged at different distances from the clock driver, the time for receiving the clock signal will be different. This variation in the arrival time of the clock signal is called clock skew.

The cause of clock skew is caused by a delay caused by a clock buffer used for distributing a clock, a clock wiring resistance (R), and a capacitance (C). This clock skew can be minimized by equally distributing all clock buffers and wiring lengths that transmit clock signals.

However, even if the clock signal is wired with the same length, the capacitance of the clock wiring is determined by the environment of other signal wiring adjacent to or crossing the clock wiring, so that the capacity of the clock wiring is not uniform. The area for drawing out the clock branch wiring between the long distance clock wiring and the signal wiring is greatly affected by the congestion of the signal wiring layer. That is, in order to minimize the clock skew, it is necessary to equalize the capacitance (C) around the clock wiring in addition to the wiring resistance (R).

[0005] A conventional clock wiring method will be briefly described. FIG. 5 shows a processing procedure of a conventional clock wiring method. FIGS. 6A and 6B are a plan view and a cross-sectional view, as an example, schematically showing the arrangement relationship of each component of the conventional semiconductor integrated circuit device. The design of the wiring pattern is realized by an information processing device having a recording medium on which a predetermined program is recorded.

First, a block library and a net list are input (step S61). Next, the wiring of the clock trunk lines 212, 212a to 212c for long distance and the wiring of the power supply line are made (step S62). When the wiring is completed, each block (the memory 204, the functional block 205,
An I / O buffer or the like is provided (step S63). Then, the wiring of the clock branch lines 213a to 213c is made (step S64). When the wiring of the clock branch line is completed, the wiring of the general signal line is made (step S65).
In FIG. 6A, reference numeral 207 indicates a pulse generator, reference numerals 208 to 211 indicate clock drivers, reference numerals 214a to 214c indicate clock input terminals, and reference numeral 215 indicates a shielded terminal. Wiring.

[0007]

However, in the prior art, the wiring capacitance of the clock main line and the clock branch line is determined, and the load capacitance is manually adjusted to the position of the clock wiring with a small capacitance, so that the capacitance of the clock wiring is reduced. Work to make it uniform is required. Even if the clock skew is suppressed by providing a shield wiring (see 215 in FIG. 6) for the clock wiring, there may be places where sufficient effects cannot be obtained due to structural restrictions. There was a problem.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a semiconductor integrated circuit having a clock wiring capable of suppressing clock skew more efficiently and effectively. An object of the present invention is to provide an apparatus, a clock wiring method, and a recording medium for executing the wiring method.

[0009]

Means for Solving the Problems The present invention has the following constitution in order to solve the above-mentioned problems. The gist of the invention according to claim 1 is a semiconductor integrated circuit device having a plurality of circuits requiring a clock signal, comprising: a clock trunk from a pulse generator and a clock driver; a power and ground line; A plurality of circuits, and a plurality of circuits are arranged, and a clock branch line is provided in accordance with a judgment result obtained by judging whether or not the arrangement relation of each component of the device satisfies a predetermined rule. And a shield line for a clock branch line, and connection means for connecting the shield line for the clock branch line and a power supply or a ground line to each other in a crossing region. Semiconductor integrated circuit device.
The gist of the invention according to claim 2 is that the shield wiring for the clock main line includes a plurality of designated regions for the clock branch wiring, and the arrangement relation of the components of the device satisfies the predetermined rule. If it is determined that
A clock branch line and a shield line for the clock branch line are arranged in an area obtained by deleting a predetermined one of the plurality of designated regions for the clock branch line included in the shield line for the clock main line. Claim 1 characterized by the following:
In the semiconductor integrated circuit device described above. The gist of the invention described in claim 3 is that each of the plurality of designated regions for the clock branch line included in the shield line for the clock main line has a rectangular shape.
In the semiconductor integrated circuit device described above. The gist of the invention according to claim 4 is that, when it is determined that the respective arrangement relations of the constituent elements of the device do not satisfy the predetermined rule, the clock based on various data for arranging a clock branch line. 2. The semiconductor integrated circuit device according to claim 1, wherein a clock branch line and a clock branch branch shield line are arranged in a region obtained by deleting a predetermined region of the trunk line shield line. The gist of the invention according to claim 5 is that the shape of the area of the shield wiring for the clock main line, which is deleted when it is determined that the arrangement relation of the respective components of the device does not satisfy the predetermined rule, is satisfied. The semiconductor integrated circuit device according to claim 4, wherein the semiconductor integrated circuit device has a rectangular shape. The gist of the invention according to claim 6 is that the two shield wirings for the clock branch are arranged at predetermined intervals in parallel with the clock branch as a center. Present in integrated circuit devices. The gist of the present invention is a clock wiring method in a semiconductor integrated circuit device having a plurality of circuits requiring a clock signal, wherein a first step of arranging a clock main line from a pulse generator and a clock driver is provided. A second step of arranging a power supply and a ground line and a shield wiring for the clock main line, a third step of arranging the plurality of circuits, and the first, second and third steps, respectively. Determining whether the arrangement result obtained in (1) satisfies a predetermined rule; and, in accordance with the determination result in the determining step, a fourth step of arranging the clock branch line and the shield line for the clock branch line. A fifth step of arranging connecting means for connecting the shield wiring for the clock branch line and a power supply or a ground line to a region where either of the shield wiring and the power supply line or the ground line intersects. It consists in clock wiring method comprising. The gist of the invention described in claim 8 is that the shield wiring for the clock main line in the second step includes a plurality of designated areas for the clock branch wiring, and satisfies the predetermined rule in the determining step. If it is determined that there is not, in the fourth step, a predetermined one of the plurality of designated regions for the clock branch line included in the shield line for the clock main line is deleted,
The clock wiring method according to claim 7, wherein a clock branch line and a shield wiring for the clock branch line are arranged in the obtained area. The gist of the invention described in claim 9 is that the plurality of designated regions for the clock branch line included in the shield line for the clock trunk line in the second step are rectangular in shape. 8 is a clock wiring method. The gist of the invention according to claim 10 further comprises, before the determining step, a step of inputting various data for arranging clock branch lines, and the determining step satisfies the predetermined rule. When it is determined that there is no clock line, in the fourth step, a predetermined area of the shield wiring for the clock main line is deleted based on various data obtained in the inputting step, and the obtained area is deleted. The clock wiring method according to claim 7, wherein a clock branch line and a shield wiring for the clock branch line are arranged. The gist of the invention according to claim 11 is that, when it is determined in the determining step that the predetermined rule is not satisfied, the shape of the clock trunk line shield wiring region to be deleted in the fourth step is changed. 11. The clock wiring method according to claim 10, wherein the clock wiring is rectangular. Claim 1
The gist of the invention described in claim 2 is that, in the fourth step, two clock branch wiring shield wires are arranged at predetermined intervals in parallel with the clock branch line as a center. 11 is a clock wiring method. The gist of the invention described in claim 13 resides in a storage medium in which a program capable of executing the clock wiring method according to any one of claims 7 to 12 is described.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(First Embodiment) FIG. 1A is a plan view schematically showing the arrangement of components in a first embodiment of the present invention. FIG. 1B is a cross-sectional view taken along the line AA ′ shown by a dashed line in FIG. 1A. FIG. 1A
1B, reference numeral 101 denotes the entire semiconductor integrated circuit device. As shown in FIG. 1, a semiconductor integrated circuit device 101 according to the first embodiment includes a memory 104, a function block 105, and an I / O as a plurality of circuits requiring a clock signal.
It has a buffer and the like. 1A and 1B, a pulse generator is denoted by 107.
Reference numerals 108 to 111 denote clock drivers, and reference numerals 114a to 114c denote clock input terminals. In the following description, the memory 104 is used for convenience.
The following description focuses on the periphery of the functional block 105, and the other parts are omitted in the drawing, but have the same configuration.

As shown in FIG. 1, a semiconductor integrated circuit device 10
In FIG. 1, after removing the rectangular graphic data 117a and 117b for shield wiring below the clock main line 112, the clock branch lines 113a and 113b with shield wiring are removed.
Are connected to the clock input terminals 114a and 114b of the memory 104 and the functional block 105.

The clock signal output from the pulse generator 107 is supplied to the clock trunk line 112 for a long distance via each of the clock drivers 108 to 111 arranged at equal distances at the branch point in order to suppress delay variations, ie, clock skew. Conveyed to. Note that the long-distance clock trunk line 112 is provided with a shield wiring 115 connected to a power supply or a ground below the clock wiring in order to suppress variations in wiring capacitance.

The lower side of the shield wiring 115 is a signal wiring layer 118. In the conventional semiconductor integrated circuit device described above, since there is a gap between the clock wiring and the signal wiring (see FIG. 6B), the capacity of the clock wiring is affected by the congestion degree of the general signal wiring, whereas In the semiconductor integrated circuit device 101 according to the present invention, since the shield wiring is provided on the entire surface between the clock trunk line 112 for long distance and the signal wiring layer 118, the wiring capacity of the clock wiring is reduced due to the congestion of the general signal wiring. The clock delay is kept almost constant in any region without affecting the degree.

The lower side of the signal wiring layer 118 is a transistor arrangement region, in which an internal region 102 and an interface region 103 are provided. The internal area 102 includes a memory 104 having a clock input terminal 114a.
And the functional block 105 (clock buffer, FF, latch, etc.)
An interface block 106 having a clock input terminal 114c is arranged at an arbitrary position.

In order to prevent the clock signal transmitted to the clock trunk line 112 from the semiconductor integrated circuit device 101 having such a structure from being affected by variations in capacitance in the subsequent wiring paths, shield wiring is provided. Provided clock branch lines 113a and 113b are provided.

More specifically, from the clock input terminals 114a and 114b of the memory 104 and the functional block 105,
Clocked branch lines 113a and 113b with shield wiring are drawn out toward the clock trunk line coordinate positions 112a and 112b where the nearest clock branch line can be drawn out. At this time, if a short error or a spacing error occurs, rectangular graphic data 117 for shield wiring, which has been created in advance so as to satisfy the design rule, is used.
a, 117b are deleted, and clock branch lines 113a, 113b with shield wiring are drawn out from the obtained area. A power supply wiring via automatically generated is arranged in a region where the shield wiring for the clock branch line and the power supply or ground line intersect. Therefore, the clock input terminal 114a of each block is connected to the clock trunk 112 for long distance.
To 114c, the variation in capacitance with other signal wiring is almost uniform, and clock skew is minimized.

FIGS. 2A and 2B are an enlarged plan view and a sectional view of the area B in FIG. 1A after the functional blocks are arranged, and show a state before the clock branch line 113b with shield wiring is drawn. 2C and 2D
FIG. 1A is an enlarged plan view and a sectional view of a region B in FIG. 1A, and shows a state where a clock branch line 113b with shield wiring is drawn. The first embodiment will be further described with reference to FIGS. 2A to 2D.

In the state shown in FIGS. 2A and 2B, a power supply or ground shield wiring 115 is provided below the long-distance clock main line 112 in order to suppress variations in the wiring capacitance of the long-distance clock main line 112. Is provided. The lower side of the shield wiring 115 is a general signal wiring layer 1.
18 and the general signal wiring passes through,
Between the clock trunk line 112 for long distance and the signal wiring layer 118, a shield wiring 115 is arranged and completely separated, so that there is no influence of the capacitance with the signal wiring.
In this state, when a via for clock wiring is generated in the shield wiring 115 at the coordinate position of the intersection of the clock main line 112 and the clock branch line from which wiring can be drawn,
A plurality of rectangular graphic data to be deleted, which does not violate a short or design rule, are created in advance.

Then, as shown in FIGS. 2C and 2D, the clock input terminal position 114b of the functional block 105
The clock branch line 113b with the shield wiring (115b) is drawn. That is, for the functional block 105 having the clock input terminal 114b, the rectangular graphic data 117b corresponding to the wiring drawing position is deleted to generate the clock wiring via 123b, and the clock branch line 113b with the shield wiring (115b) is drawn. . Therefore, even after the clock branch line is drawn out to the clock terminal of each block, only the predetermined graphic data 117b of the plurality of rectangular graphic data created in advance at the wiring drawing position is deleted. The wiring capacitance of the clock wiring is minimized. In the shield wiring 115b for the clock branch, a power supply wiring via 125b is generated in a region intersecting the same power supply or ground. As shown in FIG. 2C, the two shield wirings 115b for the clock branch line are arranged at predetermined intervals in accordance with the design rule in parallel with the clock branch line 113b as a center.

FIG. 3 is a flowchart showing a processing procedure of the clock wiring method according to the first embodiment. Note that, in FIG. 3, steps S1 to S
Reference numerals up to 8 are given. Further, the actual wiring pattern design includes a recording medium on which a predetermined program corresponding to the processing procedure shown in FIG. 3 is recorded, and reads out predetermined information from the recording medium as needed to execute a specific process. This is realized by an information processing device capable of performing the operations.

First, in step 1, a block library and a net list are input. Then, in step 2, a clock trunk line 112 for a long distance and a power supply line including a shield wiring 115 in which rectangular graphic data for deletion (see 117b in FIG. 2A) are included are arranged. Next, in step 3, the memory 104, the functional block 105, the I / O buffer, and the like are arranged. When the arrangement is completed, the process proceeds to the wiring of the clock branch line with shield wiring (steps 4 to 7).

In the wiring of the clock branch line with the shield wiring, first, in step 4, it is determined whether or not a short-circuit or a portion not satisfying the design rule has occurred. Is satisfied, the process proceeds to step 6, where a clock branch line is directly arranged. On the other hand, if it is determined in step 4 that there is a short-circuited portion or that there is a portion that does not satisfy the design rules, the process proceeds to step 5 and a predetermined portion included in the coordinate position of the shield wiring in advance. The rectangular graphic data (see 117b in FIG. 2A) is deleted. When the graphic data is deleted and the wiring area is secured, step 6
, A clock branch line is provided. In step 7, a power supply wiring via (FIG. 2C) is provided in a region intersecting the power supply or ground wiring so that the shield wiring (see 115b in FIG. 2C) of the clock branch wiring with the shield wiring provided does not become a floating wiring. 125b) is generated. When the wiring of the clock branch line with the shield wiring is completed in this way, in step 8, the wiring of the general signal line is performed.

In the above description of the first embodiment, a clock wiring via is generated at the coordinate position of the intersection of the clock main line 112 of the shield wiring 115 and the clock branch line from which wiring can be extracted. Also, a case has been described in which a plurality of rectangular graphic data to be deleted areas that do not violate the short circuit or the design rule have been created in advance, but graphic data having a line-symmetric shape other than a rectangle may be created. .

As described above, according to the first embodiment, the following effects can be obtained. The effect is that the long-distance clock trunk is shielded from other general signal wiring by shield wiring, and furthermore, when wiring from the long-distance clock trunk to each clock terminal, shielding in accordance with the design standards Since the clock branch line with the shield wiring is drawn out from the area obtained by deleting a predetermined one of the predetermined graphic data of the wiring, it is possible to further suppress the influence of the delay due to the difference in capacitance from the signal wiring. Become. For this reason, the clock wiring can minimize the variation error of the capacitance delay from other signal wirings, that is, the clock skew.

(Second Embodiment) FIG. 4 is a flowchart showing a processing procedure of a clock wiring method according to a second embodiment of the present invention. The clock wiring method according to the second embodiment differs from the clock wiring method according to the first embodiment in that the rectangular wiring pattern data for deletion is not created in the shield wiring 115 in advance, and the above-described first wiring method is performed using coordinate data. A clock branch line with shield wiring having the same effect as that of the clock wiring method according to the embodiment is arranged. Regarding the steps for performing the same processes as those of the clock wiring method according to the above-described first embodiment, corresponding portions are denoted by the same reference numerals and description thereof is omitted.

First, in step 1, a block library and a net list are input. Then, in step 42, a clock trunk line for a long distance and a power supply line including a shield wiring are arranged. Next, in step 3, each block is arranged, and in step 43, various data necessary for wiring the clock branch line are input. Specifically, the starting point coordinate position of the clock main line connectable to the clock terminals of the functional block, the memory, and the interface block, the number of repetitions and intervals in the X-axis and Y-axis directions, and the power supply for extracting the clock branch line Alternatively, a clock wiring lead-out position description file that specifies the layer from which wiring is to be deleted when the ground line needs to be deleted and the area width in the X-axis and Y-axis directions from which wiring is to be deleted is created and input in advance. When the input of various data necessary for the wiring of the clock branch line is completed, the process proceeds to the wiring of the clock branch line with shield wiring (step 44, step 46, step 6, step 7).

When shifting to the wiring of the clock branch line with shield wiring, first, in step 44, based on the data of the description file describing the drawing position of the clock branch line, the coordinate position of the file closest to the clock input terminal position of each block. Is determined, and it is determined whether or not a spacing error or a short error will occur due to design rules in drawing out the clock branch wiring. When it is determined that no error occurs, the process proceeds to step 6,
A clock branch line is drawn from the nearest file coordinate position to each clock terminal. On the other hand, if it is determined in step 44 that an error has occurred in the design rule and it is necessary to delete the shield wiring, the process proceeds to step 46 in which the X of the layer specified in the clock wiring leading position description file is specified.
The shield wiring in a region having a predetermined width in the axis and Y axis directions is deleted. Then, in step 6, a clock branch line is arranged. Then, in step 7, a power supply wiring via is generated in a region intersecting with the power supply or the ground wiring so that the shield wiring of the clock branch wiring with the shield wiring provided does not become a floating wiring. When the wiring of the clock branch line with the shield wiring is completed in this way, step 8 is executed.
In the above, wiring of general signal lines is performed.

As described above, according to the clock wiring method according to the second embodiment, it is possible to provide a semiconductor integrated circuit device having the same effect as that of the first embodiment. In addition, since the clock wiring leading position description file is created and input in advance, it is possible to reduce the load on the software of the information processing device.

It should be noted that the present invention is not limited to the above embodiments, and it is obvious that the embodiments can be appropriately modified within the scope of the technical idea of the present invention. Further, the number, position, shape, and the like of the constituent members are not limited to the above-described embodiment, but can be set to numbers, positions, shapes, and the like suitable for carrying out the present invention. In each drawing, the same components are denoted by the same reference numerals.

[0031]

Since the present invention is configured as described above, the following effects can be obtained. The effect is that the long-distance clock trunk is shielded from other general signal wiring by shield wiring, and furthermore, when wiring from the long-distance clock trunk to each clock terminal, shielding in accordance with the design standards Deletion of the area obtained by deleting a predetermined one of the predetermined graphic data of the wiring, or the shield wiring of the predetermined width in the X-axis and Y-axis directions of the layer specified by the clock wiring drawing position description file Since the clock branch line with the shield wiring is drawn out from the obtained region, it is possible to further suppress the influence of the delay due to the difference in capacitance from the signal wiring. For this reason, the clock wiring can minimize the variation error of the capacitance delay from other signal wirings, that is, the clock skew.

[Brief description of the drawings]

FIGS. 1A and 1B are a plan view and a cross-sectional view illustrating an arrangement relationship of components according to a first embodiment of the present invention.

FIG. 2 is an enlarged plan view and a cross-sectional view of a region B in FIG. 1;

FIG. 3 is a flowchart illustrating a processing procedure of a clock wiring method according to the first embodiment of the present invention.

FIG. 4 is a flowchart illustrating a processing procedure of a clock wiring method according to a second embodiment of the present invention.

FIG. 5 is a flowchart showing a processing procedure of a conventional clock wiring method.

6A and 6B are a plan view and a cross-sectional view illustrating an arrangement relationship of components of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

101: semiconductor integrated circuit device 102: internal area 103: interface area 104: memory 105: functional block 106: interface block 107: pulse generator 108 to 111: clock Driver 112: Clock trunk line for long distance 112a, 112b: Coordinate position of clock trunk line 113a, 113b: Clock branch line with shield wiring 114a to 114c: Clock input terminal 115: Shield wiring 115b ..Shield wiring for clock branch lines 117a, 117b: rectangular graphic data 118: signal wiring layer 123b: via for clock wiring 125b: via for power supply wiring

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/04 DH

Claims (13)

[Claims] 1. A semiconductor integrated circuit device having a plurality of circuits requiring a clock signal, comprising: a clock trunk from a pulse generator and a clock driver; a power and ground line; and a shield wiring for the clock trunk. The plurality of circuits are arranged, and a clock branch line and a clock branch line are provided in accordance with a determination result obtained by determining whether an arrangement relationship of each of the components of the device satisfies a predetermined rule. A semiconductor integrated circuit, wherein a shield wiring is provided, and a connecting means for connecting the shield wiring for the clock branch line and one of a power supply and a ground line to each other is provided. apparatus. 2. The clock main line shield wiring includes a plurality of designated regions for clock branch wiring, and it is determined that the arrangement relationship of each component of the device does not satisfy the predetermined rule. In this case, the clock branch line and the shield line for the clock branch line are separated from each other by removing a predetermined one of the plurality of designated regions for the clock branch line included in the shield line for the clock trunk line. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is arranged. 3. The semiconductor integrated circuit device according to claim 2, wherein each of the plurality of designated regions for the clock branch line included in the clock main line shield line has a rectangular shape. 4. A shield wiring for a clock main line based on various data for arranging a clock branch line when it is determined that the respective arrangement relations of the components of the device do not satisfy the predetermined rule. 2. The semiconductor integrated circuit device according to claim 1, wherein a clock branch line and a shield line for the clock branch line are arranged in a region obtained by deleting the predetermined region. 5. The shape of a region of the shield line for the clock main line, which is deleted when it is determined that the arrangement relation of the components of the device does not satisfy the predetermined rule, has a rectangular shape. 5. The semiconductor integrated circuit device according to claim 4, wherein: 6. The semiconductor integrated circuit device according to claim 1, wherein two shield wires for clock branch lines are arranged at predetermined intervals in parallel with the clock branch line as a center. 7. A clock wiring method in a semiconductor integrated circuit device having a plurality of circuits requiring a clock signal, comprising: a first step of arranging a clock main line from a pulse generator and a clock driver; and a power supply and a ground line. And a second step of arranging the shield wiring for the clock main line; a third step of arranging the plurality of circuits; and an arrangement result obtained in each of the first, second, and third steps. And a fourth step of arranging a clock branch line and a shield line for the clock branch line in accordance with a result of the determination in the determining step. A fifth step of arranging a connection means for connecting a shield wiring and a power supply or a ground line to a region where one of the power supply and the ground line crosses the other. Lock wiring method. 8. The shield wiring for a clock main line in the second step includes a plurality of designated areas for a clock branch line, and it is determined in the determining step that the predetermined rule is not satisfied. In this case, in the fourth step,
Removing a plurality of designated areas for the clock branch wiring included in the shield wiring for the clock trunk, and arranging a clock branch and a shield wiring for the clock branch in the obtained area. Claim 7
Clock wiring method as described. 9. The clock wiring according to claim 8, wherein each of the plurality of designated regions for the clock branch wiring included in the shield wiring for the clock main line in the second step has a rectangular shape. Method. 10. The method according to claim 1, further comprising a step of inputting various data for arranging a clock branch line before the determining step, wherein the determining step determines that the predetermined rule is not satisfied. In this case, in the fourth step,
Deleting a predetermined area of the shield wiring for the clock main line based on various data obtained by the inputting step,
8. The clock wiring method according to claim 7, wherein a clock branch line and a shield wiring for the clock branch line are arranged in the obtained area. 11. The method according to claim 11, wherein, in the determining step, when it is determined that the predetermined rule is not satisfied, the shape of the area of the shield line for the clock main line to be deleted in the fourth step is rectangular. Claim 1.
0. The clock wiring method according to item 0. 12. The method according to claim 7, wherein, in the fourth step, two shield wirings for clock branch lines are arranged at predetermined intervals in parallel with the clock branch lines as a center. Clock wiring method. 13. A recording medium in which a program capable of executing the clock wiring method according to claim 7 is described.