JPH05151313A - Layout method for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To suppress the increase in chip size, to reduce unwiring, and also, to execute an inter-block wiring by a wiring of shorter length. CONSTITUTION:In the inside of a block being an arrangement unit on a chip, free areas 31-34 for allowing an inter-block wiring to pass through are formed in advance. Also, in a block arrangement wiring processing for generating automatically a block by a computer, a processing for generating free areas 41-44 for allowing the inter-block wiring to pass through is provided in an inter-cell terminal wiring processing. Since the free areas are provided in the block, an inter-block wiring processing can be subjected to wiring by utilizing the free areas in the block, therefore, the number of pieces of unwirings can be reduced. Moreover, block terminals can be connected without going round the outside of the block, therefore, wiring length can be shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout of a semiconductor integrated circuit of a hierarchical design system, and more particularly to a block layout and a chip layout design method considering inter-block wiring.

[0002]

2. Description of the Related Art In order to cope with a large scale of a semiconductor integrated circuit, a hierarchical design is performed in which functionally coherent logic is designed as a block and a chip is composed of a plurality of blocks.

In the hierarchical design layout, after arranging and wiring the blocks, inter-block wiring is performed by utilizing the gaps between the blocks and between the blocks. In this inter-block wiring, if there is not enough space in the blocks and between the blocks, some of the signal lines cannot be wired and remain unwired. In order to wire this unwired signal, conventionally, the chip size has been increased to expand the gap between the blocks.

Further, when the number of blocks is large, the number of signals on the inter-block wirings increases, and the number of unwired wirings tends to increase. Therefore, the number of unwired lines has been reduced by integrating some blocks and reducing the number of blocks on the chip.

Another problem with reducing unwiring associated with inter-block wiring is shortening the wiring length between blocks. To solve this problem, a method of creating a block by previously determining the passage position in the block has been devised, and is described in the following document.

1) Shiobara et al., “One method of pin placement in floor plan”, IEICE Technical Committee VLSI Design Study Group, VLD8
8-87, P9-16 (1988) 2) Tomita et al., 3 persons, "Floor planning in VLSI", Information design automation research report 89-DT-46, vol.89, no.1
4, P9-16 (1989)

[0007]

In the layout of a semiconductor integrated circuit, the minimum chip area is one purpose. The method of wiring the unwired signal line by widening the gap between the blocks expands the wiring region between the blocks, and thus has a problem of increasing the chip area. Furthermore,
Since the signal line detours outside the block, the signal line extends for a long time, and there is a problem that the operation speed of the circuit is reduced. Similarly, when several blocks are integrated, there is a problem that the size of the block becomes large and the amount of detour of the signal line becomes large.

In the method of determining the position of the passing wiring in the block in advance, the wiring pattern in the block changes depending on the passing wiring position, so that the size of the block cannot be predicted and the layout is difficult to converge. There was a problem.

An object of the present invention is to suppress an increase in chip size and reduce unwiring. Still another object of the present invention is to provide a method for wiring between blocks with a wiring having a shorter length.

[0010]

In order to achieve the above object, an empty area for passing inter-block wiring is created in advance inside the block without affecting the wiring pattern in the block.

In addition, in the block layout and wiring processing for automatically generating blocks by a computer, the wiring processing between cells and terminals in the block is provided with processing for generating a vacant area for passing wiring between blocks.

In particular, in the process of generating a vacant area for passing inter-block wiring, a designated amount of vacant area for passing inter-block wiring is placed at a location in a designated block in accordance with a designer's instruction. Allow it to be generated.

[0013]

The inter-block wiring processing method includes the well-known maze method and line segment search method. Below,
An example using the maze method wiring will be described. Note that the maze method wiring is a method of searching a wiring path for the entire chip so as to widen the wavefront.

First, inter-block wiring is executed, and the cause of unwiring is analyzed in the drawing of the layout result. Based on the analysis result, the designer determines which block, where, and how much free space should be inserted. Based on this determination, in the block layout and wiring process, the amount of empty area and the insertion location are given as input information. At the time of the wiring process between the cell terminals in the block layout and wiring process, a process for generating an empty area for passing the wiring between blocks is called and an empty area is generated inside the block according to the input information.

Next, when the inter-block wiring is executed again using the block in which the empty area is formed, the wiring route is searched to the inside of the block, and the created empty area is the inter-block wiring. Used for.

Further, since the maze method wiring is performed by the shortest route, if an empty area for passing inter-block wiring is created in advance inside the block, it is created inside the block without bypassing the outside of the block. Since the embedded area is used, the wiring will be short. This is not limited to the maze method wiring, and the same result can be obtained because the wiring is performed by the shortest path even by a general wiring method.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an example of the layout block configuration. The layout block includes a block frame 1 indicating a block boundary, cell rows 21 to 23 in which cells, which are block arrangement units, are arranged in a horizontal direction, and wiring regions 41 to 44 for wiring between terminals of cells called channel regions. , An empty area 31 through the inter-block wiring provided in the channel area
It is composed of 34. The present embodiment is characterized in that a part of the inter-block signal can pass through the empty regions 31 to 34 provided inside the block and can be wired between the block terminals.

When inter-block wiring processing is performed, for example, by a maze method wiring using such a block, a route is searched to the inside of the block, and the created empty area is used to pass the inter-block wiring. To be done. Therefore,
There is an effect that it is possible to reduce the number of unwirings by reducing the number of undiscovered wiring routes.

Next, a process for automatically designing a block having the configuration shown in FIG. 1 especially by a computer will be described.
FIG. 2 is a block diagram of a block placement and routing process. CPU
An in-block placement / routing process 70 executed in 58 reads a logical input 50 in a block, which is connection information between cells stored in an external storage device such as a magnetic disk, into a memory. The cell layout 52 to be determined, the wiring process 53 for connecting the cell terminals based on the cell layout result, the data output 54 for storing the block layout result in the external storage device, and the external storage device such as a magnetic disk. The block layout result 55 is formed. Further, the wiring process 53 is configured by an initial route allocation 60 for allocating the logical wiring in the block to the channel region, and a detailed wiring 61 for determining a detailed wiring route of the signal allocated to the channel region. The detailed wiring 61 performs wiring with a horizontal line segment called a trunk line and a vertical line segment called a branch line. Creation of main line data 62, calculation of the wiring position of the main line in the wiring area, Allocation 63 to a wiring track configured by a process of creating a main table for storing the main wiring information, instruction information 56 for setting an empty area in a block is read into the memory 57, and an empty area setting instruction data is read. The input processing 641 for creating the data 68, the generation 64 of an empty area for passing the inter-block wiring, and the creation 65 of the line segment data of the wiring route. In the configuration of the present invention,
The cell arrangement 52 can be realized by a cluster growth method, and the wiring processing 53 can be realized by a generally well-known method such as a channel wiring method. The wiring process 53 has a processing configuration based on the channel method. The present embodiment is characterized in that an empty area generation 64 for passing the inter-block wiring is provided so that a part of the signals of the inter-block wiring can pass through the block.

In the following, the empty area generation 64 added to the wiring processing 53 constituted by the channel wiring method will be mainly described. First, the input data of the process 64 is shown in a concrete example in FIG. FIG. 3 shows a state in which the trunk track assignment 63 has been completed. (A) is a track allocation state, (b)
Shows a structure of a free area setting instruction table 68 created by reading the free area setting information 56 in the process 641, and (c) shows a structure of a main line table 69 for storing the track allocation state of the main line. The tables 68 and 69 become the input data of the process 64. The tracks are alternately allocated to the lower side and the upper side of the channel region. The track numbers are 1, 2, ... from the bottom on the bottom, -1, -2, ... from the top on the top.
Assign like.

Next, the empty area generation processing 64 with the tables 68 and 69 as input will be described with reference to the flowchart of FIG. A process 95 searches the table 68, and extracts free area setting instruction information having the same channel number as the channel being processed. If there is no information to be searched, it is not necessary to set an empty area in the channel being processed, and the process is terminated. If there is search information, the main line is taken out from the main line table 69 in the process 96, and the y coordinate of the main line is calculated in the process 97 based on the free area amount of the free area instruction information. The calculation result is stored in the y-coordinate column of the main line table 69 in process 98. The above processing is performed for all trunk lines. The output of process 64 is the trunk table 69. Here, the table 68
If it is specified that Ns main tracks are secured as the passage area of the inter-block wiring, the process y calculates the track y coordinate using the following equation.

Ch: number of tracks in the channel region (process 6
Output of 3. In Figure 3, Ch = 4. ) Ns: number of tracks secured as an empty area for passing inter-block wiring Ti
: Track number of signal i Yi:
Track y coordinate of signal i
When Ti <0
Yi = Ti +
Ns + Ch + 1
When Ti> 0
Yi = Ti FIG. 4 is a result obtained by applying the above equation when Ns = 2. (A) is a track allocation state,
(B) shows the contents of the trunk table 69 which stores the track allocation of the trunk at that time. In this case, an empty area for two tracks 66 and 67 is secured in the center of the channel area. Through the above processing, Ns tracks can be generated as free areas at the center of the channel area. This processing is characterized in that a free area can be set in the channel area without affecting the wiring pattern at all.

Next, it will be described that unwiring can be reduced by wiring between blocks using the blocks of the present invention. In order to obtain a chip layout that does not have unwiring and satisfies design specifications such as chip area and wiring length, it is usually necessary to perform re-layout several times. In particular, the occurrence of unwiring deteriorates the convergence of the layout. Generally, a signal that cannot be wired and remains as unwired appears for the following reason.

(1) The portions 85 and 88 in FIG. 6 indicate that the spaces between the blocks are crowded with wiring. Therefore, the wiring route of the signal line 86 is set to the portion 85,
Since it cannot be secured at 88, unwiring occurs between the terminals 81 and 82.

(2) The block terminal inside the block is the portion indicated by 89 in FIG. 6, and the wiring is blocked by the other signal 80 by the other signal 80 as shown in FIG. 6B by another wiring. Therefore, the signal line 87 cannot be wired between the terminals 83 and 84 and is left unwired.

In order to reduce the unwiring caused by such a reason, the block is moved to change the arrangement and the block configuration is repeated several times, and finally the unwiring is manually performed. Is wired. For this reason, there are problems such as a large chip area and an increase in layout man-hours. The present invention relates to 90, 9 of FIG.
Focusing on the empty areas existing above and below the block on the chip shown in FIG. 1, and allocating this empty area portion to the channel area in the block, 92, 93, and 94 shown in FIG.
As described above, a path (empty area) for passing an unwired signal is created, and this is used to reduce unwired. If there is no invalid area above and below the block, the chip size that is generally used is increased and the gap between the blocks is increased to reduce unwiring.

The above procedure is shown in FIG. 8 as a chip layout method. In particular, the relationship between the in-block placement / routing processing 70 having the free area generation processing 64 and the free area setting method has been mainly shown. First, the block used in the chip is automatically created in the intra-block placement / wiring process of process 70. Next, if the block is not placed on the chip, use a floor plan system with interactive processing function,
In step 72, blocks are arranged on the chip. If the block has already been arranged, the process 72 may be omitted.
Subsequently, in a process 73, inter-block wiring for connecting terminals between blocks is executed by a maze wiring method. As the execution result of the inter-block wiring in the process 73, the unwired signals 86 and 87 and the layout result are displayed on the terminal in the process terminal 74 as shown in FIG. If there is no non-wiring in the inter-block wiring in the process 73 and the chip area and wiring length satisfy the design specifications, the chip layout is completed (100). If the chip layout does not meet the design specifications, the designer
While looking at the terminal screen, consider which block, which channel area, where position, and how much free space should be set, and if there is a free space above and below the specified block (101) , Process 75 gives an instruction to recreate a block based on the free area. If there is no free space above or below the specified block (101), process 72
The block arrangement is re-executed to generate an empty area. In process 75, the internal details of the block for which a vacant area is to be set are displayed on the graphic terminal 78 by interactive processing. For example, when the command VIS BLK is input, the inside of the block is displayed as shown in FIG. Reference numeral 95 is a cell string, and reference numeral 96 is a channel number. The designer can interactively instruct the setting of the free area with a command while looking at the screen of FIG. A process 76 reads and interprets the command, and a process 77 stores the instruction information in the file 56. File 5
6 is read by the in-block placement / wiring processing 70, and the
A free area is created in the block by being set in the bull 68 and referenced in the free area generation processing 64.

By performing the chip layout according to the above flow, for example, as shown in FIG.
7 can be wired using the empty areas 92, 93, 94.

The embodiment is characterized in that the processing 75 is provided so that the empty area in the block can be finely set. Further, since the empty area on the chip is taken into the block, there is an effect that unwiring can be reduced without increasing the chip area.

A designation method for setting an empty area in a block will be described below. The designation method is performed by card or interactive processing. The following is an example of an instruction command for interactive processing. GAP is the command name, -c, -t,
-S is a parameter identifier.

GAP-c channel number-t track number-s free track number This command is converted into the following format in the process 76 and stored in the file 56. When specified by a card, the file 56 may be created by describing in this format.

RCOND_CHANGEGAP = channel number, track number, number of empty tracks The channel number specifies which channel in the block the empty area is set to. Channel areas are numbered in order from the bottom of the block as 1, 2, ..., And the number of this channel area is designated. In particular, when 0 is designated as the channel number, empty areas are inserted into all channels. As the track number, a detailed empty area location in the channel area is designated by the track number. The track number is 1, starting from the bottom of the channel area.
It is numbered 2, ... If you want to set an empty area in the center of the channel area, you can omit the track number. To specify the number of empty tracks, the number of empty areas to be secured for passing inter-block wiring is specified by the number of tracks.

The specified information is temporarily stored in the file 56, and the contents are referred to in the empty area generation 64 of the block layout and wiring processing as described above. When the setting location of the empty area is specified in detail by the track number, the track y coordinate is calculated by the following formula in order in process 97.

Ch: the number of tracks Ns in the channel region
: Number of tracks secured as an empty area for passing inter-block wiring Ti: track number Y of signal i
i: track y coordinate of signal i
Tp: Track position number in empty area setting channel When Ti <0
Yi = Ti + Ch + 1
When Ti> 0

Yi = Ti
When Yi> Tp
Yi = Y
i + Ns
When Yi ≦ Tp
Yi = Yi Based on this calculation formula, by updating the track y coordinate of the main table 69, it is possible to set an empty area in detail in the block.

As described above, the number of unwired lines can be reduced by incorporating the invalid area on the chip into the block and setting the empty area for passing the unwired line in the block. Furthermore, the number of wirings that bypass the outside of the block can be reduced, and the long wiring length can be reduced.

[0037]

According to the present invention, by setting the invalid area existing on the chip as an empty area inside the block, the inter-block wiring can be avoided while avoiding the wiring congestion point which causes the non-wiring in the inter-block wiring processing. Since the wiring route of is searched, unwiring can be reduced. Further, since the empty area for wiring a specific unwired can be freely set, the unwired can be surely reduced. Further, since the block terminals can be connected without bypassing the outside of the block, the wiring length can be shortened.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a layout block.

FIG. 2 is a flowchart of a block layout and wiring process.

FIG. 3 is a wiring track allocation diagram before setting an empty area.

FIG. 4 is a wiring track allocation diagram after setting an empty area.

FIG. 5 is an empty area generation flowchart.

FIG. 6 is a diagram showing the cause of non-wiring of wiring between blocks.

FIG. 7 is an unwiring countermeasure diagram.

FIG. 8 is a flow chart of a chip layout.

FIG. 9 shows an example of an unwired terminal display.

FIG. 10 shows an example of a free area setting instruction.

[Explanation of symbols]

21-23: Cell rows forming blocks 31-34: Free areas provided in channel areas 41-44: Channel areas forming block (inter-cell terminal wiring area) 61: Detailed wiring processing 62: Main line data creation Process 63: Track allocation process 64: Free area generation process 65: Line segment data creation process of wiring route 68: Free space setting instruction table 69: Main line table 70: In-block placement / wiring process 72: Block placement Processing 73: Inter-block wiring processing 75: Free area setting instruction processing 97: Main line y coordinate calculation processing

Claims (4)

[Claims] 1. When designing a layout of a semiconductor integrated circuit composed of a plurality of blocks using a computer having a memory device, the computer: a) inputs logic circuit data of the integrated circuit from the memory device. B) wiring in each of the blocks based on the logic circuit data, c) wiring between the blocks based on the logic circuit data, d) wiring between the blocks When unwiring occurs, an empty area is created in the designated wiring area in the block through which the unwiring is passed, e) The unwiring is passed through the empty area created in step d), and f). A layout method of a semiconductor integrated circuit, wherein the layout result obtained in steps b) to e) is output to the storage device. 2. A layout method of a semiconductor integrated circuit, wherein the block according to claim 1 comprises a plurality of cell columns. 3. The semiconductor integrated circuit according to claim 1, wherein steps b) and c) are re-executed when there is no free area in the vicinity of the block through which the unwiring passes. Circuit layout method. 4. The layout method according to claim 2, wherein
A method for laying out a semiconductor integrated circuit, characterized in that main lines parallel to the cell columns are generated in the wiring region between the cell columns by the number corresponding to the unwired lines.