JPH02165654A - Semiconductor integrated circuit design changing method - Google Patents

Abstract

PURPOSE:To make it possible to efficiently perform addition of wiring which has occurred after finish of layout by seeing to it that the hand designation of conversation type and the automatic processing cooperate with each other. CONSTITUTION:In the treatment to designate the compaction region to do additional wiring, a compaction region near the position where additional wiring is desired on a semiconductor integrated circuit board is designated. By this designation, in the treatment to do subsequent compaction, the compaction is done only in the designated region. Also, in the treatment to designate the compaction line to do additional wiring, a line along the course where additional wiring is wished on the semiconductor integrated circuit board is designated. The designation of the compaction region and the designation of the separation line are done using a conversation-type processor such as a graphic editor, etc. The wiring to a scaled-down wiring region which is determined by this compaction treatment is done by automatic wiring by a maze method.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention provides a method for changing a design in a layout system for a semiconductor integrated circuit, and particularly a method for modifying a layout in accordance with a system change that occurs after the completion of a layout design. It concerns the method of changing the layout design.

(Prior Art) Automatic placement and wiring systems are often used for the layout of large-scale semiconductor integrated circuits. By using this automatic placement and wiring system, the layout of large-scale semiconductor integrated circuits can be implemented relatively easily and in a short time. When the layout is completed, evaluation/verification is performed to determine whether the layout result satisfies the design standards and whether the predicted circuit characteristics satisfy the specifications. Such evaluation/verification is performed on the system design side, which is the first half of the semiconductor integrated circuit design process, and if the layout result does not satisfy the requirements, the layout result needs to be changed.

Additionally, system design results are evaluated/verified, and layout results may need to be changed in response to changes in the system. As shown in Figure 13, the relationship between system design and layout design is that layout design is not done after system design is completed;
Both are being done in parallel. Therefore, there is a need for a method for efficiently reflecting design change requests from the system designer in the layout results and implementing layout changes while minimizing the impact on the layout results that have been evaluated/verified.

In the past, several methods have been tried and implemented to make the above design changes. Here, methods for adding wiring and adding cells related to the present invention will be described.

First, the most common method is to manually add wiring and cells to the layout results using an interactive processing device such as a graphic editor. This method of using an interactive processing device such as a graphic editor requires the designer to spend a great deal of time and effort, and since the layout results are corrected manually, there is a possibility that the correction results may contain errors. expensive. In addition, there is a method for automatically placing and routing the entire semiconductor integrated circuit again, ignoring the previous layout results, using connection information with added wiring and cells after design changes, and a method for automatically placing and routing parts of the semiconductor integrated circuit. There is a way to redo the wiring. However, with this method, all or part of the computer processing time used when designing the previous layout and the efforts made to evaluate/verify the previous layout results are wasted.

In addition to this, there is also a method of using an automatic wiring method called a rip-up router for connecting wiring that remains unconnected during automatic wiring. However, in this method, the existing wiring that is an obstacle is removed, the wiring is added, and the same process is repeated using the removed existing wiring as a newly added wiring, so there is a risk that the changed portion of the layout result will be expanded.

Furthermore, there is a method to partially modify using a design change method that automatically changes in response to system changes, but in order to secure the location of additional cells, it is necessary to search for a place to add a cell and replace the already placed cell. It was necessary to move.

As described above, in a method that accommodates layout design changes, it is necessary to prevent the introduction of errors, save the number of steps, minimize the number of changed parts, and minimize the influence on circuit characteristics.

(Problems to be Solved by the Invention) As described above, in conventional layout systems, changes in placement and wiring that occur after the layout is completed are handled manually using an interactive processing device such as a graphic editor, There were methods such as redoing automatic placement and routing and using a rip-up router. However, the method using a graphic editor or the like requires the designer to spend a great deal of time and effort, and there is a problem in that the correction results are likely to contain errors. In addition, the method of performing automatic placement and routing again has the problem that all or part of the computer processing time for the previous layout and the evaluation/verification efforts made for the previous layout results are wasted. Ta. Furthermore, the method using a rip-up router has the problem that the layout change area may be enlarged.

Furthermore, with conventional cell adding techniques, whether automatic or manual, it is difficult to find a place to add a cell. For example, as shown in Figure 14, the gaps are narrow and sparse, and there is no suitable space for the size of the additional cell, so you must move the already placed cells to another location to create space for the additional cell. First, it took a lot of time to calculate the cell to move and the position to move.

The present invention has been made in consideration of the above circumstances, and its purpose is to modify the layout results performed by an automatic layout system in response to changes in system design, and in particular to add wiring and cells. The goal is to provide a means to do so efficiently and effectively.

[Structure of the Invention] (Means for Solving the Problems) The gist of the present invention is to provide a layout result of a semiconductor integrated circuit realized by arranging and wiring cells on a semiconductor substrate so as to satisfy a predetermined function. The object of the present invention is to provide a processing method for adding wiring and adding cells in accordance with desired circuit changes.

In other words, in the first configuration of the present invention, when adding wiring to modify the layout result due to a desired circuit change,
To secure the area necessary for newly added wiring,
Compaction of existing wiring is performed within a manually designated nearby area that includes the position on the semiconductor substrate through which the newly added wiring should pass.

The second configuration of the present invention is a line (manually specified) through which the newly added wiring is expected to pass on the semiconductor substrate in order to secure the area necessary for the newly added wiring.
This involves compacting existing wiring to expand the area required for newly added wiring.

Further, the third configuration of the present invention is to prepare for circuit changes by taking into consideration the area for adding cells in advance and creating gaps of a size suitable for adding cells at key points.

Furthermore, the fourth configuration of the present invention is to leave an area suitable for cell addition as a dummy wiring prohibited area, and perform wiring in such a way that this area is not blocked by wiring.

(Operation) The present invention achieves the following through cooperation between conversational manual specification and automatic processing.
The purpose is to efficiently and effectively add wiring that occurs after the layout is completed. In other words, compaction, which cannot be performed efficiently manually and is prone to errors, can be performed automatically, but it also requires empirical judgment to determine which parts, in which directions, and to what extent, to compactify as desired. Parts such as whether additional wiring can be added are left to manual designation. Therefore, according to the present invention, when wiring is added after the layout of a semiconductor integrated circuit is completed, it is possible to prevent the introduction of errors, save the number of design steps, and minimize the number of changed parts to minimize the effect on circuit characteristics. It becomes possible.

Furthermore, according to the present invention, when adding a cell, a large enough area without cells is secured to place the cells at key points on the chip, so the position of the added cell can be adjusted. can be determined without moving the already placed cells. In addition, when a cell is added using this method, there is no wiring in that area as a prohibited area for dumrlY during wiring, so there is no need to move existing wiring to secure a place for cell placement. addition·
Only the wiring of the changed signal needs to be corrected, which speeds up the processing.

(Example) Hereinafter, the present invention will be explained in detail using the drawings.

First, a first embodiment in which wiring is added will be described with reference to FIGS. 1 to 5.

FIG. 1 shows a processing flow of a first embodiment of the present invention. 1st
In the figure, S1 to s8 are processing steps.

FIG. 2 is a diagram showing a semiconductor integrated circuit device implementing the present invention. In FIG. 2, 1 is a functional cell, and 2 is a functional cell row formed by arranging functional cells 1 in a row. Also,
3 is an input/output cell for exchanging signals with the outside of the semiconductor integrated circuit device.

FIG. 3 shows an example of a layout result after completion of layout design using channel wiring. In Figure 3,
The wiring between each functional cell is indicated by thick diagonal lines, and the 0 mark indicates a through hole connecting each wiring layer. The X mark indicates the terminal of each functional cell. The case of adding a wiring connecting terminal A and terminal B indicated by circles in the same figure will be explained below along with the processing flow of FIG. 1.

First, the process of inputting layout results (step sl)
At , the layout result of the entire semiconductor integrated circuit including the layout result portion shown in FIG. 3 is input.

Next, in the process of specifying a compaction area for additional wiring (step s2), a compaction area near a desired position on the semiconductor integrated circuit board for additional wiring is specified. With this designation, in the subsequent compaction process (step s4), compaction is performed only within the designated area. Furthermore, in the process of specifying a compaction separation line for additional wiring (step s3), a line along a desired route for additional wiring on the semiconductor integrated circuit board is specified. In this embodiment, this line is called a compaction separation line. This specification causes subsequent compaction processing (
In step s4), compaction is performed so as to expand the specified compaction separation line.

In other words, compaction is performed in the opposite direction around the compaction separation line. This step 2 and
Specifying the compaction area in step 3 and
The separation line is specified using an interactive processing device such as a graphic editor. FIG. 4 shows a state in which the compaction area and separation line are specified. In FIG. 4, a region R surrounded by a dotted line indicates a compaction region, and a dashed-dotted line indicates a compaction separation line.

The compaction performed in step S4 refers to the function of determining the connection relationship of each functional cell and the position of wiring and through holes so that the design rules are satisfied and the area required for wiring is as small as possible. . However, in the present invention, since wiring is automatically added to the reduced wiring area (step s5), the area of the entire semiconductor integrated circuit or the number of wiring tracks does not change. In this example,
In step S5, automatic wiring is performed using, for example, a maze method.

Next, it is determined whether it is possible to add the wiring (step s6), and if it is possible, the layout result is output (step s8), and the process flow of the present invention ends. Conversely, if it is not possible, create a new compaction area/
Input whether or not to perform the process of specifying a separation line (step $7); if so, the process returns to step s2; if not, the process ends.

FIG. 5 shows a state in which wiring connecting terminals A and B is added to the area expanded by the compaction performed in step 4.

As shown in FIG. 5, the processing procedure shown in FIG. 1 makes it possible to add wiring while minimizing the influence on previous layout results.

Next, a second embodiment of the present invention for adding cells will be described with reference to FIGS. 6 and 7. FIG. 6 shows a flowchart of the present invention. After the start, the arrangement order (relative position) of the cells in the cell column according to the logic design description is determined (A1). Next, the absolute position of the cell is determined by taking into account the area occupied by the cell and the area of the chip. Normally, the area occupied by cells is somewhat smaller than the area of the chip, so there are gaps between cells. This is done by inserting gaps here and there on the width while determining the position of the cell (
A2). The steps up to this point are placement processing that takes the additional area into consideration.

The following is a wiring in which the additional area is a duly wiring prohibited area. A search is performed for free space (A3). If all free areas have not been searched (A4), a free area is obtained (A5), and it is determined whether the area is sufficient for placing a cell (A6). If there is enough space to place a cell, use that free space as dummy
A7) If the wiring is prohibited area, if the area is not sufficient,
Repeat the search for free space again. After completing the search for all free areas, wiring processing is performed (A8).

At this point, the iaud is finished once and the result is obtained, but
If there is an additional request (A9), the wiring prohibited area of ``dull'' is searched, and the insertion position for the cell for which the additional request is made is searched (AIO). Since there are no other cells or wiring in this area, additional cells can be placed easily. Cells are added, placement (All) and wiring (A12) are performed again to create a layout, and the process is repeated until there are no additional requests, and the process ends.

FIG. 7 is a diagram of a layout along the flow of the method of the present invention. 11 is a functional cell, 2 is a cell column, 4 is a wiring area, 5
is an additional cell area, 6 is an added cell, 7 is a wiring route,
Reference numeral 8 indicates a wiring route that has been changed or added due to the added cell. FIG. 7(a) is a diagram of the arrangement in consideration of the additional area. The dotted line portion on the cell column 2 is the additional cell area 4. FIG. 7(b) is a diagram in which wiring is performed using an empty area on cell column 2 as an aussy wiring prohibited area. Figure 7 (
C) is a diagram in which cells are arranged in the additional area 4 in response to an additional request. The diagonally shaded portion on cell column 2 is added cell 5. FIG. 7(d) is a diagram of the wiring that has been changed due to the additional request. - The route indicated by the dashed dotted line is the route of the wiring changed and added by the added cell.

Next, the present invention regarding processing of unnecessary cells will be described in detail with reference to FIGS. 8 to 12. FIG. 9 is an example of a circuit diagram for explaining this embodiment. An embodiment will be described for a case where a design change is made in this circuit diagram and the cell indicated by 10 in the diagram becomes unnecessary.

In this embodiment, as shown in Fig. 10, when an unnecessary cell is recognized, the output signal of the unnecessary cell is separated from the cell (cell 13 in the figure) that received that signal as input, and the output of the unnecessary cell is cut off. release. As a result, the unnecessary cells no longer function on the circuit, and the same result as if they had been deleted can be obtained.

However, since the input to the unnecessary cells remains, the output loads of the cells (21 and 22) that were supplying signals to the unnecessary cells have not changed compared to before the modification.

In addition, as another embodiment of the present invention, if there is no need to consider the load of cells 21 and 22, a method of deleting all unnecessary cells and their input/output signals as shown in FIG. 11 may be considered. It will be done.

In either of the above cases, it is necessary to connect an appropriate input signal to cell 13, which was supplied with a signal from an unnecessary cell, because it will no longer perform its intended function if the input signal is left as is. be. In the examples shown in FIGS. 10 and 11, since the cell 13 is a NOR circuit, rules are set so as to maintain the NOR function, and the cell 13 is connected so as to always give a constant value "0".

Further, as another example of the connection rule, in FIG. 12, the input signal is set so that a signal equal to the other input is input. As for these connection change rules, connection patterns are set in advance according to the functions of the cell, and when a signal is deleted, an appropriate pattern is extracted from the rules and connection changes are made.

The layout pattern correction process required in connection with such connection changes consists of deleting patterns in unnecessary cells and changing connections of cells that use the signals as input, but the former is extremely elegant. The latter involves modifying the layout pattern in a local area near the cell to be modified, and can be easily and quickly processed by employing a maze search method or the like.

As described above, in the conventional method, all the processing has to be done manually, but in this embodiment, as shown in the flowchart of Fig. 8, if the signal connection rules are stored in the system in advance, , it becomes possible to automatically delete and reconnect signals by simply specifying unnecessary cells.

[Effects of the Invention] As explained above, according to the present invention, design change requests from the system design side that occur after the layout design is completed can be handled as follows:
This can be reflected in layout design changes efficiently and effectively. In addition, in this layout design change, the information of the existing layout is utilized to the maximum and there are very few changes in information, so it is possible to reduce the effort required to re-evaluate/verify the layout change result.

Furthermore, according to the present invention, even if cells are added due to circuit changes, the circuit can be changed without moving cells that have already been placed or wires that have been routed, and automatic placement and routing can be performed from the beginning. The trouble of re-execution can be saved, and the desired circuit can be obtained without wasting computer time and layout results.

[Brief explanation of the drawing]

FIG. 1 is a processing flow showing a first embodiment of the present invention, FIG. 2 is a diagram showing the configuration of a semiconductor integrated circuit device in which the first embodiment of the present invention is implemented, and FIG. 3 is a diagram showing the addition of wiring. Figure 4 shows the previous layout result, Figure 4 shows the compaction area and compaction separation line specified, and Figure 5 shows the layout change result after adding wiring after compaction processing. , FIG. 6 is a diagram showing the processing flow of the second embodiment of the present invention, FIG. 7 is a diagram showing the layout change when adding cells, and FIG. 8 is a diagram showing the design change according to the third embodiment of the present invention. 9 is a diagram showing an example of a circuit in which unnecessary cells have been generated due to a design change. FIG. 10 is a diagram showing an example of a design change according to the third embodiment. A diagram showing an example of unnecessary cell deletion according to the embodiment, FIG. 12 is a circuit diagram in which unnecessary cells are processed using other rules, FIG. 13 is a diagram showing the relationship between system design and layout design, and FIG. 14 2 is a diagram illustrating a layout in a case where the area to add cells is narrow and the cell addition area must be created by moving cells. 81-S8... Processing means of the present invention, 1... Functional cell, 2... Functional cell row, 3... Input/output cell, A-B.
...Additional wiring terminal, R...Compaction area, PA L...Compaction separation line, 4...Wiring area, 5
...Added cell area, 6...Added cell, 7...
- Wiring route, 8... Wiring route changed and added due to additional cells, 10... Unnecessary cells, 13... Cells supplied with signals from unnecessary cells, 21.22...
A cell that supplies signals to unnecessary cells. Applicant's agent Patent attorney Takehiko Suzue No. 2 rM Fig. 1 Fig. Fig. Lower mold charge 2 Le 1 Moss setting Fig. 9 Fig. Fig.

Claims (2)

[Claims] (1) In a method of designing a semiconductor integrated circuit that realizes a desired circuit by arranging and wiring cells that realize pre-designed unit functions on a semiconductor substrate,
When adding wiring to modify the layout of an already designed semiconductor integrated circuit according to desired circuit changes,
To secure the area necessary for newly added wiring,
Design of a semiconductor integrated circuit characterized by securing an area for additional wiring by compacting existing wiring within a specified vicinity area centered on the position of the newly added wiring on the semiconductor substrate. Modification method. (2) In a method of designing an integrated circuit that realizes a desired circuit by arranging and wiring cells that realize pre-designed unit functions on a substrate, when wiring, an area suitable for adding cells is A method for changing the design of a semiconductor integrated circuit, characterized in that wiring is performed using a dummy as a prohibited wiring area, and the design can be changed using an area for adding cells.